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* arm: odroid: enable/disable usb host phy for exynos4412Suriyan Ramasami2014-11-17-0/+34
| | | | | | | | Enable/disable the usb host phy on the odroid U/X2 boards which are based on the Exynos4412 SOC. Signed-off-by: Suriyan Ramasami <suriyan.r@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos: dts: Correct USB vbus-gpio numbering for SnowSjoerd Simons2014-11-17-2/+2
| | | | | | | | | | | | The current vbus GPIOs on snow make very little sense, their number is far above the maximum. As a result, USB doesn't work on snow. Correct the GPIO numbering so they match the current scheme for exynos5. Tested both EHCI and XHCI to correctly work after this change. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Peach-Pi: Use the enhanced usb_copy() prototypeVadim Bendebury2014-11-17-2/+8
| | | | | | | | | | | | | Exynos5800 IROM has a different, from 5250 and 5420, prototype of the usb_copy() function. Luckily the earlier version did not expect any arguments, which means the same code could be used with old and new SoCs, the old ones just ignoring the arguments. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5: ddr3: Choose between single or double channel configAkshay Saraswat2014-11-17-0/+10
| | | | | | | | | | | | Add a 4G configuration and choose it based on the number of banks declared in config file. A board with 4 SDRAM banks declared (as per CONFIG_NR_DRAM_BANKS) will end up with the 2G confiuration. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* DMC: Exynos5: Enable update mode for DREX controllerAlim Akhtar2014-11-17-0/+20
| | | | | | | | | | | | | | | | As per Exynos5800 UM ver 0.00 section 17.13.2.1 CONCONTROL register bit 3 [update_mode], Exynos5800 does not support the PHY initiated update. And it is recommanded to set this field to 1'b1 during initialization. This patch sets this bit. Applying MC-initiated mode makes DDL tracking ON, that helps in compensate MIF voltage variation. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Config: Exynos5800: Enable build for Peach-PiAkshay Saraswat2014-11-17-1/+6
| | | | | | | | | | | | | This adds following things : - New config and defconfig for Peach-Pi board. - Alterations in Kconfig and MAINTAINERS. - Addition of CONFIG_EXYNOS5800. - ADdition of exynos5800-peach-pi in dts list. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5800: Add DTS for new board Peach-PiAkshay Saraswat2014-11-17-1/+159
| | | | | | | | | | | | We have a new board Peach-Pi similar to Peach-Pit. Peach-Pi differs from Peach-Pit in configuration factors like display resolution, memory size, SoC version etc. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5800: Introduce new proid for Exynos5800Akshay Saraswat2014-11-17-14/+23
| | | | | | | | | | | | | | This patch intends to add a new proid for Exynos5800 which is a variant of Exynos5420. Product id for Exynos5800 is 0x5422. Both Exynos5420 and Exynos5800 are pin to pin compitable. This gives us an advantage of reusing Exynos5420 clock, pinmux, memory and other settings. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-11-14-5/+8
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| * powerpc/mpc83xx: Zero boot_flags arg for calling board_init_f()Valentin Longchamp2014-11-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The argument boot_flags of board_init_f() is not used at all in the powerpc specific board.c init sequence. Now with the generic init sequence, this boot_flags arg is used by board_init_f(). This patch sets the r3 register that is used to pass the boot_flags argument from the start.S board_init_f() call to 0 prior to the function call to avoid unknown content to end up in gd->flags. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * powerpc/mpc85xx: Use IFC accessor functionPrabhakar Kushwaha2014-11-14-4/+4
| | | | | | | | | | | | | | | | | | | | IFC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of IFC IP. So use IFC acessor functions instead of in_be32(). Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * 85xx/b4:Correct USB DR controller liodn entryramneek mehresh2014-11-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | LIODN entry for B4860/B4420 mentions USB controller as "mph" insread of "dr". This results in PAMU not permitting bus transactions for USB DR controller on B4860 resulting in USB function failure. Replacing "fsl-usb2-mph" with "fsl-usb2-dr" allows USB DR controller bus transactions Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: Sethi Varun-B16395 <Varun.Sethi@freescale.com> Reviewed-by: Sun Yusong-R58495 <yorksun@freescale.com>
| * driver/net/fm/memac_phy: set NEG bit for external MDIOsShaohui Xie2014-11-14-0/+1
| | | | | | | | | | | | | | | | | | | | NEG bit default is '1' for external MDIOs as per FMAN-v3 RM, but on some platforms, e.g. T2080QDS, this bit is '0', which leads to MDIO failure on XAUI PHY, so set this bit definitely to align with the RM. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * Fman/mEMAC: mEMAC fix for 10G MAC and PHYShaohui Xie2014-11-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | 1. use Payload length check disable when enable MAC; 2. add XGMII support for setting MAC interface mode; 3. only enable auto negotiation for Non-XGMII mode; 4. return 0xffff if clause 22 is used to read 10G phy_id; Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-By: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-11-14-5/+15
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| * arm: mx6: add support for TBS2910 Matrix ARM miniPCSoeren Moch2014-11-13-0/+4
| | | | | | | | | | | | | | Add initial support for TBS2910 Matrix ARM miniPC. Support includes MMC, Ethernet, UARTs, HDMI, USB, SATA, PCI, I2C, RTC. Signed-off-by: Soeren Moch <smoch@web.de>
| * mx6: video_skip: Fix crash on NULL pointerNikolay Dimitrov2014-11-13-1/+5
| | | | | | | | | | Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg> Cc: Stefano Babic <sbabic@denx.de>
| * kconfig: imx6: add SUPPORT_SPLJohn Tobias2014-11-13-0/+1
| | | | | | | | | | | | | | add SUPPORT_SPL feature for iMX6 SabreSD. It need to use mx6sabresd_spl_defconfig to compile it. Signed-off-by: John Tobias <john.tobias.ph@gmail.com>
| * arm: imx: make bmode command work with SPL/U-Boot comboNikita Kiryanov2014-11-12-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bmode command forces the SoC to use a specific boot device by writing its boot mode into SRC_GPR9, and notifying the SoC of the change using SRC_GPR10[28] bit: if the bit is on, bootROM uses the value in SRC_GPR9 instead of SRC_SMBR1 to determine the boot device. SPL on the other hand is oblivious to this distinction, so once the bootROM loads SPL from the device configured in SRC_GPR10, SPL will attempt to load U-Boot from the device configured in SRC_SMBR1, which is not updated by the bootROM to the value in SRC_GPR9. The result is that the selected boot device is not used across all the boot stages. Update spl_boot_device() to look at gpr9 when necessary. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Troy Kisky <troy.kisky@boundarydevices.com> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Heiko Schocher <hs@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini2014-11-13-175/+1455
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| * | sun6i: ehci: Add sun6i ehci supportHans de Goede2014-11-13-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | Add support for the 2 ehci controllers found on the sun6i (A31) soc. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Marek Vasut <marex@denx.de>
| * | sun6i: Poke magic sram controller register to avoid cache issuesHans de Goede2014-11-13-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Without this the cache will only work in write-through mode, and as soon as it is put in write-back mode things break. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | sun6i: Add dram initialization codeHans de Goede2014-11-13-3/+804
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add full support for dram initialization, using a fixed clock and autodetection of the memory organization (numbers of channels, bus-width, etc.). This is based on dram_sun6i.c and dram.h from u-boot in the Allwinner A31 SDK, extended with extra initialization sequences and the autodetect algorithm from boot0. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | sun4i: Rename dram files to dram_sun4i.xHans de Goede2014-11-13-168/+187
| | | | | | | | | | | | | | | | | | | | | In preparation for adding sun6i dram support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | sun6i: Add cpucfg register definitionsHans de Goede2014-11-13-3/+71
| | | | | | | | | | | | | | | | | | | | | Not used atm, for future use (e.g. PSCI). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | sun6i: Add clock functions needed for SPL / DRAM initHans de Goede2014-11-13-1/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock_init_safe and clockset_pll5 functions, as these are needed for SPL support resp. DRAM init (which is needed for SPL too). Also add some extra clock register constant defines. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | sun6i: Add new p2wi controller driverOliver Schinagl2014-11-13-0/+261
| |/ | | | | | | | | | | | | | | | | | | | | The A31 uses a new push-pull two wire interface, which features higher transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8 bytes each time, this driver will only see very little use and thus is limited to single byte transmission only. Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-11-13-143/+11
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| * | ARM: remove unused CPU directoryMasahiro Yamada2014-11-13-132/+0
| | | | | | | | | | | | | | | | | | | | | There is no board with CPU "arm_intcm". Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
| * | ARM: cache-cp15: Use more accurate typesThierry Reding2014-11-12-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | size_t is the canonical type to represent variables that contain a size. Use it instead of signed integer. Physical addresses can be larger than 32-bit, so use a more appropriate type for them as well. phys_addr_t is a type that is 32-bit on systems that use 32-bit addresses and 64-bit if the system is 64-bit or uses a form of physical address extension to use a larger address space on 32-bit systems. Using these types the same API can be implemented on a wider range of systems. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | ARM: cache_v7: Various minor cleanupsThierry Reding2014-11-12-7/+7
| |/ | | | | | | | | | | | | | | | | | | | | Remove two gratuituous blank lines, uses u32 (instead of int) as the type for values that will be written to a register, moves the beginning of the variable declaration section to a separate line (rather than the one with the opening brace) and keeps the function signature on a single line where possible. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | arm: mx6: Fix missing Kconfig option for NovenaMarek Vasut2014-11-13-0/+1
| | | | | | | | | | | | | | | | | | | | | | Add two missing Kconfig options for Novena and drop the SPL from the Novena config. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Sean Cross <xobs@kosagi.com> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* | Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-11-13-0/+28
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| * | kconfig: zynq: Add ZYBO boardPeter Crosthwaite2014-11-11-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a defconfig and Kconfigury for the Digilent ZYBO board. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | arm: dts: zynq: Add digilent ZYBO board dtsPeter Crosthwaite2014-11-11-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | It's a Zynq board similar in design to the currently supported ones. 512MB of RAM and UART1 is used. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | kconfig: arm: move "armv8" define to arch/arm/KconfigMasahiro Yamada2014-11-13-8/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 2e07c249a67e (kconfig: arm: introduce symbol for ARM CPUs) collected the default values of CONFIG_SYS_CPU into arch/arm/Kconfig. This commit moves "armv8" to there for consistency. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Georges Savoundararadj <savoundg@gmail.com>
* | | kconfig: arm: select CPU_V7 for some new boardsMasahiro Yamada2014-11-13-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds "select CPU_V7" for some new boards that were not covered by commit 2e07c249a67e (kconfig: arm: introduce symbol for ARM CPUs). Redundant "SYS_CPU" defines and "string" directives should be removed. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Georges Savoundararadj <savoundg@gmail.com>
* | | powerpc: remove orphaned boards mcc200 and prs200Nikita Kiryanov2014-11-12-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mcc200 and prs200 are old and have no maintainer. Remove the boards. This also removes the mcc200 specific 1bpp BMP support from common/lcd.c Cc: Wolfgang Denk <wd@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: York Sun <yorksun@freescale.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-11-11-0/+900
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| * | arm: socfpga: Add socfpga_spim_enable() to reset_manager.cStefan Roese2014-11-07-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function will be needed by the upcoming Designware master SPI driver. As the SPI master controller is held in reset by the current Preloader implementation. So we need to release the reset for the driver to communicate with the controller. This function is called from arch_early_init_r() if the SPI driver is enabled. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de>
| * | arm: socfpga: Add DW master SPI clock to clock_manager.cStefan Roese2014-11-07-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function will be needed by the upcoming Designware master SPI driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de>
| * | arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates targetStefan Roese2014-11-07-0/+868
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch includes the latest DT sources for socfpga from the current Linux kernel. And enables CONFIG_OF_CONTROL for the new build target "socfpga_socrates" (the EBV SoCrates board) to make use of this new DT support. Until this patch, the only SoCFPGA U-Boot target in mainline is "socfpga_cyclone5". This build target is not (yet) changed to support DT. So nothing changes for this target. Even though the long-term goal should be to move all SoCFPGA targets over to DT. One of the reasons to enable DT support in SoCFPGA is, that I need to support multiple different SPI controllers for this platform. This is the QSPI Cadence controller and the Designware SPI master controller. Both are implemented in the SoCFPGA. And enabling both controllers is only possible by using the new driver model (DM). The DM SPI code only supports DT based probing. So it was easier to move SoCFPGA to DT than to add the (deprecated) platform-data based probing to the DM SPI suport. Note that the image with the dtb embedded is u-boot-dtb.img. This needs to be used now for those DT enabled boards instead of u-boot.img. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2014-11-11-72/+158
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| * | | ARM: UniPhier: call pin_init() also in the normal bootMasahiro Yamada2014-11-12-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_UNIPHIER_SERIAL has been moved to Kconfig and it is defined in ./.config but not in spl/.config, so pin_init() should be called from the normal image so that UART works correctly. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | ARM: UniPhier: consolidate board_postclk_init() functionMasahiro Yamada2014-11-12-50/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit merges arch/arm/cpu/armv7/uniphier/ph1-*/board_postclk_init.c to arch/arm/cpu/armv7/uniphier/board_postclk_init.c Because PH1-Pro4 does not have the BCU block, add __weak to bcu_init(). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | ARM: UniPhier: add set_pinsel macro for use in assembly codeMasahiro Yamada2014-11-12-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function sg_set_pinsel is useful for switching I/O pins but it can be only used in C code. This commit adds a simple macro that is available in asm code. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | usb: UniPhier: add UniPhier on-chip EHCI host driver supportMasahiro Yamada2014-11-12-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support EHCI host driver used on Panasonic UniPhier platform. Since Device Tree is not supported on UniPhier yet, the base address of USB cores are passed from board files (platdevice.c). TODO for me: Move the base address to device trees. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de>
| * | | ARM: UniPhier: add MIO register fileMasahiro Yamada2014-11-12-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds register defines of MIO (Media I/O) block of UniPhier platform. This file is necessary to control the reset signals of the USB cores. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | ARM: UniPhier: add EHCI host pin settings for PH1-Pro4Masahiro Yamada2014-11-12-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | These IO pins are necessary for port power control and over current detect. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | ARM: UniPhier: move DDR related configuration to KconfigMasahiro Yamada2014-11-12-19/+27
| | | | | | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
generated by cgit v1.1 at 2024-11-06 23:51:28 +0000