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| * | x86: baytrail: Add internal UART ASL descriptionBin Meng2016-05-23-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BayTrail integrates an internal ns15550 compatible UART (PNP0501). Its IRQ is hardwired to IRQ3 in old revision chipset, but in newer revision one IRQ4 is being used for ISA compatibility. Handle this correctly in the ASL file. Linux does not need this ASL, but Windows need this to correctly discover a COM port existing in the system so that Windows can show it in the 'Device Manager' window, and expose this COM port to any terminal emulation application. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: acpi: Remove header length check when writing tablesBin Meng2016-05-23-16/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before moving 'current' pointer during ACPI table writing, we always check the table length to see if it is larger than the table header. Since our purpose is to generate valid tables, the check logic is always true, which can be avoided. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: acpi: Remove the unnecessary checksum calculation of DSDTBin Meng2016-05-23-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | The generated AmlCode[] from IASL already has the calculated DSDT table checksum in place. No need for us to calculate it again. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: acpi: Switch to ACPI mode by ourselves instead of requested by OSPMBin Meng2016-05-23-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per ACPI spec, during ACPI OS initialization, OSPM can determine that the ACPI hardware registers are owned by SMI (by way of the SCI_EN bit in the PM1_CNT register), in which case the ACPI OS issues the ACPI_ENABLE command to the SMI_CMD port. The SCI_EN bit effectively tracks the ownership of the ACPI hardware registers. However since U-Boot does not support SMI, we report all 3 fields in FADT (SMI_CMD, ACPI_ENABLE, ACPI_DISABLE) as zero, by following the spec who says: these fields are reserved and must be zero on system that does not support System Management mode. U-Boot seems to behave in a correct way that the ACPI spec allows, at least Linux does not complain, but apparently Windows does not think so. During Windows bring up debugging, it is observed that even these 3 fields are zero, Windows are still trying to issue SMI with hardcoded SMI port address and commands, and expecting SCI_EN to be changed by the firmware. Eventually Windows gives us a BSOD (Blue Screen of Death) saying ACPI_BIOS_ERROR and refuses to start. To fix this, turn on the SCI_EN bit by ourselves. With this patch, now U-Boot can install and boot Windows 8.1/10 successfully with the help of SeaBIOS using legacy interface (non-UEFI mode). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Use high_table_malloc() for tables passing to SeaBIOSBin Meng2016-05-23-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | Now that we already reserved high memory for configuration tables, call high_table_malloc() to allocate tables from the region. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Reserve configuration tables in high memoryBin Meng2016-05-23-3/+8
| | | | | | | | | | | | | | | | | | | | | When SeaBIOS is on, reserve configuration tables in reserve_arch(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Unify reserve_arch() for all x86 boardsBin Meng2016-05-23-27/+12
| | | | | | | | | | | | | | | | | | | | | | | | Instead of asking each platform to provide reserve_arch(), supply it in arch/x86/cpu/cpu.c in a unified way. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Prepare configuration tables in dedicated high memory regionBin Meng2016-05-23-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently when CONFIG_SEABIOS is on, U-Boot allocates configuration tables via normal malloc(). To simplify, use a dedicated memory region which is reserved on the stack before relocation for this purpose. Add functions for reserve and malloc. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Compile coreboot_table.c only for SeaBIOSBin Meng2016-05-23-1/+1
| | | | | | | | | | | | | | | | | | | | | coreboot_table.c only needs to be built when SeaBIOS is used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Fix up PIRQ routing table checksum earlierBin Meng2016-05-23-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PIRQ routing table checksum is fixed up in copy_pirq_routing_table(), which is fine if we only write the configuration table once. But with the SeaBIOS case, when we write the table for the second time, the checksum will be fixed up to zero per the checksum algorithm, which is caused by the checksum field not being zero before fix up, since the checksum has already been calculated in the first run. To fix this, move the checksum fixup to create_pirq_routing_table(), so that copy_pirq_routing_table() only does what its function name suggests: copy the table to somewhere else. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Call board_final_cleanup() in last_stage_init()Bin Meng2016-05-23-18/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present board_final_cleanup() is called before booting a Linux kernel. This actually needs to be done before booting anything, like SeaBIOS, VxWorks or Windows. Move the call to last_stage_init() instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: qemu: rename qemu/acpi_table.cMiao Yan2016-05-23-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | Rename qemu/acpi_table.c to qemu/e820.c, because ACPI stuff is moved to qfw core, this file only contains code for installing e820 table. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | cmd: qfw: bring ACPI generation code into qfw coreMiao Yan2016-05-23-209/+0
| | | | | | | | | | | | | | | | | | | | | | | | Loading ACPI table from QEMU's fw_cfg interface is not x86 specific (ARM64 may also make use of it). So move the code to common place. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h]Miao Yan2016-05-23-4/+4
| | | | | | | | | | | | | | | | | | | | | Make file names consistent with CONFIG_QFW and CONFIG_CMD_QFW Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: qemu: add comment about qfw register endiannessMiao Yan2016-05-23-1/+8
| | | | | | | | | | | | | | | | | | | | | This patch adds some comments about qfw register endianness for clarity. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: qemu: move x86 specific operations out of qfw coreMiao Yan2016-05-23-1/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original implementation of qfw includes several x86 specific operations, like directly calling outb/inb and using some inline assembly code which prevents it being ported to other architectures. This patch adds callback functions and moves those to arch/x86/ Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: qemu: split qfw command interface and qfw coreMiao Yan2016-05-23-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch splits qfw command interface and qfw core function into two files, and introduces a new Kconfig option (CONFIG_QFW) for qfw core. Now when qfw command interface is enabled, it will automatically select qfw core. This patch also makes the ACPI table generation select CONFIG_QFW. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | cmd: qfw: remove qemu_fwcfg_free_files()Miao Yan2016-05-23-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is part of the qfw refactor work. The qemu_fwcfg_free_files() function is only used in error handling in ACPI table generation, let's not make this a core function and move it to the right place. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: qemu: fix ACPI Kconfig optionsMiao Yan2016-05-23-11/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_GENENRATE_ACPI_TABLE controls the generation of ACPI table which uses U-Boot's built-in methods and CONFIG_QEMU_ACPI_TABLE controls whether to load ACPI table from QEMU's fw_cfg interface. But with commit "697ec431469ce0a4c2fc2c02d8685d907491af84 x86: qemu: Drop our own ACPI implementation", there is only one way to support ACPI table for QEMU targets which is the fw_cfg interface. Having two Kconfig options for this purpose is not necessary any more, so this patch consolidates the two. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: qemu: Move qfw command over to cmd and add Kconfig entryTom Rini2016-05-23-732/+249
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move the command portion of arch/x86/cpu/qemu/fw_cfg.c into cmd/qemu_fw_cfg.c - Move arch/x86/include/asm/fw_cfg.h to include/qemu_fw_cfg.h - Rename ACPI table portion to arch/x86/cpu/qemu/acpi_table.c Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: baytrail: Generate ACPI FADT/MADT tablesBin Meng2016-05-23-0/+164
| | | | | | | | | | | | | | | | | | | | | FADT/MADT tables are platform specific. Generate them for BayTrail. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: baytrail: Add platform ASL filesBin Meng2016-05-23-0/+1348
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds basic BayTrail platform ASL files. They are intended to be included in dsdt.asl of any board that is based on this platform. Note: ACPI mode support for GPIO/LPSS/SCC/LPE are not supported for now. They will be added in the future. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: acpi: Return table length in acpi_create_madt_lapics()Bin Meng2016-05-23-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | Like other MADT table write routines, make acpi_create_madt_lapics() return how many bytes it has written instead of the table end addr. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: acpi: Add some generic ASL librariesBin Meng2016-05-23-0/+331
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds several generic ASL libraries that can be included by other ASL files, which are: - debug.asl: for debug output using POST I/O port and legacy serial port - globutil.asl: for string compare routines - statdef.asl: for _STA status values Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: acpi: Clean up table header revisionsBin Meng2016-05-23-18/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The comment of initializing table header revision says: /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */ which might mislead it may increase per ACPI spec revision. However this is not the case. It's actually a fixed number as defined in ACPI spec, and in the laest ACPI spec 6.1, some table header revisions are still 1. Clean these up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: acpi: Align FACS table to a 64 byte boundaryBin Meng2016-05-23-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per ACPI spec, the FACS table address must be aligned to a 64 byte boundary (Windows checks this, but Linux does not). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: acpi: Use u32 in table write routinesBin Meng2016-05-23-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | Use u32 instead of unsigned long in the table write routines, as other routines do. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: acpi: Adjust order in acpi_table.cBin Meng2016-05-23-124/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rearrange the routine order a little bit, to follow the order in which ACPI table is defined in acpi_table.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: acpi: Change fill_header()Bin Meng2016-05-23-14/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename fill_header() to acpi_fill_header() for consistency. Change its signature to remove the 'length' parameter and make it a public API. Also remove the unnecessary include files, and improve the AmlCode[] comment a little bit. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: acpi: Remove acpi_create_ssdt_generator()Bin Meng2016-05-23-36/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This acpi_create_ssdt_generator() currently does nothing. Remove this for now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: acpi: Reorder code in acpi_table.hBin Meng2016-05-23-178/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reorder the ACPI tables appearance by following the order: RSDP, RSDT, XSDT, FADT, FACS, MADT, MCFG. And adjust the table flag defines accordingly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: acpi: Various changes to acpi_table.hBin Meng2016-05-23-68/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Use "U-BOOT" and "U-BOOTBL" for the OEM ID and OEM table ID. - Do not typedef acpi_header_t, instead use struct acpi_table_hader. - Use a shorter name aslc_id and aslc-revision. - Change MCFG base address to use 32-bit value pairs (_l and _h). - Apply ACPI_APIC_ prefix to MADT APIC type macros and make their names to be more readable. - Apply __packed to struct acpi_madt_irqoverride and struct acpi_madt_lapic_nmi tables, as they are not naturally aligned by the compiler which leads to wrong sizeof(struct). - Rename model to res1 as it is reserved after ACPI spec 1.0. - Apply ACPI_ prefix to the PM profile macros and change them to enum. - Add ospm_flags to FACS structure which is defined since ACPI 4.0. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: acpi: Remove unused codesBin Meng2016-05-23-68/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Remove #include <> header files. - Remove APM_CNT register defines, which should not be here as they are SMI related. - Remove MP_IRQ_ defines as they are duplicates of the same ones in asm/mpspec.h. - Remove ACTL register defines, which should not be here as they are chipset specific. - Remove functional fixed hardware defines, which are not used. - Remove dev_scope related defines, which are not used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: dts: Update to include ACTL register detailsBin Meng2016-05-23-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This updates all x86 boards that currently have IRQ router in the dts files to include ACTL register details. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: irq: Enable SCI on IRQ9Bin Meng2016-05-23-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default SCI is disabled after power on. ACTL is the register to enable SCI and route it to PIC/APIC. To support both ACPI in PIC mode and APIC mode, configure SCI to use IRQ9. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
| * | x86: irq: Reserve IRQ9 for ACPI in PIC modeBin Meng2016-05-23-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reserve IRQ9 which is to be used as SCI interrupt number for ACPI in PIC mode. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: acpi: Fix compiler warnings in write_acpi_tables()Bin Meng2016-05-23-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following two build warnings in function 'write_acpi_tables': warning: format '%lx' expects argument of type 'long unsigned int', but argument 2 has type 'u32' [-Wformat=] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Fix build warning in tables.c when CONFIG_SEABIOSBin Meng2016-05-23-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following build warning is seen in tables.c: warning: implicit declaration of function 'memalign' Add the missing header file to fix it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: Drop asm/acpi.hBin Meng2016-05-23-27/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove asm/acpi.h which is never used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2016-05-23-20/+4386
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| * | | malta: Support MIPS32r6 configurationsPaul Burton2016-05-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both real Malta boards & QEMU's Malta emulation can feature MIPS32r6 CPUs. Allow building U-Boot for such systems by selecting CONFIG_SUPPORTS_CPU_MIPS32_R6 for Malta. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | | MIPS: Support for targetting MIPSr6Paul Burton2016-05-21-6/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for targetting MIPS32r6 & MIPS64r6 systems, in the same way that we currently select release 1 or release 2 targets. MIPSr6 is not entirely backwards compatible with earlier releases of the architecture. Some instructions are encoded differently, some are removed, some are reused, so it is not practical to run U-Boot built for earlier revisions on a MIPSr6 system. Update their Kconfig help text to reflect that. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | | MIPS: Simplify CONFIG_SYS_CPU valuesPaul Burton2016-05-21-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than having the values for CONFIG_SYS_CPU depend upon each architecture revision, have them depend upon the more general CONFIG_CPU_MIPS32 & CONFIG_CPU_MIPS64 which in turn depend upon the architecture revisions. This is done in preparation for adding MIPSr6 support, which would otherwise need to introduce new cases here. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | | MIPS: Use unchecked immediate addition/subtractionPaul Burton2016-05-21-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In MIPS assembly there have historically been 2 variants of immediate addition - the standard "addi" which traps if an overflow occurs, and the unchecked "addiu" which does not trap on overflow. In release 6 of the MIPS architecture the trapping variants of immediate addition & subtraction have been removed. In preparation for supporting MIPSr6, stop using the trapping instructions from assembly & switch to their unchecked variants. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | | mips: ath79: Add support for TPLink WDR4300Marek Vasut2016-05-21-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the TPLink WDR4300 router, which is based on the AR9344 MIPS 74Kc CPU and has 128 MiB of RAM. The USB is supported on this system as well. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * | | mips: ath79: Add AR934x supportMarek Vasut2016-05-21-1/+683
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Atheros AR934x WiSoCs. This patchs adds complete system init, including PLL and DRAM init, both of which happen from full C environment, since the AR934x has proper SRAM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * | | mips: ath79: Add support for ungating ethernet on ar933x and ar934xMarek Vasut2016-05-21-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code to ungate the ethernet controller on ar933x and ar934x . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * | | mips: ath79: dts: Add ethernet MAC nodes for ar933xMarek Vasut2016-05-21-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add node for both ethernet controllers in the ar933x. The PHY is attached only to the first ethernet controller. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * | | mips: ath79: Add support for ungating USB on ar933x and ar934xMarek Vasut2016-05-21-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code to ungate the USB controller on ar933x and ar934x . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * | | mips: ath79: dts: Add generic-ehci nodeMarek Vasut2016-05-21-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add generic EHCI node for the ChipIdea EHCI controller in the ath79. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
generated by cgit v1.1 at 2024-11-08 06:41:59 +0000