summaryrefslogtreecommitdiff
path: root/arch
Commit message (Collapse)AuthorAgeLines
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-03-23-557/+5572
|\
| * sunxi: A83T: fix 32bit overflow warningvishnupatekar2016-03-23-1/+1
| | | | | | | | | | | | | | | | | | | | In mctl_channel_init, (0x50<<26) which overflows 32bit. It was supposed to be 0x50<<16,corrected now. Reported-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Select CONFIG_OF_BOARD_SETUP from arch/arm/KconfigHans de Goede2016-03-23-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Always select OF_BOARD_SETUP on sunxi, rather then having it in almost all our defconfigs. This also fixes it missing from some recently added defconfigs. This commit also modifies our ft_board_setup() to not cause warnings when CONFIG_VIDEO_DT_SIMPLEFB is not set, since we will now always build it. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Fix gmac not working due to cpu_eth_init no longer being calledHans de Goede2016-03-23-28/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cpu_eth_init is no longer called for dm enabled eth drivers, this was causing the sunxi gmac eth controller to no longer work in u-boot. This commit fixes this by calling the clock, reset and pinmux setup function from s_init() and enabling the phy power pin (if any) from board_init(). The enabling of phy power cannot be done from s_init because it uses dm and dm is not ready yet at this point. Note that the mdelay is dropped as the phy gets enabled much earlier now, so it is no longer needed. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Tested-by: Karsten Merker <merker@debian.org> Tested-by: Michael Haas <haas@computerlinguist.org>
| * sunxi: Add support for USB vbus pin for USB3Hans de Goede2016-03-23-0/+1
| | | | | | | | | | | | | | The H3 has USB0 - USB3, add support for having a USB vbus pin for USB3. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Support SID e-fuses on A83T and H3Chen-Yu Tsai2016-03-23-0/+7
| | | | | | | | | | | | | | | | | | | | On the A83T and H3, the SID block is at a different address. Furthurmore, the e-fuses are at an offset of 0x200 within the hardware's address space. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Add defconfig and dts for Orange Pi 2 SBCHans de Goede2016-03-23-0/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Orange Pi 2 is a SBC based on the Allwinner H3 SoC with a uSD slot, 4 USB ports connected via a USB-2 hub, a 10/100M ethernet port using the SoC's integrated PHY, Wifi via a RTL8189ETV sdio wifi chip, USB OTG, HDMI, a TRRS headphone jack for stereo out and composite out, a microphone, an IR receiver, a CSI connector, 2 LEDs, a 3 pin UART header and a 40-pin GPIO header. The added dts file is identical to the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Add defconfig and dts for Dserve DSRV9703C tabletHans de Goede2016-03-23-0/+282
| | | | | | | | | | | | | | | | | | The Dserve DSRV9703C is a 9.7" A10 tablet with a 1024x768 ips LCD, 1G RAM, 4GB flash, a Focaltech FT5406EE8 touchscreen and rtl8188ctv wifi. The dts file is identical to the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Add defconfig and dts for the Polaroid MID2809PXE4 tabletHans de Goede2016-03-23-0/+244
| | | | | | | | | | | | | | | | | | | | | | The Polaroid MID2809PXE4 is a 9" tablet which is clearly marked Polaroid MID2809PXE4 on the back. It features a 9" 16:9 800x480 LCD, A23 Soc, 1GB RAM, 8GB NAND, gsl3670 touchscreen and esp8089 wifi. The dts file is identical to the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Add defconfig and dts for Difrence DIT4350 tabletHans de Goede2016-03-23-0/+227
| | | | | | | | | | | | | | | | | | | | | | | | The Difrnce dit4350 tablet is a tiny tablet with a 4.3" 16:9 480x272 LCD, A13 SoC, 512M RAM, 4G NAND, solomon systech ssd2532qn6 touchscreen at i2c1 address 0x48, Memsic MXC622X accelerometer at i2c1 address 0x15 and rtl8188etv wifi. The dts file is identical to the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Add defconfig and dts for colorfly e708 q1 tabletHans de Goede2016-03-23-0/+209
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The colorfly e708 q1 is a 7" tablet which is clearly marked as colorfly e708 q1 on the back. It features a 9:16 800x1280 IPS LCD, A31s SoC, 1GB RAM, 8G NAND, ilitek 2139qt004 touchscreen on i2c-1 addr 0x41, stk8313 accelerometer on i2c-2 addr 0x22 and a rtl8188etv wifi chip. The added dts is identical to the dts submitted to the upstream kernel, note this commit also syncs axp22x.dtsi and sun6i-a31.dtsi with the upstream kernel as the added dts depends on these. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Fix clock_twi_onoff for sun9iHans de Goede2016-03-23-2/+2
| | | | | | | | | | | | | | | | Fix a copy and paste error which caused us to use the uart rather then the twi reset bits in clock_twi_onoff for sun9i. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Fix clock_twi_onoff for sun8i-a83Hans de Goede2016-03-23-31/+35
| | | | | | | | | | | | | | | | | | clock_sun8i_a83.c did not contain a clock_twi_onoff implementation at all, this is fixed by moving the clock_sun6i.c implementation, which is correct for the a83 too, to a shared location. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Fix clock_twi_onoff for sun6iHans de Goede2016-03-23-3/+8
| | | | | | | | | | | | | | | | The clock_sun6i.c implementation was not deasserting the reset for the regular i2c controllers, this commit fixes this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Sync dts files with the upstream kernelHans de Goede2016-03-23-497/+4351
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Sync dts files with the upstream kernel including changes queued for 4.6: https://git.kernel.org/cgit/linux/kernel/git/mripard/linux.git/commit/?h=sunxi/dt-for-4.6 Note this adds a number of new unused board dts files. I've asked the authors of the kernel commits adding these to submit a matching defconfig to u-boot. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: A23: Fix some revisions needing a different magic sram pokeHans de Goede2016-03-23-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | I've had this one a23 tablet which would not boot and I've finally figured out what the problem is by looking at the released boot0 code, it seems the magic sram controller poke which we need to do in s_init() depends on the revision of the a23. Specifically this change is needed to get the A23 SoC I have with the following serial to boot: "E6071AB 26Y7". Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | ARM: uniphier: add NOR boot supportMasahiro Yamada2016-03-24-2/+2
| | | | | | | | | | | | | | This allows to boot from NOR flash (or SRAM) with help of an external loader (NOR-loader). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: support Debug UARTMasahiro Yamada2016-03-24-0/+364
| | | | | | | | | | | | | | | | | | | | | | | | For ARM32 architecture, CONFIG_DEBUG_LL is available for early low-level debugging (and actually UniPhier 32bit SoCs use it), but ARM64 architecture does not support it. Instead, CONFIG_DEBUG_UART is available as an architecture-independent debug facility. This commit supports it on all the UniPhier SoCs (including the new ARMv8 SoCs), which is very useful for new SoC bringups. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: add System Control register macros for ARMv8 SoCsMasahiro Yamada2016-03-24-0/+44
| | | | | | | | | | | | | | | | The System Control block moved to a completely different register map for ARMv8 SoCs, so it cannot be shared with the ARM 32-bit ones. Define register macros in a new header file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: add sg_set_iectrl() functionMasahiro Yamada2016-03-24-0/+11
| | | | | | | | | | | | | | This helper function would be useful for new SoCs with per-pin input enable controlling, such as PH1-LD20, PH1-LD11, etc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: dts: uniphier: add PH1-LD11 SoC/board device tree sourcesMasahiro Yamada2016-03-24-0/+275
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: dts: uniphier: add PH1-LD20 SoC/board device tree sourcesMasahiro Yamada2016-03-24-0/+316
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: enable DDR PHY parameter dump commands by defaultMasahiro Yamada2016-03-24-0/+2
| | | | | | | | | | | | | | | | | | These commands are not necessarily needed for usual operations (they are useful in case of DDR memory trouble), but enabling them by default would be nice in terms of the compilation test coverage. They are small enough, so limited impact on the memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: add work-around to support Micro Support Card v3.6.10Masahiro Yamada2016-03-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to some hardware guy's awful work, this version is not compatible with v3.6: the logic of BIT(0) of the reset logic is inverted! (and v3.6.10 is horribly wrong in multiple ways), but this is what we have to solve now. The v3.6 expects 0x0000 set to the register for reset de-assertion, while v3.6 does 0x0001. This commit (ab)uses another bug of v3.6.10 to work around the issue. The UniPhier System Bus is a 16-bit bus, which this support card is connected to. A 32-bit write to the bus (writel() function call) is divided into two 16-bit write transactions, with LSB the first. What is amazing for v3.6.10 is that access to address 4N + 2 goes to 4N (Jesus Christ!). For clarification, things are like this: writel(0x00010000, MICRO_SUPPORT_CARD_RESET); is done with two bus transactions as follows [1] write 0x0000 to address MICRO_SUPPORT_CARD [2] write 0x0001 to address MICRO_SUPPORT_CARD + 2 For v3.6, [1] is written to the register and [2] is correctly ignored because there is nothing at the address MICRO_SUPPORT_CARD + 2. This is what we expect. For v3.6.10, [1] is written to the reset register and then [2] is over-written to the same register due to the bus access bug. For the latter, it produces a glitch signal to the BIT[0], so the device state is lost due to the reset pulse. This solution only works for the start-up code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: drop ifdef in ddrphy-regs.hMasahiro Yamada2016-03-24-75/+103
| | | | | | | | | | | | | | | | | | The ifdef conditionals in header files prevent us from multi-SoC support in a single U-Boot image. Detect SoC specific parameters run-time rather than define them statically with an ifdef in ddrphy-regs.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: refactor SBC init codeMasahiro Yamada2016-03-24-145/+105
| | | | | | | | | | | | | | | | | | There is a bunch of duplication in the System Bus Controller init code. Roughly, there are two types in the SBC mode: Adress/Data Multiplex Mode and Save Pins Mode. Consolidate per-SoC functions into the two, plus per-SoC optional init code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: drop PH1- prefix from CONFIG options and file namesMasahiro Yamada2016-03-24-224/+213
| | | | | | | | | | | | | | | | The current CONFIG names like "CONFIG_ARCH_UNIPHIER_PH1_PRO4" is too long. It would not hurt to drop "PH1_" because "UNIPHIER_" already well specifies the SoC family. Also, rename files for consistency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: dts: uniphier: add device tree for Micro Support CardMasahiro Yamada2016-03-24-0/+58
|/ | | | | | | Import uniphier-support-card.dtsi from Linux Kernel and make it available on the UniPhier reference boards. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Fix spelling of "transferred".Vagrant Cascadian2016-03-22-5/+5
| | | | | | | Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* sandbox: Avoid calling commands when not availableSimon Glass2016-03-22-1/+9
| | | | | | | Don't try to run commands when not supported. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: x86: Drop command-line code when CONFIG_CMDLINE is disabledSimon Glass2016-03-22-0/+7
| | | | | | | | Update the link script to drop this code when not needed. This is only done for two architectures at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-03-22-144/+93
|\
| * armv8/fsl-lsch2: fix sdhc clock frequency valueYangbo Lu2016-03-21-0/+4
| | | | | | | | | | | | | | | | | | The eSDHC could select to use platform clock or peripheral clock to generate SD clock. The default selection is platform clock. So, fix the clock frequency value that's calculated for eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Updating entries in Serdes TablePratiyush Srivastava2016-03-21-7/+7
| | | | | | | | | | | | | | | | | | | | | | The serdes protocol entries in Serdes table 1 for protocol 0x03, 0x33, 0x35 and in Serdes table 2 for protocols 0x45 and 0x47 are updated to reflect the entries in current Reference Manual. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Reported-by: Jose Rivera <german.rivera@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver/ddr/fsl: Add workaround for erratum A-009803Shengzhou Liu2016-03-21-0/+1
| | | | | | | | | | | | | | | | | | During initial DDR training, false parity errors may be detected. This patch adds workaround to fix the erratum. Tested on LS2085QDS and LS2080RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * pci/layerscape: add defines for LUTStuart Yoder2016-03-21-0/+4
| | | | | | | | | | | | | | | | | | | | The per-PCI controller LUT (Look-Up-Table) is a 32-entry table that maps PCI requester IDs (bus/dev/fun) to a stream ID. Add defines for the register offsets. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: update stream ID partitioning infoStuart Yoder2016-03-21-21/+34
| | | | | | | | | | | | | | | | | | Update comments around how stream IDs are partitioned. Stream IDs allocated to PCI are no longer divided up by controller, but are instead a contiguous range Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: remove obsolete stream ID partitioning supportStuart Yoder2016-03-21-113/+0
| | | | | | | | | | | | | | | | | | | | Remove stream ID partitioning support that has been made obsolete by upstream device tree bindings that specify how representing how PCI requester IDs are mapped to MSI specifiers and SMMU stream IDs. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm: ls102xa: fdt: Update FSL_QSPI_COMPAT and FSL_DSPI_COMPATAlison Wang2016-03-21-2/+2
| | | | | | | | | | | | | | | | | | As the compatible property values for QSPI and DSPI dts nodes are changed in kernel, FSL_QSPI_COMPAT and FSL_DSPI_COMPAT need to be updated too. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080ardb: invert irq pins polarity for AQR405 PHYShaohui Xie2016-03-21-0/+4
| | | | | | | | | | | | | | | | | | To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins polarity by setting IRQCR register, because AQR405 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: lsch3: Enable WUO config for RNI-20 nodePrabhakar Kushwaha2016-03-21-0/+31
| | | | | | | | | | | | | | | | | | | | Enable wuo config to accelerate coherent ordered writes for LS2080A and LS2085A. WRIOP IP is connected to RNI-20 Node. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm64: Fix layerscape mmu setupAlexander Graf2016-03-21-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With commit 7985cdf we converted all systems except for the Layerscape SoCs to the generic descriptor table based page table setup. On the Layerscape SoCs however, we just provide an empty table stub and do the setup ourselves. To reserve enough memory for the tables, we need to override the default counting mechanism which would end up with an empty table because we have no maps. Fixes: 7985cdf Reported-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | arm: socfpga: sr1500: Misc updates (SPI speed, env location)Stefan Roese2016-03-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes the following changes to the SR1500 board port: - Update defconfig to support SPI NOR (use make savedefconfig). - Increase SPI speed to a maximum of 100MHz for faster system bootup. - Change environment location, so that its not between SPL and main U-Boot. This way the combined SPL / U-Boot image can be used for updates. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de>
* | dts:exynos:update pinctrl size-cells and fix child regsPrzemyslaw Marczak2016-03-17-29/+29
|/ | | | | | | | | | | | | | | | | | | This change is required to avoid warnings about invalid size-cells defined in device-tree pinctrl nodes for Exynos. Tested on: - Odroid U3 - Odroid XU3 Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* x86: Add congatec conga-QA3/E3845-4G (Bay Trail) supportStefan Roese2016-03-17-0/+283
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM, installed on the congatec Qseven 2.0 evaluation carrier board (conga-QEVAL). Its port is very similar to the MinnowboardMAX port and also uses the Intel FSP as described in doc/README.x86. Currently supported are the following interfaces / devices: - UART (via Winbond legacy SuperIO chip on carrier board) - Ethernet (PCIe Intel I210 / E1000) - SPI including SPI NOR as boot-device - USB 2.0 - SATA via U-Boot SCSI IF - eMMC - Video (HDMI output @ 800x600) - PCIe Not supported yet is: - I2C - USB 3.0 Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add support for the samus chromebookSimon Glass2016-03-17-0/+629
| | | | | | | | | | | | | | | | | | | | | | | This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Support a chained-boot development flowSimon Glass2016-03-17-0/+80
| | | | | | | | | | | | | | | | | | Sometimes it is useful to jump into U-Boot directly from coreboot or UEFI without any 16-bit init. This can help during development by allowing U-Boot to avoid doing all the init required by the platform. U-Boot expects its GDT to be set up correctly by its 16-bit code. If coreboot doesn't do this (because it hasn't run the payload setup code yet) then this won't happen. In this case we cannot rely on the GDT settings. U-Boot will hang or crash if these are wrong. Provide a development-only option to set up the GDT correctly. This is just a hack so you can jump to U-Boot from any stage of coreboot, not just at the end. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: dts: Drop memory SPD compatible stringSimon Glass2016-03-17-1/+0
| | | | | | | | This is not needed now that the memory controller driver has the SPD data in its own node. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Convert to use the common SDRAM codeSimon Glass2016-03-17-311/+83
| | | | | | | Adjust the existing implementation to use the new common SDRAM init code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add common SDRAM-init codeSimon Glass2016-03-17-0/+327
| | | | | | | | | The code to call the memory reference code is common to several Intel CPUs. Add common code for performing this init. Intel calls this 'Pre-EFI-Init' (PEI), where EFI stands for Extensible Firmware Interface. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-10-23 15:33:23 +0000