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* powerpc/t4qds: Add alternate serdes protocols to align with A-007186Shaohui Xie2014-06-05-0/+172
| | | | | | | | | | | | | | | | | A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to increase and cause the PLL to unlock when the temperature delta from the time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC VCO. Only the protocols using Ring VCOs are impacted. Workaround: For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need to use alternate serdes protocols. The alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/t208x: update t2080qds/t2080rdb for errata A-007186Shengzhou Liu2014-06-05-3/+23
| | | | | | | | | | | | | As errata A-007186, we need to use the alternate serdes protocol instead of those impacted protocols. - add support for serdes protocols: 0x1b, 0x50, 0x5e, 0x64, 0x6a, 0xd2, 0x67, 0x70. - update t2080_rcw.cfg to adapt to new rcw_66_15 for t2080qds and t2080rdb. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc: hiddendragon: remove orphan boardMasahiro Yamada2014-05-30-12/+0
| | | | | | | | | | | This board has been orphan for a while. (Emails to its maintainer have been bouncing.) Because MPC82xx family is old enough, nobody would pick up the maintainership on it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denx <wd@denx.de>
* powerpc: mpc8260ads: remove orphan boardMasahiro Yamada2014-05-30-15/+0
| | | | | | | | | | | This board has been orphan for a while. (Emails to its maintainer have been bouncing.) Because MPC82xx family is old enough, nobody would pick up the maintainership on it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denx <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-05-30-5/+2331
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| * ARM: at91sam9m10g45ek: enable mci0 supportWu, Josh2014-05-27-0/+17
| | | | | | | | | | | | | | | | | | | | Also we enable the mmc command in configuration file. As both CONFIG_CMD_MMC and CONFIG_CMD_USB use the CONFIG_DOS_PARTITION, so remove the redundant CONFIG_DOS_PARTITION definition. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * ARM: at91sam9x5: define the AT91FAMILY and ARM926EJS in SoC headerWu, Josh2014-05-27-0/+3
| | | | | | | | | | Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * ARM: at91: remove AT91X40 macro since it is not use any moreWu, Josh2014-05-27-2/+0
| | | | | | | | | | | | | | The at91x40.h is not exist. So we remove it. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm:at91: enable ROM loadable atmel imageAndreas Bießmann2014-05-27-0/+10
| | | | | | | | | | | | | | | | For sama5d3xek we need to modify the SPL image for correct detection by ROM code. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Bo Shen <voice.shen@atmel.com>
| * ARM: atmel: switch to main crystal osc for SPL bootBo Shen2014-05-27-0/+43
| | | | | | | | | | | | | | | | | | If without switch to main crystal oscillator, the sama5d3 SoC will use internal on chip RC oscillator. In order to get better accuracy, switch to main crystal oscillator. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * sunxi: non-FEL SPL boot support for sun7iIan Campbell2014-05-25-0/+60
| | | | | | | | | | | | | | | | | | | | | | Add support for booting from an MMC card. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Henrik Nordström <henrik@henriknordstrom.net> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
| * sunxi: mmc supportIan Campbell2014-05-25-0/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Mon, 2014-05-05 at 14:18 +0200, Stefan Roese wrote: > > + case 1: > > +#if CONFIG_MMC1_PG > Are you sure that this is correct and shouldn't be: > > +#ifdef CONFIG_MMC1_PG > > ? It's "correct" in so far as it works (the boards.cfg config stuff #defines things to 1), but I think you are right that it isn't the preferred style. But... > A quick scan through this patch series shows that this define > is not set at all. Perhaps its outdated? Or is it used to support > some other sunxi SoC? Not sure, perhaps it should be removed for > now. ...I had thought that it was to support some other board which wasn't being upstreamed right now, so eventually useful and harmless for now, but I've just checked and it isn't actually used by any of the boards in u-boot-sunxi.git. So rather than fix it to use #ifdef lets drop it. Rather than resend the entire series, here is v5.1 of this patch. > Other than this please add my: > > Reviewed-by: Stefan Roese <sr@denx.de> Thanks! 8<--------------------------------- >From 20704e35a41664de5f516ed0e02981ac06085102 Mon Sep 17 00:00:00 2001 From: Ian Campbell <ijc@hellion.org.uk> Date: Fri, 7 Mar 2014 04:29:39 +0000 Subject: [PATCH v5.1 7/8] sunxi: mmc support This adds support for the MMC controller on the Allwinner A20 (sun7i) processor. Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Luke Leighton <lkcl@lkcl.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Wills Wang <wills.wang.open@gmail.com> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Cc: Aaron Maoye <leafy.myeh@allwinnertech.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: Tom Rini <trini@ti.com>
| * sunxi: add gmac Ethernet supportIan Campbell2014-05-25-0/+23
| | | | | | | | | | | | | | | | | | | | | | Add support for the GMAC Ethernet controller on Allwinner A20 (sun7i) processors. Enable for the Cubietruck. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@ti.com>
| * sunxi: add sun7i cpu, board and start of day supportIan Campbell2014-05-25-1/+339
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds generic board, start of day and basic build system support for the Allwinner A20 (sun7i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. Signed-off-by: Adam Sampson <ats@offog.org> Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Luc Verhaegen <libv@skynet.be> Signed-off-by: Luke Leighton <lkcl@lkcl.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Patrick Wood <patrickhwood@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Wills Wang <wills.wang.open@gmail.com> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
| * sunxi: add sun7i dram setup supportIan Campbell2014-05-25-0/+773
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds DRAM initialisation support for the Allwinner A20 (sun7i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Luke Leighton <lkcl@lkcl.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
| * sunxi: add sun7i pinmux and gpio supportIan Campbell2014-05-25-0/+209
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the basic pinmux and gpio support for the Allwinner A20 (sun7i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ma Haijun <mahaijuns@gmail.com> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Henrik Nordström <henrik@henriknordstrom.net> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Tom Rini <trini@ti.com> Acked-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
| * sunxi: add sun7i clocks and timer support.Ian Campbell2014-05-25-0/+727
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the basic clocks and timer support for the Allwinner A20 (sun7i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. Some of the code here is common to multiple sunxi subarchtectures, hence files are named sun4i which is the earliest similar variant. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Luke Leighton <lkcl@lkcl.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Stefan Roese <sr@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
| * arm: vf610: add DDR_SEL_PAD_CONTR registerStefan Agner2014-05-25-0/+1
| | | | | | | | | | | | | | | | Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves RAM issues with newer silicon (1.1). This register was added in revision 4 of the Vybrid Reference Manual. Signed-off-by: Stefan Agner <stefan@agner.ch>
| * Arm64 fix a bug of vbar_el3 initializationDavid Feng2014-05-25-2/+2
| | | | | | | | Signed-off-by: David Feng <fenghua@phytium.com.cn>
* | m68k: powerpc: Clean up do_mdm_initSimon Glass2014-05-29-15/+0
| | | | | | | | | | | | | | | | This code seems unnecessarily complex. We really just need to check the global_data. Now that is it all in one place, and not arch-specific, this is pretty easy. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Remove unnecessary use of hush header fileSimon Glass2014-05-29-2/+0
| | | | | | | | | | | | | | Some files include hush.h but don't actually use it. Remove this where possible. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: rename device struct to udeviceHeiko Schocher2014-05-27-4/+4
|/ | | | | | | | | | | | using UBI and DM together leads in compiler error, as both define a "struct device", so rename "struct device" in include/dm/device.h to "struct udevice", as we use linux code (MTD/UBI/UBIFS some USB code,...) and cannot change the linux "struct device" Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Marek Vasut <marex@denx.de>
* Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-05-24-263/+470
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| * am33xx: report silicon revision instead of codeSergey Alyoshin2014-05-23-18/+23
| | | | | | | | | | | | | | | | | | As revision code 1 is for silicon revision 2.0, it is easily confused with silicon revision 1.0. Device type report also reworked in same style. Signed-off-by: Sergey Alyoshin <alyoshin.s@gmail.com>
| * ARM: OMAP: Fix omap_sdram_size calculationLokesh Vutla2014-05-23-4/+7
| | | | | | | | | | | | | | | | | | Last section of DMM is used for trapping tiler unmapped sections. Corresponding trap_size should be deducted from total SDRAM size only if trap section is overlapping with available SDRAM based on DMM sections. Fixing the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * armv7:TI: Add <asm/ti-common/sys_proto.h> and migrate omap_hw_init_contextTom Rini2014-05-23-112/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | The omap_hw_init_context function (and assorted helpers) is the same for all OMAP-derived parts as when CHSETTINGS are used, that's the same and our DDR base is also always the same. In order to make this common we simply need to update the names of the define for DDR address space which is also common. Cc: Sricharan R. <r.sricharan@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ARM: DRA7xx: ctrl: Fix efuse register addressesLokesh Vutla2014-05-23-4/+4
| | | | | | | | | | | | | | | | Efuse register addresses are wrongly programmed. Fixing the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * ARM: DRA72x: Update EMIF dataLokesh Vutla2014-05-23-3/+23
| | | | | | | | | | | | | | | | DRA72 has 1GB connected to EMIF1 only. Updating the details. And also enable WA for BUG0039 only if corresponding EMIF is present. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * ARM: DRA72x: clocks: Update the hwdataLokesh Vutla2014-05-23-0/+7
| | | | | | | | | | | | | | Adding the prcm, dplls, control module hooks for DRA72x. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * ARM: DRA72x: volt: Update the pmic offsetsKeerthy2014-05-23-0/+32
| | | | | | | | | | | | | | | | TPS65917 is used in DRA722 evm. Update the address offsets accordingly. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * ARM: DRA72x: Add Silicon ID supportLokesh Vutla2014-05-23-0/+5
| | | | | | | | | | | | | | Add silicon ID code for DRA722 silicon. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * ARM: omap: merge GPMC initialization code for all platformpekon gupta2014-05-23-110/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPMC controller on TI's OMAP SoC is general purpose controller to interface with different types of external devices like; - parallel NOR flash - parallel NAND flash - OneNand flash - SDR RAM - Ethernet Devices like LAN9220 Though GPMC configurations may be different for each platform depending on clock-frequency and external device interfacing with controller. But initialization sequence remains common across all platfoms. Thus this patch merges gpmc_init() scattered in different arch-xx/mem.c files into single omap-common/mem-common.c However, actual platforms specific register config values are still sourced from corresponding platform specific headers like; AM33xx: arch/arm/include/asm/arch-am33xx/mem.h OMAP3: arch/arm/include/asm/arch-omap3/mem.h OMAP4: arch/arm/include/asm/arch-omap4/mem.h OMAP4: arch/arm/include/asm/arch-omap5/mem.h Also, CONFIG_xx passed by board-profile decide config for which set of macros need to be used for initialization CONFIG_NAND: initialize GPMC for NAND device CONFIG_NOR: initialize GPMC for NOR device CONFIG_ONENAND: initialize GPMC for ONENAND device Signed-off-by: Pekon Gupta <pekon@ti.com> [trini: define GPMC_SIZE_256M for omap3] Signed-off-by: Tom Rini <trini@ti.com>
| * ARM: omap5: add platform specific info for GPMC and ELM controllerspekon gupta2014-05-23-6/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves platform specific information for GPMC and ELM controller into separate header files, so that any derivative devices do not mess other header files. Platform specific information added into arch-xx/../hardware.h - CPU related platform specific details like base-address of GPMC and ELM Platform specific information added into arch-xx/../mem.h - Generic configs for GPMC and ELM initialization. - Hardware parameters or constrains specific to GPMC and ELM IP like; number of max number of chip-selects available Signed-off-by: Pekon Gupta <pekon@ti.com>
| * ARM: omap4: add platform specific info for GPMC and ELM controllerspekon gupta2014-05-23-6/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves platform specific information for GPMC and ELM controller into separate header files, so that any derivative devices do not mess other header files. Platform specific information added into arch-xx/../hardware.h - CPU related platform specific details like base-address of GPMC and ELM Platform specific information added into arch-xx/../mem.h - Generic configs for GPMC and ELM initialization. - Hardware parameters or constrains specific to GPMC and ELM IP like; number of max number of chip-selects available Signed-off-by: Pekon Gupta <pekon@ti.com>
* | Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master'Albert ARIBAUD2014-05-23-7/+16
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| * | arm: rmobile: koelsch: Fix QoS revision 0.240 and 0.320Nobuhiro Iwamatsu2014-05-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add register define of DBSC3 operation adjustment register, and add initial value. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | arm: rmobile: r8a7791: Fix MOD_SEL3 function table about FN_SEL_IEBNobuhiro Iwamatsu2014-05-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | FN_SEL_IEB is assigned 2bit, and 2bit can represent 4 patterns. However FN_SEL_IEB but we only use 3. It adds empty patterns as 0. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | gpio: r8a7790-gpio: Fix typo in macroNobuhiro Iwamatsu2014-05-21-3/+3
| | | | | | | | | | | | | | | | | | Fix typo from __ASM_R8A7790_H__ to __ASM_R8A7790_GPIO_H__. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | gpio: r8a7791-gpio: Fix typo in macroNobuhiro Iwamatsu2014-05-21-3/+3
| | | | | | | | | | | | | | | | | | Fix typo from __ASM_R8A7791_H__ to __ASM_R8A7791_GPIO_H__. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | arm: rmobile: Add define of SCIF register for R8A7790 and R8A7791Nobuhiro Iwamatsu2014-05-21-0/+8
| |/ | | | | | | Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* | Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'Albert ARIBAUD2014-05-23-9/+383
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| * | zynq: add UART nodes to device tree to initialize UART with OFMasahiro Yamada2014-05-15-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit c9416b92 added OF UART initialization support but aliases nodes are missing in device tree. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Michal Simek <michal.simek@xilinx.com> Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com> [on ZC706 board] Tested-by: Michal Simek <michal.simek@xilinx.com> [on ZC702 board] Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | zynq: add memory nodes to device tree to initialize DRAM with OFMasahiro Yamada2014-05-15-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 9e0e37ac added OF RAM initialization support but memory nodes are missing in device tree. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Michal Simek <michal.simek@xilinx.com> Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com> [on ZC706 board] Tested-by: Michal Simek <michal.simek@xilinx.com> [on ZC702 board] Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | zynq: import zynq-7000.dtsi from Linux KernelMasahiro Yamada2014-05-15-0/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Our current motivation is to use OF initialization for RAM and UART. But adding full DTS would be helpful in future, for instance, for OF configuration of Ethernet, MMC, USB, etc. This commit imports arch/arm/boot/dts/zynq-7000.dtsi from Linux 3.15-rc5 and adjusts the license comment block for SPDX. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Suggested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | zynq: treat ps7_init.c/h as external files to ignore themMasahiro Yamada2014-05-14-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ps7_init.c and ps7_init.h are supposed to be exported by hw project and copied to board/xilinx/zynq/ directory. We want them to be ignored by git. So what we should do is to always treat them as external files rather than replacing ps7_init.c This commit does: - Move a weak function ps7_init() to arch/arm/cpu/armv7/zynq/spl.c and delete board/xilinx/zynq/ps7_init.c - Compile board/xilinx/zynq/ps7_init.c only when it exists - Add .gitignore to ignore ps7_init.c/h Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: ehci: Added USB host driver supportMichal Simek2014-05-14-0/+26
| | | | | | | | | | | | | | | | | | | | | Added USB host driver for zynq. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Add MIO detection codeMichal Simek2014-05-14-0/+51
| | | | | | | | | | | | | | | | | | | | | Add run-time MIO pin detection to get actual pin configuration for specific periphery. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Fix bootmode maskMike Looijmans2014-05-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bootmode mask was defined as 0x0F, but documentation mentions 0x07. Experiments show that bit "3" is the JTAG chain configuration. Change the mask to "7" to allow systems with a different chain configuration to boot correctly. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Setup correct slcr_lock valueMichal Simek2014-05-14-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | The driver should setup slcr state according to slcr operations. Reported-by: Andrey Filippov <andrey@elphel.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: slcr: Fix incorrect commentaryMichal Simek2014-05-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Fix c&p error in zynq_slcr_devcfg_enable() commentary and extending it with description according to Zynq TRM also in zynq_slcr_devcfg_disable(). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit v1.1 at 2024-11-07 06:31:41 +0000