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* x86: quark: Add USB PHY initialization supportBin Meng2015-09-09-0/+49
| | | | | | | | USB PHY needs to be properly initialized per Quark firmware writer guide, otherwise the EHCI controller on Quark SoC won't work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Convert to use driver model pci on quark/galileoBin Meng2015-09-09-78/+6
| | | | | | | Move to driver model pci for Intel quark/galileo. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Enable PCIe controller on quark/galileoBin Meng2015-09-09-0/+105
| | | | | | | | | | | | | Quark SoC holds the PCIe controller in reset following a power on. U-Boot needs to release the PCIe controller from reset. The PCIe controller (D23:F0/F1) will not be visible in PCI configuration space and any access to its PCI configuration registers will cause system hang while it is held in reset. Enable PCIe controller per Quark firmware writer guide. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Avoid chicken and egg problemBin Meng2015-09-09-15/+15
| | | | | | | | | | | | | | | | | | | | If we convert to use driver model pci on quark, we will encounter some chicken and egg problems like below: - To enable PCIe root ports, we need program some registers on the message bus via pci bus. With driver model, the first time to access pci bus, the pci enumeration process will be triggered. But without first enabling PCIe root ports, pci enumeration just hangs when scanning PCIe root ports. - Similar situation happens when trying to access GPIO from the PCIe enabling codes, as GPIO requires its block base address to be assigned via a pci configuration register in the bridge. To avoid such dilemma, replace all pci calls in the quark codes to use the local version which does not go through driver model. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Optimize MRC execution timeBin Meng2015-09-09-22/+57
| | | | | | | | | | | | | | | | | Intel Quark SoC has a low end x86 processor with only 400MHz frequency. Currently it takes about 15 seconds for U-Boot to boot to shell and the most time consuming part is with MRC, which is about 12 seconds. MRC programs lots of registers on the SoC internal message bus indirectly accessed via pci bus. To speed up the boot, create an optimized version of pci config read/write dword routines which directly operate on PCI I/O ports. These two routines are inlined to provide better performance too. Now it only takes about 3 seconds to finish MRC, which is really fast (4 times faster than before). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Convert to use more dm driversBin Meng2015-09-09-6/+0
| | | | | | | Move to driver model for RTC, USB and ETH on coreboot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: test: Add a new test case for dm_test_eth_rotateBin Meng2015-09-09-0/+7
| | | | | | | | | Add one more ethernet device node in the sandbox test device tree, with name 'sbe5'. This is to support a new test case for testing network device rotation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* x86: panther: Add PCI and video configurationSimon Glass2015-09-09-0/+10
| | | | | | | | | Add a PCI node to the device tree. This allows SPI flash and SATA to work correctly. Also configure the video to come up correctly even though there is no keyboard. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge git://git.denx.de/u-boot-socfpgaTom Rini2015-09-07-12/+241
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| * arm: socfpga: Add support for the Terasic DE-0 Atlas boardDinh Nguyen2015-09-04-0/+69
| | | | | | | | | | | | | | Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV based board. The board can boot from SD/MMC. Ethernet is also supported. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * arm: socfpga: Add support for DENX MCV SoM and MCVEVK boardMarek Vasut2015-09-04-0/+61
| | | | | | | | | | | | | | | | Add support for DENX MCV SoM, which is CycloneV based and the associated DENX MCVEVK baseboard. The board can boot from eMMC. Ethernet and USB is supported. Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: Add support for Terasic SoCkit boardMarek Vasut2015-09-04-0/+100
| | | | | | | | | | | | | | | | Add support for Terasic SoCkit, which is CycloneV based board. The board can boot either from SD/MMC or QSPI. Ethernet is also supported. Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: Do not call board_init_r() from board_init_f()Marek Vasut2015-09-04-2/+0
| | | | | | | | | | | | | | | | | | | | | | Instead of calling board_init_r() directly from board_init_f(), just return from board_init_f(). This will make the code continue executing in crt0.S _main(), from which the board_init_r() is called. This patch aligns the SoCFPGA SPL with the correct SPL design as well as reduces the stack utilisation slightly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * arm: socfpga: Always enable OF_CONTROL and SPL_OF_CONTROLMarek Vasut2015-09-04-0/+2
| | | | | | | | | | | | | | The SoCFPGA probes mostly from OF and the OF is mandatory both in U-Boot itself and U-Boot SPL. Enable it by default. Signed-off-by: Marek Vasut <marex@denx.de>
| * arm: socfpga: Assure ISWGRP 0 and 1 are initedMarek Vasut2015-09-04-1/+7
| | | | | | | | | | | | | | | | | | | | This fix makes sure that the ISWGRP0 and ISWGRP1 registers are correctly inited. In case those registers are not initialized, it is not possible to access the registers synthesised in the FPGA through the bridges. Any such access produces data abort. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * mmc: dw_mmc: Probe the MMC from OFMarek Vasut2015-09-04-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Rework the driver to probe the MMC controller from Device Tree and make it mandatory. There is no longer support for probing from the ancient qts-generated header files. This patch now also removes previous temporary workaround. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com>
* | arc: make AXS101 default platformAlexey Brodkin2015-09-07-1/+1
|/ | | | | | | | | | | | | | | | | | This fixes building in automated flow that doesn't use defconfigs. See discussion on that topic here: http://patchwork.ozlabs.org/patch/502558/ See similar patches for other architectures/platforms here: [1] http://git.denx.de/?p=u-boot.git;a=commit;h=ff560a13056a565a4e9ce1761bd04276a3cace88 [2] http://git.denx.de/?p=u-boot.git;a=commit;h=589907e2c187ec69b351c38ccda36730d25ab5d6 And while at it add missing shell prompt to axs103. Cc: Tom Rini <trini@konsulko.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2015-09-03-6/+6636
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| * arm: Turn of d-cache before i-cacheSjoerd Simons2015-09-02-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Booting the kernel fails on RK3288 (and probably other rockchip SoCs) when the i-cache is disabled/flushed before d-cache. I have not investigated whether this is due to U-Boot hanging or whether it's very early in the linux boot, but following the approach of the various rockchip U-Boot forks (first disable d-cache then i-cache) makes things work. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: Disable sdio mmc slot on rk3288-fireflySjoerd Simons2015-09-02-1/+1
| | | | | | | | | | | | | | | | | | U-Boot can't use the sdio card so turn it of to prevent things getting confused/struck when trying to use the card as storage. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: Add basic support for jerrySimon Glass2015-09-02-1/+1275
| | | | | | | | | | | | This builds and displays an SPL message, but does not function beyond that. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: Add basic support for firefly-rk3288Simon Glass2015-09-02-0/+544
| | | | | | | | | | | | | | | | | | | | | | The Firefly RK3288 is a suitable target board for initial mainline Rockchip support. It includes a good set of peripherals, a recent SoC and it is readily available. This adds only some basic files required to allow the baord to display a serial message in SPL and hang. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: Add SPI driverSimon Glass2015-09-02-0/+20
| | | | | | | | | | | | | | Add a SPI driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: Add I2C driverSimon Glass2015-09-02-0/+70
| | | | | | | | | | | | | | Add an I2C driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: Add core SoC start-up codeSimon Glass2015-09-02-0/+432
| | | | | | | | | | | | | | Add code for starting up U-Boot SPL and U-Boot proper. This is generic and makes use of devices provided by the board- or SoC-specific code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3288: Add SDRAM initSimon Glass2015-09-02-0/+1455
| | | | | | | | | | | | | | | | | | Add code to set up the SDRAM in SPL, ready for loading U-Boot. This uses device tree for configuration so should be able to support other RAM configurations. It may be possible to generalise the code to support other SoCs at some point. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3288: Add a simple syscon driverSimon Glass2015-09-02-0/+26
| | | | | | | | | | | | Add a driver that provides access to system controllers. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3288: Add SoC reset driverSimon Glass2015-09-02-0/+54
| | | | | | | | | | | | | | We can reset the SoC using some CRU (clock/reset unit) registers. Add support for this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3288: Add header files for PMU and GRFSimon Glass2015-09-02-0/+857
| | | | | | | | | | | | | | PMU is the power management unit and GRF is the general register file. Both are heavily used in U-Boot. Add header files with register definitions. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3288: Add clock driverSimon Glass2015-09-02-0/+185
| | | | | | | | | | | | | | Add a driver for setting up and modifying the various PLLs and peripheral clocks on the RK3288. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: Add basic peripheral and clock definitionsSimon Glass2015-09-02-0/+119
| | | | | | | | | | | | | | | | Add header files for the peripherals and clocks supported on Rockchip platforms. The particular implementation (and register set) for each is SoC-specific, but it seems that the naming can be generic. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: gpio: Add rockchip GPIO driverSimon Glass2015-09-02-0/+28
| | | | | | | | | | | | | | This supports RK3288 at present. It does not implement functions or support for pull up/down. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: rk3288: dts: Make core devices available earlySimon Glass2015-09-02-0/+15
| | | | | | | | | | | | | | In SPL we need access to the CRU and other peripherals so we can set up SDRAM. Mark these so that they will remain in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: Bring in RK3288 device tree file includes and bindingsSimon Glass2015-09-02-0/+1546
| | | | | | | | | | | | | | | | Bring in required device tree files from Linux. Since mainline Linux is somewhat behind, use the files from the Chromium tree. We can re-sync once further code is acccepted upstream. Signed-off-by: Simon Glass <sjg@chromium.org>
| * arm: reset: Avoid a build error when the reset uclass is enabledSimon Glass2015-09-02-0/+2
| | | | | | | | | | | | | | There can be only one do_reset(). When CONFIG_RESET is enabled this is provided by the reset uclass, and ARM's version should be disabled. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arch/arm/Kconfig: Add back in missing entries.Tom Rini2015-09-02-0/+2
| | | | | | | | | | | | | | In 2178282 we accidentally dropped out hilsilicon and cm_t43. Bring these back in. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Convert omap3_logic to ti_omap3_common.hAdam Ford2015-09-02-0/+3
| | | | | | | | | | | | | | Convert to using the common config files. Signed-off-by: Adam Ford <adam.ford@logicpd.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | powerpc: mpc85xx: remove stxgp3, stxssa supportMasahiro Yamada2015-09-02-8/+0
| | | | | | | | | | | | | | | | These have not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Dan Malek <dan@embeddedalley.com>
* | powerpc: mpc5xx: remove cmi_mpc5xx supportMasahiro Yamada2015-09-02-4/+0
| | | | | | | | | | | | | | This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | powerpc: ppc4xx: remove zeus supportMasahiro Yamada2015-09-02-19/+0
| | | | | | | | | | | | | | | | This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Stefan Roese <sr@denx.de>
* | powerpc: ppc4xx: remove sbc405 supportMasahiro Yamada2015-09-02-4/+0
| | | | | | | | | | | | | | This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | powerpc: ppc4xx: remove pcs440ep supportMasahiro Yamada2015-09-02-4/+0
| | | | | | | | | | | | | | | | This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Stefan Roese <sr@denx.de>
* | powerpc: ppc4xx: remove p3p440 supportMasahiro Yamada2015-09-02-4/+0
| | | | | | | | | | | | | | | | This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Stefan Roese <sr@denx.de>
* | powerpc: ppc4xx: remove lwmon5 supportMasahiro Yamada2015-09-02-11/+0
| | | | | | | | | | | | | | | | | | | | | | This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Remove CONFIG_LWMON5 references. (Also, remove undefined CONFIG_WD_MAX_RATE while I am here.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Stefan Roese <sr@denx.de>
* | powerpc: ppc4xx: remove csb272, csb472 supportMasahiro Yamada2015-09-02-8/+0
| | | | | | | | | | | | | | | | These have not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Tolunay Orkun <torkun@nextio.com>
* | powerpc: ppc4xx: remove alpr supportMasahiro Yamada2015-09-02-4/+0
| | | | | | | | | | | | | | | | This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2015-09-02-29/+124
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| * | net/fman: Support both new and legacy FMan CompatiblesIgal Liberman2015-09-01-28/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recently the FMan Port and MAC compatibles were changed. This patch aligns the FMan Port and MAC compatibles to the new FMan device tree binding document. The FMan device tree binding document can be found in the Linux kernel: ./Documentation/devicetree/bindings/powerpc/fsl/fman.txt This patch doesn't affect legacy compatibles support. Signed-off-by: Igal Liberman <igal.liberman@freescale.com> Tested-by: Xing Lei <xing.lei@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ramYork Sun2015-09-01-1/+9
| |/ | | | | | | | | | | | | | | | | MPC85xx has been using locked L1 cache as init_ram. L1 cache is a write through cache on E6500. L2 cache is enabled to to hold the data. This patch locks/unlocks L2 cache to ensure no data cast out from L2 cache. Signed-off-by: York Sun <yorksun@freescale.com> Reported-by: Jeffery Zhu <Jefferry.Zhu@freescale.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-09-02-277/+2228
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