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* board: k2e-evm: add board supportHao Zhang2014-07-25-0/+1
| | | | | | | This patch adds Keystone2 k2e_evm evaluation board support. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* ARM: keystone2: spl: add K2E SoC supportKhoronzhuk, Ivan2014-07-25-0/+8
| | | | | | | | Keystone2 K2E SoC has slightly different spl pll settings then K2HK, so correct this. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* ARM: keystone2: add MSMC cache coherency support for K2E SOCHao Zhang2014-07-25-8/+26
| | | | | | | | | | This patch adds Keystone2 K2E SOC specific code to support MSMC cache coherency. Also create header file for msmc to hold its API. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* ARM: keystone2: clock: add K2E clock supportHao Zhang2014-07-25-5/+202
| | | | | | | | This patch adds clock definitions and commands to support Keystone2 K2E SOC. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* ARM: keystone2: add K2E SoC hardware definitionsHao Zhang2014-07-25-44/+105
| | | | | | | | | | | This patch adds hardware definitions specific to Keystone II K2E device. It has a lot common definitions with k2hk SoC, so move them to common hardware.h. This is preparation patch for adding K2E SoC support. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* ARM: keystone: clock: move K2HK SoC dependent code in separate fileKhoronzhuk, Ivan2014-07-25-145/+166
| | | | | | | | | | This patch in general spit SoC type clock dependent code and general clock code. Before adding keystone II Edison k2e SoC which has slightly different dpll set, move k2hk dependent clock code to separate clock-k2hk.c file. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* k2hk: use common KS2_ prefix for all hardware definitionsKhoronzhuk, Ivan2014-07-25-130/+120
| | | | | | | | | | | | | | | | Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and add KS2_ prefix where it's needed. It requires to change names also in places where they're used. Align lines and remove redundant definitions in kardware-k2hk.h at the same time. Using common KS2_ prefix helps resolve redundant redefinitions and adds opportunity to use KS2_ definition across a project not thinking about what SoC should be used. It's more convenient and we don't need to worry about the SoC type in common files, hardware.h will think about that. The hardware.h decides definitions of what SoC to use. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* keystone2: add possibility to turn off all dspsHao Zhang2014-07-25-2/+83
| | | | | | | | | | By default all DSPs are turned off, for another case option to turn off them is added in this commit. Also add command to turn off itself. Acked-by: Murali Karicheri <m-maricheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* keystone2: move cpu_to_bus() to keystone.cHao Zhang2014-07-25-0/+29
| | | | | | | | | The SoC related common functions in board.c should be placed to a common keystone.c arch file. Acked-by: Murali Karicheri <m-maricheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* ARM: keystone2: keystone_nav: make it dependent on keystone driverKhoronzhuk, Ivan2014-07-25-1/+1
| | | | | | | | | | | This driver is needed in case if keystone driver is used. Currently only keystone_net driver uses it. So to avoid redundant code compilation make the keystone_nav dependent on keystone net driver. It also leads to compilation errors for boards that does't use it. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* keystone2: ddr: add DDR3 PHY configs updated for PG 2.0Hao Zhang2014-07-25-0/+22
| | | | | | | | | Add DDR3 PHY configs updated for PG 2.0 Also add DDR3A PHY reset before init for PG2.0 SoCs. Acked-by: Murali Karicheri <m-maricheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* keystone: ddr3: add ddr3.h to hold ddr3 APIKhoronzhuk, Ivan2014-07-25-42/+58
| | | | | | | | It's convinient to hold ddr3 function definitions in separate file such as ddr3.h. So move this from hardware.h to ddr3.h. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* ARM: keystone2: psc: use common PSC baseKhoronzhuk, Ivan2014-07-25-24/+22
| | | | | | | | Use common keystone2 Power Sleep controller base address instead of directly deciding which keystone2 SoC is used in psc module. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* ARM: omap: Remove unused arch/arm/cpu/armv7/omap3/mem.cStefan Roese2014-07-25-139/+0
| | | | | | | | | | | | These functions have been merged into the common GPMC init code with this commit a0a37183 (ARM: omap: merge GPMC initialization code for all platform). The file is not compiled any more. So remove it as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pekon Gupta <pekon@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: Pekon Gupta <pekon@ti.com>
* ARM: omap: Fix GPMC init for OMAP3 platformsStefan Roese2014-07-25-1/+1
| | | | | | | | | | | | | | | | | | | Commit a0a37183 (ARM: omap: merge GPMC initialization code for all platform) broke NAND on OMAP3 based platforms. I noticed this while testing the latest 2014.07-rc version on the TAO3530 board. NAND detection did not work with this error message: NAND: nand: error: Unable to find NAND settings in GPMC Configuration - quitting As OMAP3 configs don't set CONFIG_NAND but CONFIG_NAND_CMD. the GPMC was not initialized for NAND at all. This patch now fixes this issue. Tested on TAO3530 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pekon Gupta <pekon@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: Pekon Gupta <pekon@ti.com>
* am335x_evm / gumstix pepper: Correct DDR settingsTom Rini2014-07-25-4/+0
| | | | | | | | | | | | | | As noted by clang, we have been shifting certain values out of 32bit range when setting some DDR registers. Upon further inspection these had been touching reserved fields (and having no impact). These came in from historical bring-up code and can be discarded. Similarly, we had been declaring some fields as 0 when they will be initialized that way. Tested on Beaglebone White. Reported-by: Jeroen Hofstee <jeroen@myspectrum.nl> Cc: Ash Charles <ash@gumstix.com> Signed-off-by: Tom Rini <trini@ti.com> Tested-By: Ash Charles <ashcharles@gmail.com>
* socfpga: Relocate arch common functions away from boardChin Liang See2014-07-05-0/+24
| | | | | | | | | | | | | To move the arch common function away from board folder to arch/arm/cpu/armv7/socfpga folder. Its to avoid code duplication for other non Altera dev kit which is using socfpga device. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Detlev Zundel <dzu@denx.de>
* arm: Fix armv8 compilation errorShaibal.Dutta2014-07-05-1/+1
| | | | | | | | | | | Fix following compilation error when CONFIG_ARM64 is defined Error: unknown or missing system register name at operand 2 -- `mrs x0,daifmsr daifset,#3' Signed-off-by: Shaibal.Dutta <shaibal.dutta@broadcom.com> Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Darwin Rambo <drambo@broadcom.com>
* arm: spl: fix include guardJeroen Hofstee2014-07-05-2/+2
| | | | | cc: Tom Rini <trini@ti.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* socfpga: Adding Scan Manager driverChin Liang See2014-07-05-1/+305
| | | | | | | | | | | | Scan Manager driver will be called to configure the IOCSR scan chain. This configuration will setup the IO buffer settings Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* socfpga: Adding DesignWare watchdog supportChin Liang See2014-07-05-0/+1
| | | | | | | | | | | To enable the DesignWare watchdog support at SOCFPGA Cyclone V dev kit. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
* arm: ep9315: Return back Cirrus Logic EDB9315A board supportSergey Kostanbaev2014-07-04-27/+521
| | | | | | | This patch returns back support for old ep93xx processors family Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com> Cc: albert.u.boot@aribaud.net
* ARM: cache_v7: use __weakJeroen Hofstee2014-07-04-55/+15
| | | | | | | | | | This is not only more readable but also prevents a warning about a missing prototype. The prototypes which are actually missing are added. cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: Tom Rini <trini@ti.com>
* ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board supportYork Sun2014-07-04-2/+2
| | | | | | | | | | | | | | | | LS2085A is an ARMv8 implementation. This adds board support for emulator and simulator: Two DDR controllers UART2 is used as the console IFC timing is tightened for speedy booting Support DDR3 and DDR4 as separated targets Management Complex (MC) is enabled Support for GIC 500 (based on GICv3 arch) Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
* armv8/fsl-lsch3: Add support to load and start MC FirmwareJ. German Rivera2014-07-03-0/+11
| | | | | | | | | | | | | | | | Adding support to load and start the Layerscape Management Complex (MC) firmware. First, the MC GCR register is set to 0 to reset all cores. MC firmware and DPL images are copied from their location in NOR flash to DDR. MC registers are updated with the location of these images. Deasserting the reset bit of MC GCR register releases core 0 to run. Core 1 will be released by MC firmware. Stop bits are not touched for this step. U-boot waits for MC until it boots up. In case of a failure, device tree is updated accordingly. The MC firmware image uses FIT format. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
* ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoCYork Sun2014-07-03-1/+937
| | | | | | | | | | | | | | Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
* ARMv8: Adjust MMU setupYork Sun2014-07-03-30/+44
| | | | | | | Make MMU function reusable. Platform code can setup its own MMU tables. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
* Added 64-bit MMIO accessors for ARMv8J. German Rivera2014-07-03-0/+8
| | | | | | | This is needed for accessing peripherals with 64-bit MMIO registers, from ARMv8 processors. Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
* arm: Add support for semihosting for armv8 fastmodel targets.Darwin Rambo2014-07-03-0/+255
| | | | | | | | | | | | | | | | | | | | | | The armv8 ARM Trusted Firmware (ATF) can be used to load various ATF images and u-boot, and does this for virtual platforms by using semihosting. This commit extends this idea by allowing u-boot to also use semihosting to load the kernel/ramdisk/dtb. This eliminates the need for a bootwrapper and produces a more realistic boot sequence with virtual models. Though the semihosting code is quite generic, support for armv7 in fastmodel is less useful due to the wide range of available silicon and the lack of a free armv7 fastmodel, so this change contains an untested armv7 placeholder for the service trap opcode. Please refer to doc/README.semihosting for a more detailed description of semihosting and how it is used with the armv8 virtual platforms. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Cc: trini@ti.com Cc: fenghua@phytium.com.cn Cc: bhupesh.sharma@freescale.com
* Merge remote-tracking branch 'u-boot-samsung/master'Albert ARIBAUD2014-07-01-193/+582
|\ | | | | | | | | | | | | | | Conflicts: boards.cfg Conflict was trivial between goni maintainer change and lager_nor removal.
| * Exynos5420: Introduce support for the Peach-Pit boardAkshay Saraswat2014-06-23-93/+281
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the Exynos5420 chip is used in both Smdk5420 and in the Peach-Pit line of devices, there could be other boards using the same chip, so a common configuration file is being added (exynos5420.h) as well as two common device tree files (exynos54xx.dtsi & exynos5420.dtsi). The peach board as declared in boards.cfg is a copy of smdk5420 declaration. The configuration files are similar, but define different default device trees, console serial ports and prompts. The device tree files for smdk5420 and peach-pit inherit from the same common file. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5420: Let macros be used for exynos5420Akshay Saraswat2014-06-23-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Macros defined in exynos5_setup.h specific to SMDK5420 are required for Peach-Pit too. Hence, replacing CONFIG_SMDK5420 with CONFIG_EXYNOS5420 to enable these macros for all the boards based on Exynos5420. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5420: DMC: Add software read levelingAkshay Saraswat2014-06-13-7/+255
| | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes Read DQ and DQS are not in phase. Since, this phase shift differs from board to board, we need to calibrate it at DRAM init phase, that's read DQ calibration. This patch adds SW Read DQ calibration routine to compensate this skew. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * DMC: exynos5420: Gate CLKM to when reading PHY_CON13Doug Anderson2014-06-13-5/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when CLKM is running. If we stop CLKM when sampling it the glitches all go away, so we'll do that as per Samsung suggestion. We also check the "is it locked" bits of PHY_CON13 and loop until they show the the value sampled actually represents a locked value. It doesn't appear that the glitching and "is it locked" are related, but it seems wise to wait until the PHY tells us the value is good before we use it. In practice we will not loop more than a couple times (and usually won't loop at all). Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5420: Remove code for enabling read levelingAkshay Saraswat2014-06-13-71/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch intends to remove all code which enables hardware read leveling. All characterization environments may not cope up with h/w read leveling enabled, so we must disable this. Also, disabling h/w read leveling improves the MIF LVcc value (LVcc value is the value at which DDR will fail to work properly). Improving LVcc means we have enough voltage margin for MIF. When h/w leveling is enabled, we have almost zero volatge margin. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos5: DMC: Modify the definition of ddr3_mem_ctrl_initAkshay Saraswat2014-06-13-13/+5
| | | | | | | | | | | | | | | | | | | | Passing fewer arguments is better and mem_iv_size is never used. Let's keep only one argument and make it cleaner. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Revert "exynos: Enable PSHOLD in SPL"Minkyu Kang2014-06-13-2/+0
| | | | | | | | This reverts commit eb0dd9986c3883820ff888c3738b013c0a7d918c.
* | Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'Albert ARIBAUD2014-07-01-1/+1
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| * | tegra20: display: fix checking of return valueJeroen Hofstee2014-06-19-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | The calling code seems a bit in doubt about the return value of fdtdec_lookup_phandle. Since it returns a negative value on error (and fdt_node_offset_by_phandle as well), check for that. cc: Wei Ni <wni@nvidia.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2014-07-01-283/+94
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| * | OMAP: disable gpmc timeout safely for reenablingStefano Babic2014-06-19-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gpmc timeout is disabled and the reset counter is set to 0. However, if later a driver activates the timeout setting the reset to a valid value, the old reset value with zero is still valid for the first access. In fact, the timeout block loads the reset counter after a successful access. Found on a am335x board with a FPGA connected to the GPMC bus together with the NAND. When the FPGA driver in kernel activates the timeout, the system hangs at the first access by the NAND driver. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | omap3: board: trivial: add void for no argsJeroen Hofstee2014-06-19-2/+2
| | | | | | | | | | | | Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
| * | cpu: armv7: am33x: ddr: write emif ref_ctrl_shadow registerFelipe Balbi2014-06-19-0/+1
| | | | | | | | | | | | Signed-off-by: Felipe Balbi <balbi@ti.com>
| * | ARM: keystone: aemif: move aemif driver to drivers/memory/ti-aemif.cKhoronzhuk, Ivan2014-06-19-105/+43
| | | | | | | | | | | | | | | | | | | | | | | | Move AEMIF driver to drivers/memory/ti-aemif.c along with AEMIF definitions collected in arch/arm/include/asm/ti-common/ti-aemif.h Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | mtd: nand: davinci: add header file for driver definitionsKhoronzhuk, Ivan2014-06-19-175/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The definitions inside emif_defs.h concern davinci nand driver and should be in it's header. So create header file for davinci nand driver and move definitions from emif_defs.h and nand_defs.h to it. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> [trini: Fixup more davinci breakage] Signed-off-by: Tom Rini <trini@ti.com>
| * | omap: Don't enable GPMC CS0 with nothing attachedAsh Charles2014-06-19-1/+2
| |/ | | | | | | | | | | | | | | | | | | | | If CONFIG_(NAND|NOR|ONENAND) is not defined, no configuration is set for GPMC on chip select #0---size is 0. In this case, the GPMC configuration should be reset but not enabled. Enabling causes the Gumstix DuoVero board to hang when entering Linux. Signed-off-by: Ash Charles <ashcharles@gmail.com> [trini: Switch to testing base as GPMC_SIZE_256M is 0x0] Signed-off-by: Tom Rini <trini@ti.com>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-06-30-162/+962
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| * | vf610: fix build due to missing sys_proto.hStefano Babic2014-06-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | commit 67a04ab3ab8522a3a34491853e46105317580df5 fix the build for MX25. The same error happens for VF610 SOC. Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | imx: correct HAB status for new chip TOStefano Babic2014-06-17-14/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to: http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/log/?h=imx_v2009.08_3.0.35_4.1.0 ENGR00287268 mx6: fix the secure boot issue on the new tapout chip commit 424cb1a79e9f5ae4ede9350dfb5e10dc9680e90b newer i.MX6 silicon revisions have an updated ROM and HAB API table. Please see also: i.MX Applications Processors Documentation Engineering Bulletins EB803, i.MX 6Dual/6Quad Applications Processor Silicon Revsion 1.2 to 1.3 Comparison With this change the secure boot status is correctly displayed Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | mx6: Fix definition of IOMUXC_GPR12_DEVICE_TYPE_RCFabio Estevam2014-06-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mx6 reference manual incorrectly states that the DEVICE_TYPE field of IOMUXC_GPR12 register should be configured as '0010' for setting the PCI controller in RC mode. The correct value should be '0100' instead. This also aligns with the same value used in the mx6 pci kernel driver. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
generated by cgit v1.1 at 2024-11-14 22:28:16 +0000