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* zynq: timer: Fix wrong timer calculationSiva Durga Prasad Paladugu2015-04-29-1/+3
| | | | | | | | | | Fix wrong timer calculation in get_timer_masked incase of overflow. This fixes the issue of getting wrong time from get_timer() calls. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynqmp: Add support for R5 sw loadingMichal Simek2015-04-29-3/+283
| | | | | | | Add support for loading sw for R5 with enabling for zynqmp. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
* zynqmp: caches: Enable dcache for zynqmpSiva Durga Prasad Paladugu2015-04-29-0/+164
| | | | | | | | Define the mmu table till 2MB granularity enable dcaches for zynqmp. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: slcr: Disable all level shiftersSiva Durga Prasad Paladugu2015-04-29-0/+7
| | | | | | | | | | | Disable all level shifters before enabling the PS-to-PL level shifters as it would be good to disable all level shifters before enabling the PS-to-PL in order to ensure that it is in proper state Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM: zynq: drop legacy ps7_init.c/h supportMasahiro Yamada2015-04-29-1/+1
| | | | | | | | | | | | | | We are about to change the location for ps7_init files, breaking the current work-flows. It is good time to drop the legacy ps7_init.c/h support. Going forward, please use ps7_init_gpl.c/h all the time. If you are still using old Xilinx tools that are only able to generate ps7_init.c/h, rename them into ps7_init_gpl.c/h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: Add Zynq PicoZed board supportNathan Rossi2015-04-29-0/+28
| | | | | | | | | | | | | | | | | | The PicoZed is a System-on-Module board which is marketed as part of the ZedBoard/MicroZed/etc. collection. It includes a Zynq-7000 processor. This patch adds support that covers all the variants of the PicoZed including the SKUs with Z7010/Z7020 and Z7015/Z7030 Zynq chips. This patch set however only covers support for the System-on-Module and does not cover any extra components that are available on carrier boards (except those that are fanned out of the module itself). More information on this board, its variants and available carrier boards is available at: http://zedboard.org/product/picozed Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* gpio: add Xilinx Zynq PS GPIO driverAndrea Scian2015-04-29-0/+66
| | | | | | | | | Most of the code is taken (and adapted) from Linux kernel driver. Just add CONFIG_ZYNQ_GPIO to you config to enable it Signed-off-by: Andrea Scian <andrea.scian@dave.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2015-04-24-7/+8
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| * MIPS: implement device-tree handover to Linux kernelDaniel Schwierzeck2015-04-24-7/+8
| | | | | | | | | | | | | | | | | | | | | | Add device-tree handover to Linux kernel conforming with MIPS UHI [1]. Register $a0 will be set to the reserved value -2. The address of the device-tree blob will be stored as KSEG0 address in $a1. $a2 and $a3 are set to zero. [1] http://prplfoundation.org/wiki/MIPS_documentation Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-04-24-316/+956
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| * armv8/fsl-lsch3: Implement workaround for I2C erratum A009203York Sun2015-04-23-0/+34
| | | | | | | | | | | | | | | | This erratum requires setting GLITCH_EN bit in debug register to enable digital filter to improve clock stability. Signed-off-by: York Sun <yorksun@freescale.com> CC: Heiko Schocher <hs@denx.de>
| * ls2085a: esdhc: Add esdhc support for ls2085aYangbo Lu2015-04-23-0/+19
| | | | | | | | | | | | | | This patch adds esdhc support for ls2085a. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085ardb: Enable NAND SPL supportScott Wood2015-04-23-0/+14
| | | | | | | | | | | | | | | | | | | | Enable NAND boot support using SPL framework. To boot from NAND, either use DIP switches on board, or "qixis_reset nand" command. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <scottwood@freescale.com> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085aqds: NAND boot supportScott Wood2015-04-23-0/+180
| | | | | | | | | | | | | | | | | | This adds NAND boot support for LS2085AQDS, using SPL framework. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <scottwood@freescale.com> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <yorksun@freescale.com>
| * driver/ifc: Add 64KB page supportJaiprakash Singh2015-04-23-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IFC has two register pages.Till IFC version 1.4 each register page is 4KB each.But IFC ver 2.0 register page size is 64KB each.IFC regiters structure is break into two viz FCM and RUNTIME.FCM(Flash control machine) registers are defined in PAGE0 and controls IFC generic functionality. RUNTIME registers are defined in PAGE1 and controls NAND and GPCM funcinality. FCM and RUNTIME structures defination is common for IFC version 1.4 and 2.0. Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085ardb: Add support of LS2085ARDB platformYork Sun2015-04-23-2/+13
| | | | | | | | | | | | | | | | | | | | The LS2085ARDB is a evaluation platform that supports LS2085A family SoCs. This patch add sbasic support for the platform. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * armv8/ls2085aqds: Add support of LS2085AQDS platformYork Sun2015-04-23-8/+73
| | | | | | | | | | | | | | | | | | The LS2085AQDS is an evaluatoin platform that supports the LS2085A family SoCs. This patch add basic support of the platform. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
| * driver/ldpaa: Add support of WRIOP static data structurePrabhakar Kushwaha2015-04-23-1/+33
| | | | | | | | | | | | | | | | | | | | | | | | Wire rate IO Processor (WRIOP) provide support of receive and transmit ethernet frames from the ethernet MAC. Here Each WRIOP block supports upto 64 DPMACs. Create a house keeping data structure to support upto 16 DPMACs and store external phy related information. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-ch3: Add support to print RCW configurationBhupesh Sharma2015-04-23-0/+14
| | | | | | | | | | | | | | | | This patch adds support to print out the Reset Configuration Word information. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * net/memac_phy: reuse driver for little endian SoCsShaohui Xie2015-04-23-264/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The memac for PHY management on little endian SoCs is similar on big endian SoCs, so we modify the driver by using I/O accessor function to handle the endianness, so the driver can be reused on little endian SoCs, we introduce CONFIG_SYS_MEMAC_LITTLE_ENDIAN for little endian SoCs, if the CONFIG_SYS_MEMAC_LITTLE_ENDIAN is defined, the I/O access is little endian, if not, the I/O access is big endian. Move fsl_memac.h out of powerpc include. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * drivers/fsl-mc: Changed MC firmware loading for new boot architectureJ. German Rivera2015-04-23-0/+8
| | | | | | | | | | | | | | | | | | | | | | Changed MC firmware loading to comply with the new MC boot architecture. Flush D-cache hierarchy after loading MC images. Add environment variables "mcboottimeout" for MC boot timeout in milliseconds, "mcmemsize" for MC DRAM block size. Check MC boot status before calling flib functions. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8: Add SerDes framework for Layerscape ArchitectureMinghuan Lian2015-04-23-0/+308
| | | | | | | | | | | | | | | | | | | | | | Add support of SerDes framework for Layerscape Architecture. - Add support of 2 SerDes block - Add SerDes protocol parsing and detection - Create table of SerDes protocol supported by LS2085A Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: Use correct compatible for serial clock fixupScott Wood2015-04-23-1/+1
| | | | | | | | | | | | | | | | The serial nodes in the fsl-lsch3 device trees have compatible = "fsl,ns16550", "ns16550a" -- so don't look for "ns16550". Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: Add workaround for USB erratum A-008751Scott Wood2015-04-23-0/+16
| | | | | | | | | | | | | | | | Without this "USB may not work" according to the erratum text, though I did not notice a problem without it. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * fsl-lsch3: Introduce place for common early SoC initScott Wood2015-04-23-0/+23
| | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: Update early MMU tableYork Sun2015-04-23-17/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | During booting, IFC is mapped to low region. After booting up, IFC is remapped to high region for larger space. The environmental variables are also stored at high region. In order to read the variables during booting, a virtual mapping is required. Cache was enabled for entire IFC space before. Actually the first two entries are big enough (4MB) to cover the boot code and environmental variables. Remove extra entries. Move OCRAM entry out of ifdef. Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: Set nodes in DVM domainScott Wood2015-04-23-0/+15
| | | | | | | | | | | | | | This is required for TLB invalidation broadcasts to work. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: Add support for reset requestpankaj chauhan2015-04-23-0/+11
| | | | | | | | | | | | | | Add support for reset_cpu() by asserting RESET_REQ_B. Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: Fix generic timer clock sourceYork Sun2015-04-23-0/+38
| | | | | | | | | | | | | | | | | | | | The timer clock is system clock divided by 4, not fixed 12MHz. This is common to the SoC, not board specific. Primary core is fixed when u-boot still runs in board_f. Secondary cores are fixed by reading a variable set by u-boot. Signed-off-by: York Sun <yorksun@freescale.com> CC: Mark Rutland <mark.rutland@arm.com>
| * armv8/fsl-lsch3: Fix platform clock calculationYork Sun2015-04-23-4/+3
| | | | | | | | | | | | | | Platform clock is half of platform PLL. There is an additional divisor in place. Clean up code copied from powerpc. Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8/ls2085a: Update common header filePrabhakar Kushwaha2015-04-23-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ls2085a_common.h contains hard-coded information for NOR/NAND flash, I2C, DDR, etc. These are platform specific. Move them out of common header file and placed into respective board header files. Move TEXTBASE to 1MB offset to fit NOR flash with up to 1MB sector size. Enable command auto complete. Update prompt symbol. Set fdt_high to 0xa0000000 because Linux requires that the fdt be 8-byte aligned and below 512 MiB. Besides ensuring compliance with the 512 MiB limit, this avoids problems with the dtb being misaligned within the FIT image. Change the MC FW, MC DPL and Debug server NOR addresses in compliance with the NOR flash layouts for 128MB flash. Add PCIe macros. Enable "loadb" command. Disable debug server. Enable workaround for erratum A008511. Stop reset on panic for postmortem debugging. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: Implement workaround for erratum A008585York Sun2015-04-23-0/+12
| | | | | | | | | | | | | | Generic Timer may contain an erroneous value. The workaround is to read it twice until getting the same value. Signed-off-by: York Sun <yorksun@freescale.com>
| * driver/ldpaa_eth: Add LDPAA Ethernet driverPrabhakar Kushwaha2015-04-23-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LDPAA Ethernet driver is a freescale's new ethernet driver based on Layerscape architecture. Every ethernet driver controls on DPNI object. Where all DPNIs share one common DPBP and DPIO object to support Rx and Tx flows. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Cristian Sovaiala <cristian.sovaiala@freescale.com> CC: Bogdan Hamciuc <bogdan.hamciuc@freescale.com> CC: J. German Rivera <German.Rivera@freescale.com> [York Sun: s/NetReceive/net_process_received_packet] Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/fsl-mc: Add support of MC FlibsPrabhakar Kushwaha2015-04-21-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's Layerscape Management Complex (MC) provide support various objects like DPRC, DPNI, DPBP and DPIO. Where: DPRC: Place holdes for other MC objectes like DPNI, DPBP, DPIO DPBP: Management of buffer pool DPIO: Used for used to QBMan portal DPNI: Represents standard network interface These objects are used for DPAA ethernet drivers. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com> Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * fsl-ch3/README: Add description for NOR flash layout (firmware images)Bhupesh Sharma2015-04-21-0/+25
| | | | | | | | | | | | | | | | This patch adds description for NOR flash layout (firmware images) in the README file for LS2085A platforms. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: Add Freescale Debug Server driverBhupesh Sharma2015-04-21-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | The Debug Server driver is responsible for loading the Debug server FW on the Service Processor (Cortex-A5 core) on LS2085A like SoCs and then polling for the successful initialization of the same. TOP MEM HIDE is adjusted to ensure the space required by Debug Server FW is accounted for. MC uses the DDR area which is calculated as: MC DDR region start = Top of DDR - area reserved by Debug Server FW Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * QE/DeepSleep: add QE deepsleep support for mpc85xxZhao Qiang2015-04-21-4/+0
| | | | | | | | | | | | | | | | Muram will power off during deepsleep, and the microcode of qe in muram will be lost, it should be reload when resume. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * pci/layerscape: remove unnecessary pcie_layerscape.hMinghuan Lian2015-04-21-13/+0
| | | | | | | | | | | | | | | | | | | | The patch uses the common function name ft_pci_setup to replace ft_pcie_setup, then removes unnecessary pcie_layerscape.h because all the functions have been declared in common.h. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * Add bootscript support to esbc_validate.gaurav rana2015-04-21-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Default environment will be used for secure boot flow which can't be edited or saved. 2. Command for secure boot is predefined in the default environment which will run on autoboot (and autoboot is the only option allowed in case of secure boot) and it looks like this: #define CONFIG_SECBOOT \ "setenv bs_hdraddr 0xe8e00000;" \ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ "esbc_halt;" #endif 3. Boot Script can contain esbc_validate commands and bootm command. Uboot source command used in default secure boot command will run the bootscript. 4. Command esbc_halt added to ensure either bootm executes after validation of images or core should just spin. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm/ls102xa:Add support of conditional workaround implementation as per SoC verAlison Wang2015-04-21-0/+3
| | | | | | | | | | | | | | | | For LS102xA, some workarounds are only used in VER1.0, so silicon version detection are added for QDS and TWR boards. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-dmTom Rini2015-04-23-0/+63
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| * | fdt: sandbox: Move setup code from board_f to fdtdecSimon Glass2015-04-23-0/+49
| | | | | | | | | | | | | | | | | | | | | We want to be able to set up the device tree in SPL, so move this code to a common place. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | exynos: sandbox: ti: Add SPDX license identifiers and notesSimon Glass2015-04-22-0/+14
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some files I neglected to add a license. Rectify this: arch/arm/dts/exynos4210-pinctrl-uboot.dtsi arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi arch/arm/dts/exynos5250-pinctrl-uboot.dtsi arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi arch/arm/dts/s5pc100-pinctrl.dtsi arch/arm/dts/s5pc110-pinctrl.dtsi This file came from Linux and has no license information there, so add a comment to that effect: arch/sandbox/include/asm/bitops.h This file also came from Linux - presumably someone from TI could add the license: include/dt-bindings/pinctrl/omap.h Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Ingrid Viitanen <ingrid.viitanen@nokia.com>
* | usb: host: Add ehci-vf USB driver for ARM Vybrid SoC'sSanchayan Maity2015-04-23-0/+40
| | | | | | | | | | | | | | This driver adds support for the USB peripheral on Freescale Vybrid SoC's. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
* | ARM: vf610: Initial integration for Colibri VF50/VF61Sanchayan Maity2015-04-23-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds initial support for Colibri VF50/VF61 based on Freescale Vybrid SoC. - CPU clocked at 396/500 MHz - DDR3 at 396MHz - for VF50, use PLL2 as memory clock (synchronous mode) - for VF61, use PLL1 as memory clock (asynchronous mode) - Console on UART0 (Colibri UART_A) - Ethernet on FEC1 - PLL5 based RMII clocking (E.g. No external crystal) - UART_A and UART_C I/O muxing - Boot from NAND by default Tested on Colibri VF50/VF61 booting using serial loader over UART. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Acked-by: Stefan Agner <stefan@agner.ch>
* | ARM: vf610: Enable cachesStefan Agner2015-04-23-0/+16
| | | | | | | | | | | | | | | | Enables caches which provides a rather huge speedup of the boot loader. Also mark the on-chip RAM as cachable since this is the area U-Boot runs from. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
* | ARM: vf610: Add SoC and CPU type detectionSanchayan Maity2015-04-23-2/+39
| | | | | | | | | | | | | | | | | | | | | | Vybrid product family consists of several rather similar SoC which can be determined by softare during boot time. This allows use of variable ${soc} for Linux device tree files. Detect VF5xx CPU's by reading the CPU count register. We can determine the second number of the CPU type (VF6x0) which indicates the presence of a L2 cache. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
* | ARM: vf610: Enable external 32KHz oscillatorStefan Agner2015-04-23-1/+11
| | | | | | | | | | | | | | Enable the SCSC (Slow Clock Source Controller) and select the external 32KHz oscillator. This improves the accuracy of the RTC. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
* | ARM: vf610: Move DDR3 initialization to imx-commonSanchayan Maity2015-04-23-2/+355
| | | | | | | | | | | | | | | | | | | | In order to avoid code duplication, move the DDR3 initialization to the common place under imx-common. Currently ROW_DIFF and COL_DIFF can be chosen from the board file. The JEDEC timings are specified using a common ddr3_jedec_timings structure. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
* | arm: am437x: mux: Update mux namesBryan De Faria2015-04-23-31/+56
| | | | | | | | | | | | Correct and complete the mux names following AM437x Technical Reference Manual. Signed-off-by: Bryan De Faria <bdefaria-ext@adeneo-embedded.com>
generated by cgit v1.1 at 2024-11-10 14:22:13 +0000