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* davinci: omapl138_lcdk: configure ddr2Fabien Parent2016-12-03-0/+1
| | | | | | | | The SPL is unable to load u-boot because the DDR2 is not configured. Configure the DDR2. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* davinci: omapl138_lcdk: configure pll0Fabien Parent2016-12-03-0/+1
| | | | | | | | The SPL is not able to boot properly because the PLL0 is not configured. Configure it. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: davinci: Move CONFIG_SYS_DA850_DDR_INIT to KconfigFabien Parent2016-12-03-0/+7
| | | | | | | | Clean config headers by moving CONFIG_SYS_DA850_DDR_INIT away to a Kconfig file. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: davinci: Move CONFIG_SYS_DA850_PLL_INIT to KconfigFabien Parent2016-12-03-0/+7
| | | | | | | | Clean config headers by moving CONFIG_SYS_DA850_PLL_INIT away to a Kconfig file. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7x/AM57xx: Get rid of CONFIG_AM57XXNishanth Menon2016-12-03-8/+8
| | | | | | | | | | | CONFIG_AM57XX is just an unnecessary macro that is redundant given So, remove the same instead of spreading through out the u-boot source code and getting in the way to maintain common code for DRA7x family. Acked-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: K2G: DDR3: Fix up priv ID for MPUNishanth Menon2016-12-03-4/+19
| | | | | | | | | | | | | | For ECC enabled DDR, we use EDMA to reset all memory values to 0. For K2E/L/H/K the priv ID of 8 was indicative of ARM, but that is not the case for K2G, where it is 1. Unfortunately, ddr3 code had hard coded the privID and had missed identification previously. Fix the same, else unforeseen behavior can be expected in our reset of DDR contents to 0 for ECC enablement. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* sh: generate position independent code for all platformsVladimir Zapolskiy2016-12-02-1/+2
| | | | | | | | | | | | | | Finally add fpic compilation option to produce relocatable code. Note that this requires to define CONFIG_NEEDS_MANUAL_RELOC for all board files, also relocation support still has some limitations (e.g. a developer should care not to overwrite the executing code or memset() with zeroes not yet relocated data on malloc init etc.), which may be fixed while switching to PIE. Due to short investigation the architecture code is not ready for PIE linking, this will require some manipulations with .dyn* sections. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* sh: share the correct version of start.S among all cpusVladimir Zapolskiy2016-12-02-135/+9
| | | | | | | | | | | It is easy to note that SH2/SH3/SH4 start.S code is practically the same with a minor difference for SH2 where a short data header is present. To avoid unwanted code duplication and to automatically convert SH2 and SH3 platforms to generic board support move fixed SH4 start.S into arch/sh/lib/start.S and share it among all platforms. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sh4: fix start.S by calling board_init_f() after first code relocationVladimir Zapolskiy2016-12-02-12/+11
| | | | | | | | | | | | | | | | | Like on ARM platform keep the first code relocation from a U-boot image storage to RAM at CONFIG_SYS_TEXT_BASE, then pass execution to a generic board_init_f() with empty GD flags. If CONFIG_SYS_TEXT_BASE is equal to a calculated by board_init_f() relocation address there will be no more code and data copy, however it's worth to mention that the first copy happens even if $pc on _start is the same as CONFIG_SYS_TEXT_BASE, on practice this works without a problem. Also note that _sh_start is renamed back to _start to correct gd->mon_len calculation by setup_mon_len(), the opposite rename was done in pre-generic board commit 2024b968ee9 ("sh: Fix build in start.S"). Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sh: add shared relocate_code() function and call board_init_r()Vladimir Zapolskiy2016-12-02-18/+18
| | | | | | | | | | | | | Commits b61e90e6fd83 ("sh: Drop the arch-specific board init") and f41e6088eb1a ("sh: Fix build errors for generic board") left code and data relocation done in start.S, however further actual U-boot configuration is not started anymore. Practically SH boards with the code relocated into the expected position by start.S still can be booted, so the change adds this option and provides an option how to relocate code for board_init_r() execution. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sh: add common dram_init() function for all boardsVladimir Zapolskiy2016-12-02-1/+18
| | | | | | | | | | | Generic board support assumes a different method of specifying DRAM size on board, also it can be shared among all boards, notably only sh7763rdp board has a custom legacy dram_init(), however the difference is only in printing some additional information, this feature can be removed. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sh: add MEMORY command to a shared linker scriptVladimir Zapolskiy2016-12-02-16/+16
| | | | | | | | | At the moment in runtime all defined sections are copied into or created in RAM, specify this explicitly to assert potential out of RAM placements of the sections. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sh: define entry point and reloc_dst inside a linker scriptVladimir Zapolskiy2016-12-02-6/+1
| | | | | | | | | | No functional change, concentrate linker script commands in one place for convenience. Entry point is set to CONFIG_SYS_TEXT_BASE by default on build, so this option can be omitted from being added to the linker script. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sh: place board lowlevel_init code in the beginning of .textVladimir Zapolskiy2016-12-02-1/+1
| | | | | | | | | Reference lowlevel_init of all supported SH2A/SH3/SH4/SH4A boards from a shared linker script, the lowlevel_init function will be called by a relative address. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sh4: use single u-boot linker script for all boardsVladimir Zapolskiy2016-12-02-0/+4
| | | | | | | | | | | | | | Three supported SH4/SH4A boards with the bootloader image stored on SPI flash have own flavour of a linker script, in turn they are equal among each other. The only difference is that the text from lowlevel_init.o is placed right after start.o, which makes sense. Note that .bss section is not marked as NOLOAD, because for about 10 years this is a default option of a GNU linker, either the attribute is found or not the resulting image file is the same. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sh4: remove __io config options from r2dplus and r7780mp boardsVladimir Zapolskiy2016-12-02-10/+0
| | | | | | | | Defined __io is no-op for the SH architecture and it can be removed from board files without any functional change. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sh4: cache: move exported cache manipulation functions into cache.cVladimir Zapolskiy2016-12-02-39/+36
| | | | | | | | | No functional change, moving cache manipulation functions into cache.c allows to collect all of them in a single location and as a pleasant side effect cache_control() function can be unexported now. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sh: cache: don't modify CCR from P1 areaVladimir Zapolskiy2016-12-02-5/+3
| | | | | | | | | | | cache_wback_all() is a local function and it is called from cache_control() only, which is in turn jumps to P2 area. The change fixes an issue when cache_wback_all() returns from P2 to P1, however cache_control() continues to manipulate with CCR register, according to the User's Manual this is restricted. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* sh: cache use jump_to_P2() and back_to_P1() from asm/system.hVladimir Zapolskiy2016-12-02-37/+2
| | | | | | | | Both jump_to_P2() and back_to_P1() functions are found in asm/system.h header file and functionally they are the same, don't redefine them. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sh3: remove unused cache.c file from being builtVladimir Zapolskiy2016-12-02-97/+1
| | | | | | | | | | | | | The change is similar to commit 994b56616bae ("sh: delete an unused source file") for SH2, however here the removed cache.c file was built and included into an image as a dead code. If it is needed in future the contents can be reused from a similar arch/sh/cpu/sh4/cache.c file, which is in turn will be moved to a shared among all core flavours location at arch/sh/lib/cache.c. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sh4: cache: correct flush_cache() to writeback and invalidateVladimir Zapolskiy2016-12-02-1/+1
| | | | | | | | | | In common usecases flush_cache() assumes both cache invalidation and write-back to memory, instead of doing cache invalidation only with the wrapped 'ocbi' instruction pin flush_cache() to cache invalidation with memory write-back done by 'ocbp'. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* sh4: cache: correct dcache flush to invalidate with write-backVladimir Zapolskiy2016-12-02-1/+1
| | | | | | | | | | | | | | | In common usecases flush_cache() assumes both cache invalidation and write-back to memory, thus in flush_dcache_range() implementation change SH4 cache write-back only instruction 'ocbwb' with cache purge instruction 'ocbp', according to the User's Manual there should be no performance penalty for that. Note that under circumstances only cache invalidation is expected from flush_cache() call, in these occasional cases the current version of flush_cache() works, which is a wrapper over invalidate_dcache_range() at the moment, this will be fixed in the following change. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* ARM: zynq: Enable SD1 and qspi for picozed boardSiva Durga Prasad Paladugu2016-12-02-0/+12
| | | | | | | Enable SD1 and qspi for picozed board. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: List secondary software boot modesMichal Simek2016-12-02-0/+15
| | | | | | | | Using alternative bootmode field to support automatic secondary boot modes. It is purely software setting where SW modes are using free bootmode combinations. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* ARM64: zynqmp: Force certain bootmode for SPLMichal Simek2016-12-02-1/+1
| | | | | | | | ZynqMP provides an option to overwrite bootmode setting which can change SPL behavior. For example: boot SPL via JTAG and then SPL loads images from SD. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm: mvebu: move SYS_MVEBU_PLL_CLOCK to KconfigChris Packham2016-12-01-3/+6
| | | | | | | | | | The main PLL frequency is 2GHz for Armada-XP and 1GHZ for Armada 375, 38x and 39x. [ Linux commit ae142bd9976532aa5232ab0b00e621690d8bfe6a ] Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2016-11-30-63/+582
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| * MIPS: Fix map_physmem for cached mappingsPaul Burton2016-11-30-1/+1
| | | | | | | | | | | | | | | | | | | | map_physmem should return a pointer that can be used by the CPU to access the given memory - on MIPS simply returning the physical address as it does prior to this patch doesn't achieve that. Instead return a pointer to the memory within (c)kseg0, which matches up consistently with the (c)kseg1 pointer that uncached mappings return via ioremap. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Use ram_top, not bi_memsize, in arch_lmb_reservePaul Burton2016-11-30-1/+1
| | | | | | | | | | | | | | | | | | When calculating the region to reserve for the stack in arch_lmb_reserve, make use of ram_top instead of adding bi_memsize to CONFIG_SYS_SDRAM_BASE. This avoids overflow if the system has enough memory to reach the end of the address space. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * mips: Let cache.h be included from assembly sourceMarek Vasut2016-11-30-0/+2
| | | | | | | | | | | | | | | | | | Add ifdef __ASSEMBLY__ around the function prototype to let cache.h be included from assembly code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
| * MIPS: add handling for generic and EJTAG exceptionsDaniel Schwierzeck2016-11-30-0/+344
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add exception handlers for generic and EJTAG exceptions. Most of the assembly code is imported from Linux kernel and adapted to U-Boot. The exception vector table will be reserved above the stack before U-Boot is relocated. The exception handlers will be installed and activated after relocation in the initr_traps hook function. Generic exceptions are handled by showing a CPU register dump similar to Linux kernel. For example: malta # md 1 00000001: Ooops: $ 0 : 00000000 00000000 00000009 00000004 $ 4 : 8ff7e108 00000000 0000003a 00000000 $ 8 : 00000008 00000001 8ff7cd18 00000004 $12 : 00000002 00000000 00000005 0000003a $16 : 00000004 00000040 00000001 00000001 $20 : 00000000 8fff53c0 00000008 00000004 $24 : ffffffff 8ffdea44 $28 : 90001650 8ff7cd00 00000004 8ffe6818 Hi : 00000000 Lo : 00000004 epc : 8ffe6848 (text bfc28848) ra : 8ffe6818 (text bfc28818) Status: 00000006 Cause : 00000410 (ExcCode 04) BadVA : 8ff9e928 PrId : 00019300 ### ERROR ### Please RESET the board ### EJTAG exceptions are checked for SDBBP and delegated to the SDBBP handler if necessary. Otherwise the debug mode will simply be exited. The SDBBP handler currently prints the contents of registers c0_depc and c0_debug. This could be extended in the future to handle semi-hosting according to the MIPS UHI specification. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Tested-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: reserve space for exception vectorsDaniel Schwierzeck2016-11-30-0/+20
| | | | | | | | | | | | | | | | | | | | | | In order to set own exception handlers, a table with the exception vectors must be built in DRAM and the CPU EBase register must be set to the base address of this table. Reserve the space above the stack and use gd->irq_sp as storage for the exception base address. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: add asm-offsets for struct pt_regsDaniel Schwierzeck2016-11-30-0/+66
| | | | | | | | | | | | | | Import asm-offsets.c from kernel to generate offset for struct pt_regs needed by exception handlers. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: add possibility to setup initial stack and global data in SRAMDaniel Schwierzeck2016-11-30-0/+18
| | | | | | | | | | | | | | | | | | | | This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which a SoC can select if it supports some kind of SRAM. Together with CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be set up in that SRAM. This can be used to provide a C environment also for lowlevel_init(). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: factor out code for initial stack and global dataDaniel Schwierzeck2016-11-30-26/+30
| | | | | | | | | | | | | | Move the code for setting up the initial stack and global data to a macro to be able to use it more than once. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: fix iand optimize setup of CP0 registersDaniel Schwierzeck2016-11-30-24/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Clear cp0 status while preserving implementation specific bits. Set bits BEV and ERL as the arch specification requires after a reset or soft-reset exception. Extend and fix initialization of watch registers. Check if additional watch register sets are implemented and initialize them too. Initialize cp0 count as early as possible to get the most accurate boot timing. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: fix ROM exception vectorsDaniel Schwierzeck2016-11-30-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | When booting from ROM, early exceptions can't be handled properly. Instead of busy-looping give the developer the possibilty to examine the situation. Invoke an UHI exception operation which can be read as unhandled exception by a hardware debugger if one is attached. If the debugger doesn't support UHI, the exception is read as unexpected breakpoint. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: make inclusion of ROM exception vectors configurableDaniel Schwierzeck2016-11-30-3/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds a compile time option to include code for static exception vectors. Static exception vectors are only needed, when the U-Boot entry point is equal to the CPU reset exception vector address. For instance this is the case when U-Boot is used as ROM in Qemu or booted from parallel NOR flash. When U-Boot is booted from RAM (e.g. loaded there by SPL), the exception vectors need to be setup dynamically, which is done in follow-up commits. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-11-30-54/+174
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| * imx6: clock: Enable External Memory Interface [EIM] clock (eim_slow_clock)Lukasz Majewski2016-11-30-0/+15
| | | | | | | | | | | | | | | | This patch extends the imx6 clock code to enable or disable the EIM slow clock, which in necessary when one wants to use EIM interface t o read/write from external memory (e.g. NOR). Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
| * mx6sx: Add initial support for Samtec VIN|ING 2000 boardChristoph Fritz2016-11-30-0/+7
| | | | | | | | | | | | | | | | This patch adds initial support for Samtec VIN|ING 2000 board. Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Acked-by: Marek Vasut <marex@denx.de>
| * mx6sx: Add initial support for UDOO Neo BoardBreno Lima2016-11-29-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UDOO Neo Board is a development board from Seco that has three models: - UDOO Neo Basic - UDOO Neo Basic Kick Starter - UDOO Neo Extended - UDOO Neo Full All versions are based on the i.MX6 SoloX processor. For more details about the UDOO Neo board, please refer to: http://www.udoo.org/udoo-neo/ This work is based on a previous commit of Francesco Montefoschi <francesco.monte@gmail.com>: https://github.com/fmntf/u-boot/commit/877b71184a5105e708024f232d36aed574961844 Only tested on the UDOO Neo Full board. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * ARM: ts4600: add basic board supportSebastien Bourdelin2016-11-29-0/+6
| | | | | | | | | | | | | | | | This commit adds basic support including: MMC, Serial console Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routinesEric Nelson2016-11-29-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DDR calibration routines are gated by conditionals for the i.MX6DQ SOCs, but with the use of the sysinfo parameter, these are usable on at least i.MX6SDL and i.MX6SL variants with DDR3. Also, since only the Novena board currently uses the dynamic DDR calibration routines, these routines waste space on other boards using SPL. Add a KConfig entry to allow boards to selectively include the DDR calibration routines. Signed-off-by: Eric Nelson <eric@nelint.com>
| * mx6: ddr: add routine to return DDR calibration dataEric Nelson2016-11-29-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | Add routine mmdc_read_calibration() to return the output of DDR calibration. This can be used for debugging or to aid in construction of static memory configuration. This routine will be used in a subsequent patch set adding a virtual "mx6memcal" board, but could also be useful when gathering statistics during an initial production run. Signed-off-by: Eric Nelson <eric@nelint.com>
| * mx6: ddr: pass mx6_ddr_sysinfo to calibration routinesEric Nelson2016-11-29-44/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DDR calibration routines have scattered support for bus widths other than 64-bits: -- The mmdc_do_write_level_calibration() routine assumes the presence of PHY1, and -- The mmdc_do_dqs_calibration() routine tries to determine whether one or two DDR PHYs are active by reading MDCTL. Since a caller of these routines must have a valid struct mx6_ddr_sysinfo for use in calling mx6_dram_cfg(), and the bus width is available in the "dsize" field, use this structure to inform the calibration routines which PHYs are active. This allows the use of the DDR calibration routines on CPU variants like i.MX6SL that only have a single MMDC port. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * mx6: ddr: allow 32 cycles for DQS gating calibrationEric Nelson2016-11-29-0/+7
| | | | | | | | | | | | | | | | | | | | | | The DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample cycle) for the first PHY. Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0 output value isn't polluted with calibration artifacts. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * imx: mx6: ddr: add register MPZQLP2CTL for LPDDR2Eric Nelson2016-11-29-0/+2
| | | | | | | | | | | | | | | | | | Add constants for the MPZQLP2CTL DDR register for both banks to allow setting the LPDDR2 timing values in .cfg files using a named constant instead of hex addresses as is currently done in mx6slevk and other board files. Signed-off-by: Eric Nelson <eric@nelint.com>
| * imx: make ipu's di configurableMax Krummenacher2016-11-29-1/+2
| | | | | | | | | | | | | | | | | | The ipu has two display interfaces. Make the used one a parameter in struct display_info_t instead of using unconditionally DI0. DI0 is the default setting. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Reviewed-by: Eric Nelson <eric@nelint.com>
| * ARM: mx6: add MMC2 boot device detection support in SPLMarcin Niestroj2016-11-29-1/+5
| | | | | | | | | | | | | | | | | | Check BOOT_CFG2[3:4] to determine which SD/MMC port is selected to boot from. If MMC2 is selected return BOOT_DEVICE_MMC2. In all other cases return BOOT_DEVICE_MMC1, as we do not have corresponding macro for MMC3 and MMC4. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
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