summaryrefslogtreecommitdiff
path: root/arch
Commit message (Collapse)AuthorAgeLines
...
* arm: print the cache config option in hex instead of decimalKeerthy2016-11-13-1/+1
| | | | | | | Printing the option value in hex makes it more comprehensible. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-11-08-32/+69
|\
| * ARM: tegra186: call secure monitor for all cache-wide opsStephen Warren2016-11-07-3/+21
| | | | | | | | | | | | | | | | | | An SMC call is required for all cache-wide operations on Tegra186. This patch implements the two missing hooks now that U-Boot supports them, and fixes the mapping of "hook name" to SMC call code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * armv8: add hooks for all cache-wide operationsStephen Warren2016-11-07-11/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: translate __asm_flush_l3_cache to assemblyStephen Warren2016-11-07-23/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When performing a cache disable function, code must not access DRAM. That is because when the cache is disabled, it will be bypassed and all loads and stores will be serviced by RAM. This prevents accessing any dirty data in the cache. In turn, this means the stack cannot be used, since that is in RAM. To guarantee that code doesn't use RAM (and in particular the stack) __asm_flush_l3_cache() must be manually implemented in assembly, rather than implemented in C since the compiler won't know not to touch RAM. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: ensure nvtboot_boot_x0 alignmentStephen Warren2016-11-07-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | nvtboot_boot_x0 is a 64-bit variable and hence must be 64-bit aligned. So far this has happened by accident! Fix the code so this is guaranteed. This fixes the following build error: ... relocation truncated to fit: R_AARCH64_LDST64_ABS_LO12_NC against symbol `nvtboot_boot_x0' ... Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: enable Ethernet on p2771-0000Stephen Warren2016-11-07-0/+5
| | | | | | | | | | | | | | | | | | Enable the Ethernet device in DT, provide board-specific configuration, and enable the driver in Kconfig. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | ARM: tegra: add DWC EQoS (ethernet) to Tegra186 DTStephen Warren2016-11-07-0/+20
| | | | | | | | | | | | | | | | | | Tegra186 includes a Synopsys DWC EQoS (Ethernet) device. Add this to the Tegra186 SoC DT so that boards can make use of it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | ARM: tegra: configure Ethernet address on Tegra186Stephen Warren2016-11-07-0/+55
| | | | | | | | | | | | | | | | | | | | | | On Tegra186, the bootloader which runs before U-Boot passes the Ethernet MAC address to U-Boot using device tree. Extract this value and write it to the environment, so that the Ethernet uclass picks it up and uses it for the built-in Ethernet device. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | ARM: tegra: add SoC-level hook for board_late_init()Stephen Warren2016-11-07-1/+6
|/ | | | | | | | | | | | | Extend the Tegra186 implementation of board_late_init() to call a per-SoC "hook" function. This will allow SoC-specific (rather than Tegra-wide) functionality to be implemented without the core Tegra code needing to be aware of the details. While board186.c is currently only used for Tegra186, it should be applicable to any other future SoC, and perhaps its simple design could be back-ported to older SoCs in the future too. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* armv8: define get_ticks() for the ARMv8 Generic TimerAndre Przywara2016-11-05-0/+11
| | | | | | | | | | | | | | | | | | | For 64-bit ARM systems we provide just a timer_read_counter() implementation and rely on the generic non-uclass get_ticks() function in lib/time.c to call the former. However this function is actually not 64-bit safe, as it assumes a "long" to be 32-bit. Beside the fact that the resulting uint64_t isn't bigger than "long" on 64-bit architectures and thus combining two counters makes no sense, we get all kind of weird results when we try to OR in the high value shifted by _32_ bits. So let's avoid that function at all and provide a straight forward get_ticks() implementation for ARMv8, which also is in line with ARMv7. This fixes occasional immediate time-out expiration issues I see on the Pine64 board. The root cause of this needs to be investigated, but this fix looks like the right thing anyway. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2016-11-02-64/+364
|\
| * rk3288: kconfig: remove duplicate definition of SPL_MMC_SUPPORTKever Yang2016-10-30-3/+0
| | | | | | | | | | | | | | | | | | SPL_MMC_SUPPORT defined in rockchip top level Kconfig instead of inside rk3288 and default to disable if ROCKCHIP_SPL_BACK_TO_BROM defined. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * dts: rk3288: remove node in dmc which not need anymoreKever Yang2016-10-30-18/+0
| | | | | | | | | | | | | | | | | | | | Since we implement the dram capacity auto detect, we don't need to set the channel number and sdram-channel in dts. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Tested-by: Vagrant Cascadian <vagrant@debian.org>
| * rk3288: sdram: auto-detect the capacityKever Yang2016-10-30-42/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for rk3288 dram capacity auto detect, support DDR3 and LPDDR3, DDR2 is not supported. The program will automatically detect: - channel number - rank number - column address number - row address number The dts file do not need to describe those info after apply this patch. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Simon Glass <sjg@chromium.org> Tested-by: Vagrant Cascadian <vagrant@debian.org> Tested-by: Vagrant Cascadian <vagrant@debian.org>
| * rk3288: fix reg address for GRF_SOC_CON2Kever Yang2016-10-30-1/+1
| | | | | | | | | | | | The GRF base address is missing, fix it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * rk3399: disable the clock multiplier support when SoC initKever Yang2016-10-30-0/+14
| | | | | | | | | | | | | | | | | | | | | | The Clock Multiplier in rk3399 EMMC programmable clock generator is broken, we can remove its support from SoC GRF register. Without this patch, rk3399 emmc driver is not work after below patch applied: 6dffdbc mmc: sdhci: Add the programmable clock mode support Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3288: Move rockchip_get_cru() out of the driverSimon Glass2016-10-30-0/+23
| | | | | | | | | | | | | | | | This function is called from outside the driver. It should be placed into common SoC code. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3399: Move rockchip_get_cru() out of the driverSimon Glass2016-10-30-0/+40
| | | | | | | | | | | | | | | | | | | | | | This function is called from outside the driver. It should be placed into common SoC code. Move it. Also rename the driver symbol to be more consistent with the other rockchip clock drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * rockchip: rk3036: Move rockchip_get_cru() out of the driverSimon Glass2016-10-30-0/+41
| | | | | | | | | | | | | | | | | | | | | | This function is called from outside the driver. It should be placed into common SoC code. Move it. Also rename the driver symbol to be more consistent with the other rockchip clock drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | Fix spelling of "resetting".Vagrant Cascadian2016-10-31-5/+8
|/ | | | | | | | Cover-Letter: Fixes several spelling errors for the words "resetting", "extended", "occur", and "multiple". Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'sun9i-a80-spl' of http://git.denx.de/u-boot-sunxiTom Rini2016-10-30-20/+1666
|\
| * sunxi: Add support for SID e-fuses on sun9iChen-Yu Tsai2016-10-30-0/+2
| | | | | | | | | | | | | | | | | | The A80 has SID e-fuses. Like other newer SoCs, the actual e-fuses are at an offset of 0x200 within the SID address space. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: add initial clock setup for sun9i for SPLPhilipp Tomsich2016-10-30-5/+223
| | | | | | | | | | | | | | | | | | | | This is a cleaned up version set_pll() from Allwinner's boot0 source (bootloader/basic_loader/bsp/bsp_for_a80/common/common.c). [wens@csie.org: Added commit message; style cleanup] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Enable SMP mode for the boot CPU on sun9i (A80)Philipp Tomsich2016-10-30-1/+2
| | | | | | | | | | | | | | | | | | | | Since the A80 has many cores which we intend to use in SMP fashion, we should set the SMP bit for the boot CPU. [wens@csie.org: Added commit message] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: add gtbus-initialisation for sun9iPhilipp Tomsich2016-10-30-1/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On sun9i, the GTBUS manages transaction priority and bandwidth for multiple read ports when accessing DRAM. The initialisation mirrors the settings from Allwinner's boot0 for now, even though this may not be optimal for all applications (e.g. headless systems might want to give priority to IO modules). Adding a common callout to gtbus_init() from the SPL clock init with a weakly defined implementation in sunxi/clock.c to fallback to for platforms that don't require this. [wens@csie.org: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: DRAM initialisation for sun9iPhilipp Tomsich2016-10-30-13/+1269
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds DRAM initialisation code for sun9i, which calculates the appropriate timings based on timing information for the supplied DDR3 bin and the clock speeds used. With this DRAM setup, we have verified DDR3 clocks of up to 792MHz (i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration. [wens@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup] Signed-off-by: Chen-Yu Tsai <wens@csie.org> [hdegoede@redhat.com: Drop some huge non-documenting #if 0 ... #endif blocks] [hdegoede@redhat.com: Fix checkpatch warnings] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-10-30-4/+47
|\ \ | |/
| * sunxi: A64: enable USB supportAmit Singh Tomar2016-10-30-3/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mostly by adding MACH_SUN50I to some existing #ifdefs enable support for the the HCI0 USB host controller on the A64. Fix up some minor 64-bit hiccups on the way. Add the bare minimum DT bits to the A64 .dtsi and enable the controllers and the PHY on the Pine64. This is limited to the first USB controller at the moment, which is connected to the lower USB socket on the Pine64 board. [Andre: remove unneeded defines, enable OHCI, add commit message] Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: dts: Pine64: add Ethernet aliasAndre Przywara2016-10-30-0/+1
| | | | | | | | | | | | | | | | | | | | | | The sun8i-emac driver works fine with the A64 Ethernet IP, but we are missing an alias entry to trigger the driver instantiation by U-Boot. Add the line to point U-Boot to the Ethernet DT node. This enables TFTP boot on the Pine64. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Rename CONFIG_SUNXI to CONFIG_ARCH_SUNXIJagan Teki2016-10-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SUNXI -> CONFIG_ARCH_SUNXI and removed CONFIG_SUNIX from config_whitelist.txt Cc: Simon Glass <sjg@chromium.org> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-10-29-2/+15
|\ \
| * | ddr: altera: Configuring SDRAM extra cycles timing parametersChin Liang See2016-10-27-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* | | ARM: uniphier: update DRAM init code for LD11 SoCMasahiro Yamada2016-10-29-23/+391
| | | | | | | | | | | | | | | | | | Introduce run-time DDR PHY training. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: support DDR PHY parameter dump command for LD11Masahiro Yamada2016-10-29-6/+19
| | | | | | | | | | | | | | | | | | | | | | | | Add the LD11 SoC data and adjuts the printf() format because this is a 64-bit SoC. Otherwise, 16-digits pointer addresses would break the log format. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: refactor DDR PHY parameter dump commandMasahiro Yamada2016-10-29-44/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not hard-code the number of DX blocks because it is a different value for LD11 SoC. Move the macro NR_DATX8_PER_DDRPHY to ddrphy-training.c since it is the last user. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: rework existing DDR PHY code to reuse for LD11 SoCMasahiro Yamada2016-10-29-294/+302
| | | | | | | | | | | | | | | | | | | | | | | | | | | The DDR PHY register view of LD11 is slightly different from that of LD4/Pro4/sLD8, but it will be possible to share the register macros (and I want to re-use as much code as possible). Change the code in the more flexible form. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: do not run harmful code for USB boot mode of LD11 ES3Masahiro Yamada2016-10-29-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | The USB boot without the stand-by MPU is available on ES3 or later of LD11 SoC, but the code in this if-conditional block must not be run when booting from USB. Check if the boot device is USB, and skip the code in the case. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: enable clocks to MIO/STDMAC on LD11 if USB is enabledMasahiro Yamada2016-10-29-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | At the moment, the clk driver is not clever enough to automatically enable parent clocks like Linux. Enable the STDMAC clock explicitly if USB is enabled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: fix DRAM init poll address for LD4, Pro4, sLD8Masahiro Yamada2016-10-29-3/+3
| | | | | | | | | | | | | | | | | | The status register should be polled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: rename ddrphy-ld20-regs.h to ddruqphy-regs.hMasahiro Yamada2016-10-29-4/+4
| | | | | | | | | | | | | | | | | | | | | This PHY might be used for other SoCs in the future. Avoid including the SoC name in the header name. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: update DRAM init code for LD20 SoC (3rd)Masahiro Yamada2016-10-29-36/+83
| | | | | | | | | | | | | | | | | | | | | | | | - Constify UMC setting data arrays - Merge data arrays *_d0 and *_d1. - Add PHY parameters for LD20 C1 board Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: remove unused board attribute macrosMasahiro Yamada2016-10-29-3/+0
| | | | | | | | | | | | | | | | | | After SoC evaluation, they turned out unnecessary. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: enable SSC for more PLLs for LD20 SoCMasahiro Yamada2016-10-29-13/+11
| | | | | | | | | | | | | | | | | | | | | | | | For Electro-Magnetic Compatibility. Set CPLL, SPLL2, MPLL, VPPLL, GPPLL, DPLL* to SSC rate 1 percent. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: remove unneeded mdelay() in PLL setting functionMasahiro Yamada2016-10-29-2/+0
| | | | | | | | | | | | | | | | | | This delay is already cared by the callers of this function. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: uniphier: adjust fdt_file environment handling to latest LinuxMasahiro Yamada2016-10-29-12/+9
| |/ |/| | | | | | | | | | | The environment fdt_file is useful to remember the appropriate DTB file name. Adjust it to the recent renaming in the upstream kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-10-28-70/+109
|\ \
| * | ARM: at91/dt: sama5d2: Fix the warning from dtcWenyou Yang2016-10-28-70/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the warning from dtc like, ---8<---- Warning (unit_address_vs_reg): Node /ahb/apb/pmc@f0014000/periph64ck/sdmmc0_hclk has a reg or ranges property, but no unit name --->8---- Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com>
| * | arm, at91: add icache supportHeiko Schocher2016-10-28-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add at least icache support for at91 based boards. This speeds up NOR flash access on an at91sam9g15 based board from 15.2 seconds reading 8 MiB from a SPI NOR flash to 5.7 seconds. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | ARM: at91: clock: correct PRES offset for at91sam9x5Heiko Schocher2016-10-28-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | on at91sam9x5 PRES offset is 4 in the PMC master clock register. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Andreas Bießmann <andreas@biessmann.org>
generated by cgit v1.1 at 2024-11-06 03:26:47 +0000