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* | x86: Use unsigned long for address in table generationSimon Glass2017-02-06-21/+14
| | | | | | | | | | | | | | | | We should use unsigned long rather than u32 for addresses. Update this so that the table-generation code builds correctly on 64-bit machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Synchronize list of x86 subarchitectures (update bootparam.h)Andy Shevchenko2017-02-06-1/+2
|/ | | | | | | | Basically rename X86_SUBARCH_MRST to X86_SUBARCH_INTEL_MID to be more specific. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-02-03-72/+106
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: configs/ls1046aqds_defconfig configs/ls1046aqds_nand_defconfig configs/ls1046aqds_qspi_defconfig configs/ls1046aqds_sdcard_ifc_defconfig configs/ls1046aqds_sdcard_qspi_defconfig configs/ls1046ardb_emmc_defconfig configs/ls1046ardb_qspi_defconfig configs/ls1046ardb_sdcard_defconfig
| * arch: powerpc: update the eLBC IP input clockPrabhakar Kushwaha2017-02-03-40/+21
| | | | | | | | | | | | | | | | | | | | | | | | eLBC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock ratio register (LCRR) used in current implementation governs eLBC IP output cloc. Update sys_info->freq_localbus to represent eLBC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arch: powerpc: Move CONFIG_FSL_ELBC to KconfigPrabhakar Kushwaha2017-02-03-0/+20
| | | | | | | | | | | | | | Enable ELBC from Kconfig. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arch: arm: update the IFC IP input clockPrabhakar Kushwaha2017-02-03-24/+5
| | | | | | | | | | | | | | | | | | | | | | | | IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arch: powerpc: update the IFC IP input clockPrabhakar Kushwaha2017-02-03-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arch: powerpc: Move CONFIG_FSL_IFC to KconfigPrabhakar Kushwaha2017-02-03-0/+17
| | | | | | | | | | | | | | Enable IFC from Kconfig. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * board: freescale: ls1012a: Enable secure DDR on LS1012A platformsPrabhakar Kushwaha2017-02-03-0/+3
| | | | | | | | | | | | | | | | | | | | | | PPA binary needs to be relocated on secure DDR, hence marking out a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag is set Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046a: Enable workaround for erratum A-008336York Sun2017-01-31-0/+1
| | | | | | | | | | | | | | Erratum A-008336 applies to LS1046A per latest SoC document. Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
| * armv8: ls1046a: added usb nodes in dtsTang Yuantian2017-01-27-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | The LS1046A processor has three integrated USB 3.0 controllers (USB1, USB2, and USB3) that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. USB1 and USB2 ports are powered by a NX5P2190UK device, which supplies 5v power at up to 1.2 A. The power enable and power-fault-detect pins are connected to the LS1046A processor via CPLD for individual port management. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge git://git.denx.de/u-boot-mpc85xxTom Rini2017-02-01-17/+38
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| * | powerpc: mpc5200: Correct return value of memcpy functionMark Marshall2017-02-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The memcpy() function returns a pointer to trg. Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at> Reviewed-by: Thomas Graziadei <thomas.graziadei@omicronenergy.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: York Sun <york.sun@nxp.com>
| * | powerpc: mpc85xx: Use symbolic names for cache control bitsMark Marshall2017-01-31-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | We should use the symbolic names for the cache control bits. Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at> Reviewed-by: Thomas Graziadei <thomas.graziadei@omicronenergy.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | powerpc: mpc83xx: Enable pre-relocation mallocmario.six@gdsys.cc2017-01-31-7/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | To enable DM on MPC83xx, we need pre-relocation malloc, which is implemented in this patch. Signed-off-by: Mario Six <mario.six@gdsys.cc> [York S: Fixed compiling warning for unused variable 'i'] Reviewed-by: York Sun <york.sun@nxp.com>
| * | powerpc: mpc83xx: Minimize r1 modificationmario.six@gdsys.cc2017-01-31-5/+8
| |/ | | | | | | | | | | | | | | | | | | | | | | | | The r1 register is modified several times during the cache-ram setup of the MPC83xx SoCs. Since this SP modification confuses debuggers, we use a general purpose register to compute the new stack pointer value, and only set the SP once after all computations are done. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Joakim Tjernlund <Joakim.Tjernlund@infinera.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2017-02-01-30/+3075
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| * | BOARD: MCCMON6: Provide support for iMX6q based mccmon6 boardLukasz Majewski2017-01-30-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | This patch provides u-boot support for Liebherr (LWN) mccmon6 board. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | arm: dts: imx53-cx9020: fix packetloss on fec_mxcPatrick Bruenn2017-01-30-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinmuxing for i.MX53 FEC ethernet copied from <kernel>/arch/arm/boot/dts/imx53-qsb-common.dtsi (at least until v4.9) was bad. It is different from the manual pinmuxing in <u-boot>/board/freescale/mx53loco/mx53loco.c which was used in cx9020 implementation previously before mainlining into u-boot. It seems the bug in imx53-qsb kernel device tree is hidden for so long, because it was never used, by the kernel driver. Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
| * | imx: dts: mx6sxsabreauto: enable i2c2/3Peng Fan2017-01-27-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | Enable i2c2/3, add pinctrl settings. Add max7310 for i2c3. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6sx: add dts for mx6sxsabreauto boardPeng Fan2017-01-27-0/+3003
| | | | | | | | | | | | | | | | | | | | | | | | Add dts for mx6sxsabreauto board. dts related files imported fro Linux (commit e5517c2a5a4). Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | ARM: imx6ul: Move liteSOM source to SoC directoryMarcin Niestroj2017-01-27-18/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moving arch/arm/mach-litesom/ to arch/arm/cpu/armv7/mx6/ was requested in [1] during discussion of chiliSOM support patches. [1] http://lists.denx.de/pipermail/u-boot/2017-January/279137.html Suggested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | imx_common: check for bmode Serial DownloaderStefan Agner2017-01-27-2/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before commit 81c4eccb55cc ("imx: mx6: fix USB bmode to use reserved value") a non-reserved value has been used to trigger Serial Downloader using bmode, which translated to a GPR9 value of 0x10. However, on some boards the non-reserved value lead to unreliable bmode command. With the above mentioned commit, U-boot switched to use [7:4] b0001, which translates to GPR9 0x10 for Serial Downloader mode. Check for the new value and classify it as Serial Downloader mode. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> CC: Stefano Babic <sbabic@denx.de> CC: Tim Harvey <tharvey@gateworks.com> CC: Fabio Estevam <Fabio.Estevam@freescale.com> CC: Eric Nelson <eric.nelson@boundarydevices.com>
* | Merge git://www.denx.de/git/u-boot-marvellTom Rini2017-02-01-2/+382
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| * | arm: mvebu: Implement secure bootMario Six2017-02-01-0/+371
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch implements secure booting for the mvebu architecture. This includes: - The addition of secure headers and all needed signatures and keys in mkimage - Commands capable of writing the board's efuses to both write the needed cryptographic data and enable the secure booting mechanism - The creation of convenience text files containing the necessary commands to write the efuses The KAK and CSK keys are expected to reside in the files kwb_kak.key and kwb_csk.key (OpenSSL 2048 bit private keys) in the top-level directory. Signed-off-by: Reinhard Pfau <reinhard.pfau@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: spl.c: Remove useless gd declarationReinhard Pfau2017-02-01-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ddaa905 ("arm: mvebu: Add DM (driver model) support") removed the assignment of the gd pointer, but kept the (now superfluous) declaration of the gd pointer. Remove this declaration. Signed-off-by: Reinhard Pfau <pfau@gdsys.de> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | mvebu: Add board_pex_config()Mario Six2017-02-01-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Allow boards to do some initialization when PCIe comes up. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | pci: mvebu: Fix Armada 38x supportDirk Eibach2017-02-01-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Armada 38x has four PCI ports, not three. The optimization in pci_init_board() seems to assume that every port has three lanes. This is obviously wrong, and breaks support for Armada 38x. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | | mmc: zynq: rename CONFIG_ZYNQ_SDHCI to CONFIG_MMC_SDHCI_ZYNQMasahiro Yamada2017-01-31-1/+1
|/ / | | | | | | | | | | | | | | | | Make the naming scheme consistent; all SDHCI-base drivers prefixed with CONFIG_MMC_SDHCI_. While we are here, add "depends on ARCH_ZYNQ || ARCH_ZYNQMP". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: compile board data only for SPLMasahiro Yamada2017-01-29-1/+1
| | | | | | | | | | | | | | Now U-Boot proper need not get the uniphier_boards array. Compile it only for SPL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: refactor cmd_ddrmphyMasahiro Yamada2017-01-29-83/+112
| | | | | | | | | | | | Make it look like cmd_ddrphy. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: clean up UMC init for PXs2 SoCMasahiro Yamada2017-01-29-283/+284
| | | | | | | | | | | | | | | | | | Just cosmetic changes: - Rename prefix DMPHY_ to MPHY_ for consistency - Move UMC parameters below for complete decouple of PHY and UMC - Remove redundant whitespaces Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: refactor cmd_ddrphyMasahiro Yamada2017-01-29-73/+83
| | | | | | | | | | | | | | It seems more readable to use arrays to get SoC specific parameters instead of the crappy switch statement. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: use gd->bd->bi_dram for memory reserve on LD20 SoCMasahiro Yamada2017-01-29-10/+3
| | | | | | | | | | | | | | | | | | | | For LD20 SoC, the last 64 byte of each DRAM bank is used for the dynamic training of DRAM PHY. The regions must be reserved in DT to prevent the kernel from using them. Now gd->bd->bi_dram reflects the actual memory banks. Just use it instead of getting access to the board parameters. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: detect RAM size by decoding HW register instead of DTMasahiro Yamada2017-01-29-49/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot needs to set up available memory area(s) in dram_init() and dram_init_banksize(). It is platform-dependent how to detect the memory banks. Currently, UniPhier adopts the memory banks _alleged_ by DT. This is based on the assumption that users bind a correct DT in their build process. Come to think of it, the DRAM controller has already been set up before U-Boot is entered (because U-Boot runs on DRAM). So, the DRAM controller setup register seems a more reliable source of any information about DRAM stuff. The DRAM banks are initialized by preliminary firmware (SPL, ARM Trusted Firmware BL2, or whatever), so this means the source of the reliability is shifted from Device Tree to such early-stage firmware. However, if the DRAM controller is wrongly configured, the system will crash. If your system is running, the DRAM setup register is very likely to provide the correct DRAM mapping. Decode the SG_MEMCONF register to get the available DRAM banks. The dram_init() and dram_init_banksize() need similar decoding. It would be nice if dram_init_banksize() could reuse the outcome of dram_init(), but global variables are unavailable at this stage because the .bss section is available only after the relocation. As a result, SG_MEMCONF must be checked twice, but a new helper uniphier_memconf_decode() will help to avoid code duplication. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: shrink arrays of DDR-PHY parameters for LD20 SoCMasahiro Yamada2017-01-29-175/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | The two arrays ddrphy_{op,ip}_dq_shift_val, occupy more than 3.8 KB memory footprint, which is significant in SPL. There are PHY parameters for 5 boards, but they are actually not board specific, but SoC specific. After all, we just need to have 2 patterns, for LD20 and LD21. Also, the shift values are small enough to become "short" type instead of "int". This change will save about 3 KB memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: SPI: stm32: add stm32f746 qspi driverMichael Kurz2017-01-28-2/+8
| | | | | | | | | | | | This patch adds support for the QSPI IP found in stm32f7 devices. Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
* | net: stm32: add designware mac glue code for stm32Michael Kurz2017-01-28-0/+44
| | | | | | | | | | | | | | | | This patch adds glue code required for enabling the designware mac on stm32f7 devices. Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | ARM: stm32: use clock setup function defined in clock.cMichael Kurz2017-01-28-28/+14
| | | | | | | | | | | | | | | | | | | | | | Use the clock setup function defined in clock.c instead of setting the clock bits directly in the drivers. Remove register definitions of RCC in rcc.h as these are already defined in the struct in stm32.h Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
* | ARM: stm32: fix stm32f7 sdram fmc base addressMichael Kurz2017-01-28-3/+2
| | | | | | | | | | | | | | | | | | The fmc base address is defined twice, once in fmc.h and once in stm32.h. Fix wrong definition in stm32.h. Remove the definiton in fmc.h. Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Vikas Manocha <vikas.manocha@st.com>
* | ARM: stm32: cleanup stm32f7 filesMichael Kurz2017-01-28-118/+110
| | | | | | | | | | | | | | | | | | | | | | | | Cleanup stm32f7 files: - use BIT macro - use GENMASK macro - use rcc struct instead of macro additions Add missing stm32f7 register in rcc struct Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Vikas MANOCHA<vikas.manocha@st.com>
* | ARM: DTS: stm32: add stm32f746-disco device tree filesMichael Kurz2017-01-28-0/+202
| | | | | | | | | | | | | | | | | | | | | | This patch adds the DTS source files needed for stm32f746-disco board The files are based on the stm32f429/469 files from current linux kernel. Source for "arch/arm/dts/armv7-m.dtsi": Linux: "arch/arm/boot/dts/armv7-m.dtsi" Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
* | arm: omap3: Update cpuinfo for DM3730, DM3725, AM3715, and AM3703Adam Ford2017-01-28-2/+48
| | | | | | | | | | | | | | | | | | | | | | | | The check for OMAP3630/3730 only checks for 800MHz 3630/3730, but anything else is lumped into 36XX/37XX with an assumed 1GHz speed. Based on the DM3730 TRM bit 9 shows the MPU Frequency (800MHz/1GHZ). This also adds the ability to distinguish between the DM3730, DM3725, AM3715, and AM3703 and correctly display their maximum speed. Signed-off-by: Adam Ford <aford173@gmail.com> Tested-by: Ladislav Michl <ladis@linux-mips.org>
* | arm: omap3: Fix cpuinfo frequency spellingLadislav Michl2017-01-28-3/+3
| | | | | | | | | | | | Frequency is measured in Hz. Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* | arm64: spin-table: add more information in Kconfig helpMasahiro Yamada2017-01-28-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This feature seems to be sometimes misunderstood. The intention is: [1] Bring the slaves into the U-Boot proper image, not SPL (unless you have a special reason to do otherwise). [2] The operation must be done in a board (SoC) specific manner since how to wake the slaves from the Boot ROM is SoC specific. [3] The slaves must enter U-Boot proper after U-Boot relocates itself because the "cpu-release-addr" property points to the relocated memory area. [2] is already explained in the help. We can make [1] even clearer by mentioning "U-Boot proper" instead of "U-Boot". [3] is missing, so I am adding it to the list. Instead, "before the master CPU jumps to the kernel" is a matter of course, so removed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | board/chiliboard: Add support for chiliBoardMarcin Niestroj2017-01-28-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | chiliBoard is a development board which uses chiliSOM as its base. Hardware specification: * chiliSOM (TI AM335x, DRAM, NAND) * Ethernet PHY (id 0) * USB host (usb1) * MicroSD slot (mmc0) Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: am335x: Add support for chiliSOMMarcin Niestroj2017-01-28-0/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chiliSOM is a System On Module (http://http://grinn-global.com/chilisom/). It can't exists on its own, but will be used as part of other boards. Hardware specification: * TI AM335x processor * 128M, 256M or 512M DDR3 memory * up to 256M NAND We place source inside arch/arm/mach-omap2/ directory and make it possible to reuse initialization code (i.e. DDR, NAND init) for all boards that use it. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | aspeed: Support for ast2500 Eval Boardmaxims@google.com2017-01-28-0/+27
| | | | | | | | | | ast2500 Eval Board device tree and board specific configuration. Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: Board init functions and common configs for ast2500 based boardsmaxims@google.com2017-01-28-1/+84
| | | | | | | | | | | | | | | | Add configuration file with parameters that are very likely to be shared by all ast2500-based boards. Add ast2500-board.c file with the init code that is very likely to be shared by all ast2500-based boards. Reviewed-by: Simon Glass <sjg@chromium.org>
* | aspeed: Add basic ast2500-specific drivers and configurationmaxims@google.com2017-01-28-0/+970
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-15 14:37:57 +0000