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| * powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536Kumar Gala2011-09-29-3/+4
| | | | | | | | | | | | | | | | The MPC8536 seems to use only 3 bits for the major revision field in the SVR rather than the 4 bits used by all other processors. The most significant bit is used as a mfg code on MPC8536. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add networking support to P1023RDSRoy Zang2011-09-29-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The P1023 has two 1G ethernet controllers the first can run in SGMII, RGMII, or RMII. The second can only do SGMII & RGMII. We need to setup a for SoC & board registers based on our various configuration for ethernet to function properly on the board. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add support for FMan ethernet in Independent modeKumar Gala2011-09-29-12/+741
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/mp: add support for discontiguous coresTimur Tabi2011-09-29-26/+61
| | | | | | | | | | | | | | | | | | | | Some SOCs have discontiguously-numbered cores, and so we can't determine the valid core numbers via the FRR register any more. We define CPU_TYPE_ENTRY_MASK to specify a discontiguous core mask, and helper functions to process the mask and enumerate over the set of valid cores. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fdt: Rename fdt_create_phandle to fdt_set_phandleKumar Gala2011-09-29-1/+1
| | | | | | | | | | | | | | | | The old fdt_create_phandle didn't actually create a phandle it just set one. We'll introduce a new helper that actually does creation. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
| * powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't setKumar Gala2011-09-29-1/+8
| | | | | | | | | | | | | | | | Add ifdef protection around fman specific code related to device tree clock setup. If we dont have CONFIG_SYS_DPAA_FMAN defined we shouldn't be executing this code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)Poonam Aggrwal2011-09-29-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue: Address masking doesn't work properly. When sum of the base address, defined by BA, and memory bank size, defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask CSPRn[BA] bits. Impact: This will impact booting when we are reprogramming CSPR0(BA) and AMASK0(AMASK) while executing from NOR Flash. Workaround: Re-programming of CSPR(BA) and AMASK is done while not executing from NOR Flash. The code which programs the BA and AMASK is executed from L2-SRAM. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)Poonam Aggrwal2011-09-29-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue: Peripheral connected to IFC_CS3 may hamper booting from IFC. Impact: Boot from IFC may not be successful if IFC_CS3 is used. Workaround: If IFC_CS3 is used, gate IFC_CS3 while booting from NAND or NOR. Also Software should select IFC_CS3 using PMUXCR[26:27] = 0x01. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)Poonam Aggrwal2011-09-29-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue: The NOR-FCM does not support access to unaligned addresses for 16 bit port size Impact: When 16 bit port size is used, accesses not aligned to 16 bit address boundary will result in incorrect data Workaround: The workaround is to switch to GPCM mode for NOR Flash access. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1MPoonam Aggrwal2011-09-29-3/+4
| | | | | | | | | | | | | | | | | | | | | | For an IFC Erratum (A-003399) we will need to access IFC registers in cpu_init_early_f() so expand the TLB covering CCSR to 1M. Since we need a TLB to cover 1M we move to using TLB1 array for all the early mappings so we can cover various sizes beyond 4k. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * nand: Freescale Integrated Flash Controller NAND supportDipen Dudhat2011-09-29-7/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add NAND support (including spl) on IFC, such as is found on the p1010. Note that using hardware ECC on IFC with small-page NAND (which is what comes on the p1010rdb reference board) means there will be insufficient OOB space for JFFS2, since IFC does not support 1-bit ECC. UBI should work, as it does not use OOB for anything but ECC. When hardware ECC is not enabled in CSOR, software ECC is now used. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> [scottwood@freescale.com: ECC rework and misc fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
| * powerpc/85xx: relocate CCSR before creating the initial RAM areaTimur Tabi2011-09-29-58/+234
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before main memory (DDR) is initialized, the on-chip L1 cache is used as a memory area for the stack and the global data (gd_t) structure. This is called the initial RAM area, or initram. The L1 cache is locked and the TLBs point to a non-existent address (so that there's no chance it will overlap main memory or any device). The L1 cache is also configured not to write out to memory or the L2 cache, so everything stays in the L1 cache. One of the things we might do while running out of initram is relocate CCSR. On reset, CCSR is typically located at some high 32-bit address, like 0xfe000000, and this may not be the best place for CCSR. For example, on 36-bit systems, CCSR is relocated to 0xffe000000, near the top of 36-bit memory space. On some future Freescale SOCs, the L1 cache will be forced to write to the backing store, so we can no longer have the TLBs point to non-existent address. Instead, we will point the TLBs to an unused area in CCSR. In order for this technique to work, CCSR needs to be relocated before the initram memory is enabled. Unlike the original CCSR relocation code in cpu_init_early_f(), the TLBs we create now for relocating CCSR are deleted after the relocation is finished. cpu_init_early_f() will still need to create a TLB for CCSR (at the new location) for normal U-Boot purposes. This is done to keep the impact to existing U-Boot code minimal and to better isolate the CCSR relocation code. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macrosTimur Tabi2011-09-29-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, which contain the high and low portions of CONFIG_SYS_CCSRBAR_PHYS. This is necessary for the assembly-language code that relocates CCSR, since the assembler does not understand 64-bit constants. CONFIG_SYS_CCSRBAR_PHYS is automatically defined from the CONFIG_SYS_CCSRBAR_PHYS_HIGH and CONFIG_SYS_CCSRBAR_PHYS_LOW macros, so it should not be defined in a board header file. Similarly, CONFIG_SYS_CCSRBAR_DEFAULT is defined for each SOC in config_mpc85xx.h, so it should also not be defined in the board header file. CONFIG_SYS_CCSR_DO_NOT_RELOCATE is a "short-cut" macro that guarantees that CONFIG_SYS_CCSRBAR_PHYS is set to the same value as CONFIG_SYS_CCSRBAR_DEFAULT, and so CCSR will not be relocated. Since CONFIG_SYS_CCSRBAR_DEFAULT is locked to a fixed value, multi-stage U-Boot builds (e.g. NAND) are required to relocate CCSR only during the last stage (i.e. the "real" U-Boot). All other stages should define CONFIG_SYS_CCSR_DO_NOT_RELOCATE to ensure that CCSR is not relocated. README is updated with descriptions of all the CONFIG_SYS_CCSRBAR_xxx macros. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0Kumar Gala2011-09-29-0/+5
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014Ramneek Mehresh2011-09-29-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Add UTMI and ULPI PHY support for USB controller on qoriq series of processors with internal UTMI PHY implemented, for example P1010/P1014 - Use both getenv() and hwconfig to get USB phy type till getenv() is depricated - Introduce CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY to specify if soc has internal UTMI phy Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | microblaze: Clean up reset asm codeMichal Simek2011-10-03-20/+5
| | | | | | | | | | | | | | | | - Remove code copying - Reset address is setup from first stage bootloader - Support reset vector setup on little endian Signed-off-by: Michal Simek <monstr@monstr.eu>
* | microblaze: Save and restore first unused vectorMichal Simek2011-10-03-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Use one memory space to detect little/big endian platforms. The first unused address(0x28) is used instead 0x0 address (reset vectors). Detection rewrited reset vector setup from first stage bootloader. Workflow: 1. Store 0x28 to r7 2. Do little/big endian test 3. Restore r7 to 0x28 Signed-off-by: Michal Simek <monstr@monstr.eu>
* | microblaze: Setup MB vectors if feature is enable for u-bootMichal Simek2011-10-03-12/+22
| | | | | | | | | | | | | | For example: Setup reset vectors if reset address is setup. Setup user exception vector if user exception is enabled Signed-off-by: Michal Simek <monstr@monstr.eu>
* | microblaze: Remove debug saving valueMichal Simek2011-10-03-2/+0
| | | | | | | | | | | | Forget to remove debug code. Signed-off-by: Michal Simek <monstr@monstr.eu>
* | sbc82xx: delete support for obsolete SBC8240/SBC8260Paul Gortmaker2011-10-01-1/+1
| | | | | | | | | | | | | | | | | | | | The EST SBC8260 is over 10 years old, and the SBC8240 older than that. With the tiny amount of RAM (by today's standards), there really isn't anyone interested in running the latest U-boot on these EOL products anymore. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> CC: jon.diekema@smiths-aerospace.com
* | console: Squelch pre-console output in console functionsGraeme Russ2011-10-01-32/+16
| | | | | | | | | | | | | | | | | | | | There are some locations in the code which anticipate printf() being called before the console is ready by squelching printf() on gd->have_console. Move this squelching into printf(), vprintf(), puts() and putc(). Also make tstc() and getc() return 0 if console is not yet initialised Signed-off-by: Graeme Russ <graeme.russ@gmail.com> Tested-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'post' of git://git.denx.de/u-boot-blackfinWolfgang Denk2011-10-01-251/+144
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'post' of git://git.denx.de/u-boot-blackfin: Blackfin: uart: implement loop callback for post Blackfin: bf537-stamp/bf548-ezkit: update POST flash block range Blackfin: post: generalize led/button tests with GPIOs Blackfin: bf537-stamp: drop uart/flash post tests Blackfin: post: drop custom test list Blackfin: bf537-stamp: convert to gpio post hotkey
| * | Blackfin: uart: implement loop callback for postMike Frysinger2011-09-29-0/+40
| | | | | | | | | | | | | | | | | | This allows the Blackfin UART driver to be tested via post. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: post: generalize led/button tests with GPIOsMike Frysinger2011-09-29-0/+104
| | | | | | | | | | | | | | | | | | Make it easy for any Blackfin board to enable led/push button tests. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: post: drop custom test listMike Frysinger2011-09-29-251/+0
| |/ | | | | | | | | | | | | The few tests that are Blackfin-specific have been migrated to common code or been rewritten with the existing "bsp-specific" defines. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | zmx25: Fix build warning due to 'get_reset_cause' defined but not usedFabio Estevam2011-09-30-23/+23
| | | | | | | | | | | | | | | | | | | | | | | | When building the zmx25 target we get: Configuring for zmx25 board... generic.c:108: warning: 'get_reset_cause' defined but not used Fix this warning by defining get_reset_cause only if CONFIG_DISPLAY_CPUINFO is defined. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | MX5: Clean up the output of "clocks" commandMarek Vasut2011-09-30-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new output looks like this: > clocks PLL1 800 MHz PLL2 665 MHz PLL3 216 MHz AHB 133000 kHz IPG 66500 kHz IPG PERCLK 665000 kHz Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <jason.hui@linaro.org>
* | MX5: Add AHB clock reporting and fix IPG clock reportingMarek Vasut2011-09-30-9/+27
| | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Liu <jason.hui@linaro.org> Acked-by: Jason Liu <jason.hui@linaro.org>
* | MX5: Modify the PLL decoding algorithmMarek Vasut2011-09-30-10/+70
| | | | | | | | | | | | | | | | | | | | The PLL decoding algorithm didn't take into account many configuration bits. Adjust it according to Linux kernel. Also, add PLL4 for MX53. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Hui <jason.hui@linaro.org> Tested-by: Jason Liu <Jason.hui@linaro.org>
* | FEC: Move imx_get_mac_from_fuse() definition to fec_mxc.hMarek Vasut2011-09-30-6/+0
| | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* | MX31: Disable watchdog during low-power modesFabio Estevam2011-09-30-2/+4
| | | | | | | | | | | | | | | | | | | | | | Turn on the watchdog WDZST bit so that watchdog timer does not count during low power modes. Prior to applying this patch mx31pdk board got watchdog resets because when it booted in the Linux prompt and there was no activity, the system entered into idle mode while watchdog timer was still active. Fix this by disabling watchdog timer during idle mode. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | MX25: tx25: Avoid the usage of extern in C fileFabio Estevam2011-09-30-0/+29
| | | | | | | | | | | | Avoid the usage of extern in C file as pointed out by checkpatch. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | MX31: Improve readability for reset causeFabio Estevam2011-09-30-1/+1
| | | | | | | | | | | | | | | | | | Currently the reset cause is printed like: CPU: Freescale i.MX31 rev 2.0 at 531 MHz.Reset cause: POR Improve readability by adding a new line like it is done on other i.MX boards. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | ARM: mx25: Print the source of resetFabio Estevam2011-09-30-1/+24
| | | | | | | | | | | | Print the source of reset during boot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | ARM: mx25: Print the silicon revisonFabio Estevam2011-09-30-1/+32
| | | | | | | | | | | | Print the silicon revison during boot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | arm, davinci, da8xx: add cpuinfoHeiko Schocher2011-09-30-2/+14
| | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | arm, davinci, am1808: add lowlevel functions for booting from NORHeiko Schocher2011-09-30-0/+473
| | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | arm, davinci: add NOR Boot Configuration WordHeiko Schocher2011-09-30-0/+9
| | | | | | | | | | | | | | | | | | | | to add the "NOR Boot Configuration Word" on AM18xx based boards, define CONFIG_SYS_DV_NOR_BOOT_CFG. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | arm, davinci: add ddr2 definitionHeiko Schocher2011-09-30-0/+96
| | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | arm, davinci, am1808, gpio: add missing defines for bank 8Heiko Schocher2011-09-30-0/+2
| | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | arm, davinci: add some missing defines in hardware.hHeiko Schocher2011-09-30-0/+11
| | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | arm, davinci: add SYSCFG1 base and register structHeiko Schocher2011-09-30-0/+16
| | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | arm, davinci: add RTC base addrHeiko Schocher2011-09-30-0/+1
| | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | arm, davinci: add internal WDT support for AM1808 cpusHeiko Schocher2011-09-30-0/+35
| | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | arm, davinci: add missing timer baseaddresses for !DA8xx cpuHeiko Schocher2011-09-30-0/+2
| | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | arm, davinci: move davinci_timer in header fileHeiko Schocher2011-09-30-14/+41
| | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | net, davinci_emac: add KSZ8864 switchHeiko Schocher2011-09-30-1/+75
| | | | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Paulraj Sandeep <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | omap3: Fix compile warningSanjeev Premi2011-09-30-1/+1
| | | | | | | | | | | | | | | | | | | | Building without option CONFIG_DISPLAY_CPUINFO leads to this warning: sys_info.c:50:14: warning: 'rev_s_37xx' defined but not used Signed-off-by: Sanjeev Premi <premi@ti.com> Cc: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | mmc: omap: config VMMC, MMC1_PBIASBalaji T K2011-09-30-1/+7
| | | | | | | | | | | | | | | | | | | | Config VMMC voltage to 3V for MMC/SD card slot and PBIAS settings needed for OMAP4 Fixes MMC/SD detection on boot from eMMC. Signed-off-by: Balaji T K <balajitk@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | devkit8000: Fix build breakSandeep Paulraj2011-09-30-1/+1
| | | | | | | | | | | | | | Found a build erros when i ran MAKEALL. So fix it. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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