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* tegra: i2c: Add I2C driverYen Lin2012-03-29-0/+157
| | | | | | | | | | | | | Add basic i2c driver for Tegra2 with 8- and 16-bit address support. The driver requires CONFIG_OF_CONTROL to obtain its configuration from the device tree. (Simon Glass: sjg@chromium.org modified for upstream) Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: fdt: i2c: Add extra I2C bindings for U-BootSimon Glass2012-03-29-1/+9
| | | | | | | | Add U-Boot's peripheral clock information to the Tegra20 device tree file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Enhance clock support to handle 16-bit clock divisorsSimon Glass2012-03-29-24/+49
| | | | | | | | I2C ports have a 16-bit clock divisor. Add code to handle this special case so that I2C speeds below 150KHz are supported. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Rename NV_PA_PMC_BASE to TEGRA2_PMC_BASESimon Glass2012-03-29-8/+8
| | | | | | | | | Change this name to fit with the current convention in the Tegra header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* arm: Check for valid FDT after console is upSimon Glass2012-03-29-0/+8
| | | | | | | | When using CONFIG_OF_CONTROL, add a check that we have a valid FDT and panic() if not. This must be done after the console is ready. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: usb: Add support for Tegra USB peripheralSimon Glass2012-03-29-1/+717
| | | | | | | | | | | | | | | | | | This adds basic support for the Tegra2 USB controller. Board files should call board_usb_init() to set things up. Configuration is performed through the FDT, with aliases used to set the order of the ports, like this fragment: aliases { /* This defines the order of our USB ports */ usb0 = "/usb@0xc5008000"; usb1 = "/usb@0xc5000000"; }; drivers/usb/host files ONLY: Acked-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: fdt: Add function to return peripheral/clock IDSimon Glass2012-03-29-0/+71
| | | | | | | | | A common requirement is to find the clock ID for a peripheral. This is the second cell of the 'clocks' property (the first being the phandle itself). Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: usb: fdt: Add additional device tree definitions for USB portsSimon Glass2012-03-29-0/+4
| | | | | | | | | | | | | | This adds clock references to the USB part of the device tree for U-Boot, and marks USB1 as supporting legacy mode (which we disable in the driver). The USB timing information may vary between boards sometimes, but for now we hard-code it in C. This is because all current T2x boards use the same values, we will deal with T3x later and we first need to agree on the format for this timing information in the fdt and may in fact decide that it has no place there. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: fdt: Add clock bindingsSimon Glass2012-03-29-0/+16
| | | | | | | | | | | | | | | | | This adds a basic binding for the oscillator and peripheral clocks. The second cell is the clock number, defined as the bit number within the clock enable register if the peripheral clock. This uses the RFC clock bindings from Grant Likely so may change later: https://lkml.org/lkml/2011/12/12/498 It is taken from Stephen Warren's patch here: http://patchwork.ozlabs.org/patch/141359/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: fdt: Add Tegra2x device tree file from kernelSimon Glass2012-03-29-0/+170
| | | | | | | | | | | | | This was taken from commit b48c54e2 at: git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git config.mk is updated to provide this file to boards through the built-in mechanism: /include/ ARCH_CPU_DTS Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* arm: fdt: Add skeleton device tree file from kernelSimon Glass2012-03-29-0/+13
| | | | | | | | This was taken from commit b48c54e2 at: git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* arm: Tegra2: Fix ELDK42 gcc failure with inline asm stack pointer loadTom Warren2012-03-29-5/+5
| | | | | | | | | | | | | The 4.2.2 gcc in the ELDK42 release doesn't like the direct SP load using a constant in tegra2_start. Change it to use a load thru another reg using mov sp, %0 : : "r"(CONST). Tested on my Seaboard T20-A03, U-Boot loads and runs OK. Also compiled all tegra2 builds with both gcc 4.2.2 and 4.4.1 OK. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* i.MX28: Enable caches by defaultMarek Vasut2012-03-29-0/+10
| | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* ARM926EJS: Implement cache operationsMarek Vasut2012-03-29-12/+54
| | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* nhk8815: fix build errorsAnatolij Gustschin2012-03-28-0/+10
| | | | | | | | | | | | | Fix: common/libcommon.o: In function `cread_line': /home/ag/git/u-boot/common/main.c:695: undefined reference to `get_ticks' /home/ag/git/u-boot/common/main.c:695: undefined reference to `get_tbclk' /home/ag/git/u-boot/common/main.c:698: undefined reference to `get_ticks' Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Alessandro Rubini <rubini@unipv.it> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Alessandro Rubini <rubini@unipv.it>
* ARM: highbank: add reset supportRob Herring2012-03-28-0/+1
| | | | | | | Implement reset for highbank platform. Reset is triggered via a wfi instruction, so enabling armv7 for the compiler is necessary. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* ARM: highbank: Add boot counter supportRob Herring2012-03-28-1/+37
| | | | | | Add boot counter support using an sysreg which is persistent across reset. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* ARM: highbank: fix us_to_tick calculationRob Herring2012-03-28-2/+2
| | | | | | | udelay calls were off due to failing to convert us to ns. Fix this and drop the unnecessary shifts since NS_PER_TICK is only 7ns. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* ARM: highbank: add missing get_tbclkRob Herring2012-03-28-0/+5
| | | | | | | The get_tbclk function was missing and the recent commit "common: add possibility for readline_into_buffer timeout" makes it required. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* EXYNOS: Add structure for Exynos4 DMCChander Kashyap2012-03-27-0/+109
| | | | | | | Add exynos4_dmc structure in dmc.h for exynos4 dram controllor(DMC). Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARM: fix s3c2410 timer codeDavid Müller (ELSOFT AG)2012-03-27-44/+20
| | | | | | | | This patch fixes the s3c24x0 timer code to work with the ARM relocation feature. Signed-off-by: David Mueller <d.mueller@elsoft.ch> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm: Add Prep subcommand support to bootmSimon Schwarz2012-03-27-169/+206
| | | | | | | | | | | | | Adds prep subcommand to bootm implementation of ARM. When bootm is called with the subcommand prep the function stops right after ATAGS creation and before announce_and_cleanup. This is used in command "cmd_spl export" Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Tom Rini <trini@ti.com>
* SPL: call cleanup_before_linux() before booting LinuxStefano Babic2012-03-27-1/+1
| | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Tom Rini <tom.rini@gmail.com> CC: Wolfgang Denk <wd@denx.de> CC: Simon Schwarz <simonschwarzcor@gmail.com>
* OMAP3: SPL: do not call I2C init if no I2C is set.Stefano Babic2012-03-27-0/+2
| | | | | | | | | | Call i2c initialization in spl_board_init only if I2C is configured for the board. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Tom Rini <tom.rini@gmail.com> CC: Wolfgang Denk <wd@denx.de> CC: Simon Schwarz <simonschwarzcor@gmail.com>
* Add cache functions to SPL for armv7Stefano Babic2012-03-27-4/+5
| | | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Tom Rini <tom.rini@gmail.com> CC: Wolfgang Denk <wd@denx.de> CC: Simon Schwarz <simonschwarzcor@gmail.com>
* omap/spl: change output of spl_parse_image_headerSimon Schwarz2012-03-27-1/+1
| | | | | | | | | This only outputs "Assuming u-boot.bin..." if debug is active. Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> CC: Tom Rini <tom.rini@gmail.com> CC: Stefano Babic <sbabic@denx.de> CC: Wolfgang Denk <wd@denx.de>
* omap-common/spl: Add linux boot to SPLSimon Schwarz2012-03-27-23/+75
| | | | | | | | | | | | | | | | | | | | | | | | This adds Linux booting to the SPL This depends on CONFIG_MACH_TYPE patch by Igor Grinberg (http://article.gmane.org/gmane.comp.boot-loaders.u-boot/105809) Related CONFIGs: CONFIG_SPL_OS_BOOT Activates/Deactivates the OS booting feature CONFIG_SPL_OS_BOOT_KEY defines the IO-pin number u-boot switch - if pressed u-boot is booted CONFIG_SYS_NAND_SPL_KERNEL_OFFS Offset in NAND of direct boot kernel image to use in SPL CONFIG_SYS_SPL_ARGS_ADDR Address where the kernel boot arguments are expected - this is normaly RAM-begin + 0x100 Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> CC: Tom Rini <tom.rini@gmail.com> CC: Stefano Babic <sbabic@denx.de> CC: Wolfgang Denk <wd@denx.de>
* devkit8000/spl: init GPMC for dm9000 in SPLSimon Schwarz2012-03-27-0/+1
| | | | | | | | | Linux crashes if the GPMC isn't configured for the dm9000. Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> CC: Tom Rini <tom.rini@gmail.com> CC: Stefano Babic <sbabic@denx.de> CC: Wolfgang Denk <wd@denx.de>
* omap-common: Add NAND SPL linux bootingSimon Schwarz2012-03-27-16/+50
| | | | | | | | | | | | | | | | This implements booting of Linux from NAND in SPL Related config parameters: CONFIG_SYS_NAND_SPL_KERNEL_OFFS Offset in NAND of direct boot kernel image to use in SPL CONFIG_SYS_SPL_ARGS_ADDR Address where the kernel boot arguments are expected - this is normally RAM-start + 0x100 (on ARM) Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com> CC: Tom Rini <tom.rini@gmail.com> CC: Stefano Babic <sbabic@denx.de> CC: Wolfgang Denk <wd@denx.de>
* mx53: Make PLL2 to be the parent of UART clockFabio Estevam2012-03-27-3/+17
| | | | | | | | | | | | | | | | | | Change the parent UART clock to be PLL2, so that U-boot can also boot a Freescale 2.6.35 kernel for mx53. FSL kernel and U-boot changed the UART parent from PLL3 to PLL2 to avoid conflicts with IPU clocks, so that the video resolution can be changed without affecting the UART clock. On a 2.6.35 kernel the serial console is messed up after IPU driver is loaded and this patch fixes this problem. Tested on a mx53loco board booting a FSL kernel and also a mainline kernel. Reported-by: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* mx6: Read silicon revision from registerFabio Estevam2012-03-27-3/+171
| | | | | | | | | | | | | | | Instead of hardcoding the mx6 silicon revision, read it in run-time. Also, besides the silicon version print the mx6 variant type: quad,dual/solo or solo-lite. Tested on a mx6qsabrelite, where it shows: CPU: Freescale i.MX6Q rev1.0 at 792 MHz Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Jason Liu <r64343@freescale.com>
* i.MX28: Drop __naked function from spl_mem_initMarek Vasut2012-03-27-7/+3
| | | | | | | | | | | | | Instead of compiling the function and using the result as a constant, simply use the constant. NOTE: This patch works around bug: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52546 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com>
* i.MX28: Make the stabilization delays shorterMarek Vasut2012-03-27-4/+4
| | | | | | | | | | | | | Cut down the VDDIO/VDDA regulator stabilization delays to 500 uS. That should be enough according to the datasheet and bootlets. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Robert Deliën <robert@delien.nl> Cc: Fabio Estevam <festevam@gmail.com> Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
* mx6: Remove duplicate definition of ANATOP_BASE_ADDRFabio Estevam2012-03-27-1/+0
| | | | | | Remove duplicate definition of ANATOP_BASE_ADDR. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: Fix reset cause for Power On Reset caseFabio Estevam2012-03-27-0/+1
| | | | | | | | | | | | | After booting mx6qsabrelite from POR the following is reported: CPU: Freescale i.MX61 family rev1.0 at 792 MHz Reset cause: unknown reset This is because both the POR and WDOG bits are set after reset. Fix this by also checking both bits in the POR case. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* i.MX28: Enable additional DRAM address bitsMarek Vasut2012-03-27-1/+1
| | | | | | | | Enables all fourteen address lines for DRAM Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marek.vasut@gmail.com> Tested-by: Marek Vasut <marek.vasut@gmail.com>
* mx31: add "ARM11P power gating" to get_reset_causeHelmut Raiger2012-03-27-0/+2
| | | | | | Add missing reset reason 7 to get_reset_cause(). Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
* IXP: Fix GPIO_INT_ACT_LOW_SET()Marek Vasut2012-03-26-2/+8
| | | | | | | | | The GPIO_INT_ACT_LOW_SET was incorrectly handling interrupt lines higher than 7. This is due to the fact that there are two registers for total of 16 lines. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Bryan Hundven <bryanhundven@gmail.com> Cc: Michael Schwingen <rincewind@discworld.dascon.de>
* IXP: Squash warnings in IXP NPEMarek Vasut2012-03-26-7/+1
| | | | | | | | | | | | | IxEthAcc.c: In function ‘ixEthAccInit’: IxEthAcc.c:105:21: warning: comparison between ‘IxEthDBStatus’ and ‘enum <anonymous>’ [-Wenum-compare] IxEthDBAPISupport.c: In function ‘ixEthDBPortAddressSet’: IxEthDBAPISupport.c:633:18: warning: variable ‘ackPortAddressLock’ set but not used [-Wunused-but-set-variable] IxQMgrDispatcher.c: In function ‘ixQMgrLLPShow’: IxQMgrDispatcher.c:1194:18: warning: variable ‘q’ set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bryan Hundven <bryanhundven@gmail.com> Cc: Michael Schwingen <rincewind@discworld.dascon.de>
* IXP: Make IXP buildable with arm-linux- toolchainsMarek Vasut2012-03-26-0/+3
| | | | | | | | | | | Add -EB flag to LD to switch endianness of the linker. This should make armeb targets buildable again. Also, make use of U-Boot's internal libgcc instead of toolchain's one, this works around the use of libraries from GCC, which might be little endian. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Bryan Hundven <bryanhundven@gmail.com> Cc: Michael Schwingen <rincewind@discworld.dascon.de>
* SPL: Add YMODEM over UART load supportMatt Porter2012-03-26-0/+87
| | | | | | | | | | Adds support for loading U-Boot from UART using YMODEM protocol. If YMODEM support is enabled in SPL and the romcode indicates that SPL loaded via UART then SPL will wait for start of a YMODEM transfer via the console port. Signed-off-by: Matt Porter <mporter@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* spl.c: Use __noreturn decoratorTom Rini2012-03-26-3/+2
| | | | | Acked-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Tom Rini <trini@ti.com>
* Fix erroneous 32-bit access to hw_clkctrl_frac0 and hw_clkctrl_frac1 registersRobert Delien2012-03-26-88/+52
| | | | | | | | | This patch fixes erroneous 32-bit access to registers hw_clkctrl_frac0 and hw_clkctrl_frac1. Signed-off-by: Robert Delien <robert@delien.nl> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de>
* Introducing 8-bit wide register, mx28_register_8Robert Delien2012-03-26-0/+16
| | | | | | | | | | This patch introduces an 8-bit register, mx28_register_8, in order to prepare for fixing erroneous 32-bit wide access of registers hw_clkctrl_frac0 and hw_clkctrl_frac1. Signed-off-by: Robert Delien <robert@delien.nl> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de>
* Renamed mx28_register to mx28_register_32 to prepare for mx28_register_8Robert Delien2012-03-26-425/+429
| | | | | | | | | This patch renames mx28_register to mx28_register_32 in order to prepare for the introduction of an 8-bit register, mx28_register_8. Signed-off-by: Robert Delien <robert@delien.nl> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de>
* i.MX28: Reformat the DRAM memory configuration dataMarek Vasut2012-03-26-38/+48
| | | | | | Reformat the data so it's easier to navigate through them. Signed-off-by: Marek Vasut <marex@denx.de>
* usb/ehci: Add USB support for the MX6QWolfgang Grandegger2012-03-26-0/+17
| | | | | | | Currently, only USB Host 1 is supported. Cc: Remy Bohmer <linux@bohmer.net> Signed-off-by: Wolfgang Grandegger <wg@denx.de>
* i.mx28: Replaced magic numbers for scratch register addresses with register ↵Robert Delien2012-03-26-8/+8
| | | | | | | | | definitions This patch replaces the use of magice numbers for scratch register addresses with earlier defined register definitions. Signed-off-by: Robert Delien <robert@delien.nl>
* i.mx28: Added register definitions for DIGCTL registersRobert Delien2012-03-26-0/+156
| | | | | | | This patch adds register definitions for the registers of the DIGCTL IP-block. Signed-off-by: Robert Delien <robert@delien.nl>
* PXA: Fix missing get_tbclk() breaking vpac boardsMarek Vasut2012-03-26-0/+5
| | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
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