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| | * | tegra: remove support for UART SPI switchAllen Martin2013-03-25-48/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This feature was only used for tegra20 seaboard that had a pinmux conflict on the SPI pins. These boards were never manufactured, so remove this support to clean up SPI driver. Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * | | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-26-1/+134
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| | * | Exynos5: TMU: Add hardware trippingAkshay Saraswat2013-03-12-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds hardware tripping at 110 degrees celsius which must enable forced system shutdown in case TMU fails to power off. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | Exynos5: FDT: Add TMU device node valuesAkshay Saraswat2013-03-12-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fdt entry for Exynos TMU driver specific pre-defined values used for calibration of current temperature and defining threshold values. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | Exynos5: TMU: Add driver for Thermal Management UnitAkshay Saraswat2013-03-12-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding Exynos Thermal Management Unit driver to monitor SOC temperature and take actions corresponding to states of TMU. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | EXYNOS: Correct ordering of SPL machine_paramsSimon Glass2013-03-12-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mem_manuf is not in the correct order according to the string table. This causes cros_bundle_firmware to get the BL2 settings in the wrong order. This patch fixes the same. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | EXYNOS5: Add function to enable XXTI clock sourceRajeshwari Shinde2013-03-08-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds funtion to enable XXTI clock source required by MAX98095 codec. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | EXYNOS5: Add function to setup set ps holdRajeshwari Shinde2013-02-20-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a function to set ps_hold data driving value high. This enables the machine to stay powered on even after the initial power-on condition goes away(e.g. power button). Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-24-361/+1342
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| | * | | arm: Correct CONFIG_STANDALONE_LOAD_ADDR for AM33XX/OMAP* platformsTom Rini2013-03-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All of these platforms have memory starting at 0x80000000, so this is the correct CONFIG_STANDALONE_LOAD_ADDR for all of them. Acked-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Tom Rini <trini@ti.com>
| | * | | am335x_evm: Add better timings for the new BeagleBoard DDR3 partTom Rini2013-03-24-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | Tested-by: Rao Bodapati <rao@circuitco.com> Signed-off-by: Tom Rini <trini@ti.com>
| | * | | ti814x_evm: add ti814x evm board supportMatt Porter2013-03-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add TI814X EVM board directory, config file, and MAINTAINERS entry. Enable build. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt to recent omap_hsmmc requirements, Matt re-tested] Signed-off-by: Tom Rini <trini@ti.com>
| | * | | am33xx: support ti814x mmc reference clockMatt Porter2013-03-24-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TI814x has a 192MHz hsmmc reference clock. Select that clock rate when building for TI814x. Signed-off-by: Matt Porter <mporter@ti.com>
| | * | | am33xx: add dmm support to emif4 libraryMatt Porter2013-03-24-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds a config_dmm() routine to support TI814X DMM configuration. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| | * | | am33xx: add ti814x specific register definitionsMatt Porter2013-03-24-21/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support the ti814x specific register definitions within arch-am33xx. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| | * | | am33xx: refactor am33xx mux support and add ti814x supportMatt Porter2013-03-24-227/+566
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM33XX and TI814X have a similar mux though the pinmux register layout and address space differ. Add a separate ti814x mux include to support the TI814X-specific differences. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
| | * | | am33xx: refactor am33xx clocks and add ti814x supportMatt Porter2013-03-24-33/+502
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split clock.c for am335x and ti814x and add ti814x specific clock support. Signed-off-by: Matt Porter <mporter@ti.com>
| | * | | am33xx: refactor emif4/ddr to support multiple EMIF instancesMatt Porter2013-03-24-72/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AM33xx emif4/ddr support closely matches what is need to support TI814x except that TI814x has two EMIF instances. Refactor all the emif4 helper calls and the config_ddr() init function to use an additional instance number argument. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| | * | | am33xx: convert defines from am33xx-specific to generic namesMatt Porter2013-03-24-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Eliminate AM33xx specific names to prepare for TI814x support within AM33xx-land. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| | * | | am33xx: Add required includes to some omap/am33xx codeTom Rini2013-03-24-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - In arch/arm/cpu/armv7/omap-common/timer.c, drivers/mtd/nand/omap_gpmc.c and drivers/net/cpsw.c add #include files that the driver needs but had been relying on <config.h> to bring in. - In arch/arm/cpu/armv7/omap-common/lowlevel_init.S add <config.h> - In am335x_evm.h and pcm051.h don't globally include <asm/arch/hardware.h> and <asm/arch/cpu.h> but just <asm/arch/omap.h> as that is the only include which defines things the config uses. Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Tom Rini <trini@ti.com>
| | * | | ARM: AM33XX: Fix typo that causes an AM duplication in CPU name.Enric Balletbo i Serra2013-03-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just fix a typo displaying the CPU info. With CONFIG_DISPLAY_INFO we see something like AMAM335X-GP rev 0 instead of AM335X-GP rev 0. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com> Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
| | * | | am335x: Enable DDR PHY dynamic power down bit for DDR3 boardsVaibhav Hiremath2013-03-24-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable DDR PHY dynamic power down bit, which enables powering down the IO receiver when not performing read. This also helps in reducing overall power consumption in low power states (suspend/standby). Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com> Cc: Tom Rini <trini@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| | * | | am33xx:ddr:Fix config_sdram to work for all DDRSteve Kipisz2013-03-22-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original write to sdram_config is correct for DDR3 but incorrect for DDR2 so SPL was hanging. For DDR2, the write to sdram_config should be after the writes to ref_ctrl. This was working for DDR3 because there was a write of 0x2800 to ref_ctrl before a write to sdram_config. Tested on: GP EVM 1.1A (DDR2), GP EVM 1.5A (DDR3), Beaglebone A6 (DDR2), Beagleone Blacd A4A (DDR3) Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
| | * | | Initialise correct GPMC WAITx irq for AM33xxMark Jackson2013-03-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently WAIT0 irq is reset and then WAIT1 irq is enabled. Fix it such that WAIT0 irq is enabled instead. Signed-off-by: Mark Jackson <mpfj@newflow.co.uk> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
| | * | | Allow AM335x MPU core clock speed to be specified in the board config fileMark Jackson2013-03-22-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow AM335x MPU core clock speed to be specified in the board config file. To use, add the following to the board's config file:- #define CONFIG_SYS_MPUCLK <desired clock freq in MHz> Signed-off-by: Mark Jackson <mpfj@newflow.co.uk> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
| * | | | ARM: implement erratum 716044 workaroundStephen Warren2013-03-22-0/+6
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | Add common code to enable the workaround for ARM erratum 716044. This will be enabled for Tegra. Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | | ARM: rpi_b: enable SD controller, add related env/cmdsStephen Warren2013-03-20-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the SD controller driver for the Raspberry Pi. Enable a number of useful MMC, partition, and filesystem-related commands. Set up the environment to provide standard locations for loading a kernel, DTB, etc. Provide a boot command that loads and executes boot.scr.uimg from the SD card; this is written considering future extensibilty to USB storage. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
| * | | mmc: add bcm2835 driverStephen Warren2013-03-20-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a simple driver for the BCM2835's SD controller. Workarounds are implemented for: * Register writes can't be too close to each-other in time, or they will be lost. * Register accesses must all be 32-bit, so implement custom accessors. This code was extracted from: git://github.com/gonzoua/u-boot-pi.git master which was created by Oleksandr Tymoshenko. Portions of the code there were obviously based on the Linux kernel at: git://github.com/raspberrypi/linux.git rpi-3.6.y commit f5b930b "Main bcm2708 linux port" signed-off-by Dom Cobley. swarren changed the following for upstream: * Removed hack udelay()s in bcm2835_sdhci_raw_writel(); setting SDHCI_QUIRK_WAIT_SEND_CMD appears to solve the issues. * Remove register logging from read*/write* functions. * Sort out confusion with min/max_freq values passed to add_sdhci(). * Use more descriptive variable names and calculations in IO accessors. * Simplified and commented twoticks_delay calculation. * checkpatch fixes. Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Oleksandr Tymoshenko <gonzo@bluezbox.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Andy Fleming <afleming@gmail.com>
| * | | ARM: bcm2835: add mailbox driverStephen Warren2013-03-20-1/+572
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a "GPU") and the ARM CPU. The ARM CPU is often thought of as the main CPU. However, the VideoCore actually controls the initial SoC boot, and hides much of the hardware behind a protocol. This protocol is transported using the SoC's mailbox hardware module. Here, we add a very simplistic driver for the mailbox module, and define a few structures for the property messages. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | | | x86: Move PCI init before SPI initSimon Glass2013-03-19-4/+4
|/ / / | | | | | | | | | | | | | | | | | | It is possible that our PCI bus will provide the SPI controller, so change the init order to make this work. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-03-18-6330/+8566
|\ \ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Albert's rework of the linker scripts conflicted with Simon's making everyone use __bss_end. We also had a minor conflict over README.scrapyard being added to in mainline and enhanced in u-boot-arm/master with proper formatting. Conflicts: arch/arm/cpu/ixp/u-boot.lds arch/arm/cpu/u-boot.lds arch/arm/lib/Makefile board/actux1/u-boot.lds board/actux2/u-boot.lds board/actux3/u-boot.lds board/dvlhost/u-boot.lds board/freescale/mx31ads/u-boot.lds doc/README.scrapyard include/configs/tegra-common.h Build tested for all of ARM and run-time tested on am335x_evm. Signed-off-by: Tom Rini <trini@ti.com>
| * | Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-15-869/+987
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| | * | Tegra114: Dalmore: Add pad config tables/code based on pinmux codeTom Warren2013-03-14-14/+280
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pad config registers exist in APB_MISC_GP space, and control slew rate, drive strengh, schmidt, high-speed, and low-power modes for all of the pingroups in Tegra30. This builds off of the pinmux way of constructing init tables to configure select pads (SDIOCFG, for instance) during pinmux_init(). Currently, no padcfg entries exist. SDIO3CFG will be added when the MMC driver is added as per the TRM to work with the SD-card slot on Dalmore E1611. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | Tegra114: fdt: Move aliases from dtsi to dts file as per other TegrasTom Warren2013-03-14-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All other Tegra boards have their alias nodes in the .dts file Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | Tegra114: Fix/update GP padcfg register structTom Warren2013-03-14-8/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Differences in padcfg registers (some removed, some added) between Tegra30 and Tegra114 weren't picked up when I first ported this file. Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | Tegra114: pinmux: Fix bad CAM_MCLK func 3 table entryTom Warren2013-03-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This caused CAM_MCLK's pinmux reg to be locked out, since the table parsing code couldn't find a matching entry for VI_ALT3 and wrote garbage to the register. Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | Tegra: MMC: Added/update SDMMC registers/base addresses for T20/T30Tom Warren2013-03-14-6/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removed SDMMC base addresses from tegra.h since they're no longer used. Added additional vendor-specific SD/MMC registers and bus power defines. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | Tegra30: fdt: Add SDMMC (sdhci) nodes for T30 boards (Cardhu for now)Tom Warren2013-03-14-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Took these values directly from the kernel dts files. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | Tegra30: Cardhu: Add pad config tables/code based on pinmux codeTom Warren2013-03-14-2/+261
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pad config registers exist in APB_MISC_GP space, and control slew rate, drive strengh, schmidt, high-speed, and low-power modes for all of the pingroups in Tegra30. This builds off of the pinmux way of constructing init tables to configure select pads (SDIOCFG, for instance) during pinmux_init(). Currently, only SDIO1CFG is changed as per the TRM to work with the SD-card slot on Cardhu. Thanks to StephenW for the suggestion/original idea. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | Tegra114: pinmux: Update pinmux tables & code, fix a bug w/SDMMC3 initTom Warren2013-03-14-197/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the latest tables & code from our internal U-Boot repo. The SDMMC3_CD, CLK_LB_IN and CLK_LB_OUT offsets in the pingroup table were off by a few indices, causing the pinmux init code to write bad data to the PINMUX_AUX_ regs. This also enabled the lock bit, which made it impossible to reconfig the pads correctly for SDMMC3 (SD card on Dalmore) operation. Also fixes SPI_CS2_N, USB_VBUS_EN0, HDMI_CEC and UART2_RXD/TXD muxes. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | Tegra114: fdt: Sync DT nodes with kernel DT files (GPIO, tegra_car)Tom Warren2013-03-14-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Minor edit to tegra_car node, add gpio node. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | ARM: tegra: implement WAR for Tegra114 CPU reset vectorStephen Warren2013-03-14-4/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A Tegra114 HW bug prevents the main CPU vector from being modified under certain circumstances. Tegra114 A01P and later with a patched boot ROM set the CPU reset vector to 0x4003fffc (end of IRAM). This allows placing an arbitrary jump instruction at that location, in order to redirect to the desired reset vector location. Modify Tegra114's start_cpu() to make use of this feature. This allows CPUs with the patched boot ROM to boot. Based-on-work-by: Jimmy Zhang <jimmzhang@nvidia.com>. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| | * | Tegra30: fdt: Sync DT nodes with kernel DT files (I2C, SPI, GPIO, clock)Tom Warren2013-03-14-34/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Minor edits to clock, apbdma and SPI, make I2C match kernel DT, and add gpio Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | Tegra: MMC: Add DT support to MMC driver for all T20 boardsTom Warren2013-03-14-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tegra_mmc_init() now parses the DT info for bus width, WP/CD GPIOs, etc. Tested on Seaboard, fully functional. Tamonten boards (medcom-wide, plutux, and tec) use a different/new dtsi file w/common settings. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | Tegra: fdt: Add/enhance sdhci (mmc) nodes for all T20 DT filesTom Warren2013-03-14-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux dts files were used for those boards that didn't already have sdhci info populated. Tamonten has their own dtsi file with common sdhci nodes (sourced from Linux). Signed-off-by: Tom Warren <twarren@nvidia.com> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | Tegra: fdt: Change /include/ to #include for C preprocessorTom Warren2013-03-14-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dts Makefile has the arch & board include paths added to DTS_CPPFLAGS. This allows the use of '#include "xyz"' in the dts/dtsi file which helps the C preprocessor find common dtsi include files. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | Tegra114: fdt: Update DT files with I2C info for T114/DalmoreTom Warren2013-03-14-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T114, like T30, does not have a separate/different DVC (power I2C) controller like T20 - all 5 I2C controllers are identical, but I2C5 is used to designate the controller intended for power control (PWR_I2C in the schematics). PWR_I2C is set to 400KHz. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | Tegra: I2C: Add T114 clock support to tegra_i2c driverTom Warren2013-03-14-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T114 has a slightly different I2C clock, with a new (extra) divisor in standard/fast mode and HS mode. Tested on my Dalmore, and the I2C clock is 100KHz +/- 3Hz on my Saleae Logic analyzer. Added a new entry in compat_names for T114 I2C since it differs from the previous Tegra SoCs. A flag is set when T114 I2C HW is found so new features like the extra clock divisor can be used. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
| | * | Tegra114: I2C: Take DVFS out of reset to allow I2C5 (PWR_I2C) to workTom Warren2013-03-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I2C driver can now probe dev 0 (PWR_I2C, where the PMU, etc. lives). This is needed so that the SDIO slot power can be brought up for the MMC driver, so it has to precede those commits. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| | * | tegra: usb: move [start|stop]_port into ehci_hcd_[init|stop]Lucas Stach2013-03-14-19/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ehci_hcd entry points were just calling into the Tegra USB functions. Now that they are in the same file we can just move over the implementation. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-11-09 20:21:51 +0000