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| * | ARM: AM43xx: Adapt to ti_armv7_common.h config fileLokesh Vutla2013-12-18-1/+1
| | | | | | | | | | | | | | | | | | | | | Use ti_armv7_common.h config file to inclde the common configs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | ARM: AM43xx: Update the base addresses of modulesLokesh Vutla2013-12-18-13/+15
| | | | | | | | | | | | | | | | | | | | | PRCM, timer base addresses and offsets are different from AM33xx. Updating the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | Merge remote-tracking branch 'u-boot-pxa/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-18-0/+1
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| | * | ARM: pxa: prevent PXA270 occasional reboot freezesSergei Ianovich2013-12-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum 71 of PXA270M Processor Family Specification Update (April 19, 2010) explains that watchdog reset time is just 8us insead of 10ms in EMTS. If SDRAM is not reset, it causes memory bus congestion and the device hangs. We put SDRAM in selfresh mode before watchdog reset, removing potential freezes. Signed-off-by: Sergei Ianovich <ynvich@gmail.com> CC: Marek Vasut <marex@denx.de>
| * | | arm: tegra: Fix the CPU complex reset masksAlban Bedel2013-12-18-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU complex reset masks are not matching with the datasheet for the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20 and T30 the register consist of groups of 4 bits, with one bit for each CPU core. On T20 the 2 high bits of each group are always stubbed as there is only 2 cores. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swrren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: support SKU b1 of Tegra30Alban Bedel2013-12-18-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the Tegra30 SKU b1 and treat it like other Tegra30 chips. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Reviewed-by: Julian Scheel <julian.scheel@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | Tegra114: Do not program CPCON field for PLLXThierry Reding2013-12-18-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PLLX no longer has the CPCON field on Tegra114, so do not attempt to program it. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | Tegra114: Fix PLLX M, N, P init settingsJimmy Zhang2013-12-18-24/+59
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The M, N and P width have been changed from Tegra30. The maximum value for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should be set accordingly. Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: OMAP5: clocks: Update MPU settings for OPP_NOMLokesh Vutla2013-12-12-12/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per the latest 0.6 version of DM for OMAP5430 ES2.0, MPU_GCLK is given as 1000MHz. In order to achieve this DPLL_MPU should be locked at 2000MHz. Fixing the same and cleaning the previously used dpll values. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | ARM: DRA7xx: Change clk divider settingLokesh Vutla2013-12-12-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Commit "armv7: hw_data: change clock divider setting" updates the setting for m6 divider for 20MHz sys_clk frequency. But missed to update for other sys_clk frequencies. Doing the same. Reported-by: Rajendran, Vinothkumar <vinothr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | arm: omap: abb: add missing includeNikita Kiryanov2013-12-12-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ABB code uses LDELAY but does not include the header that provides its definition. Include the header. Cc: Tom Rini <trini@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Nishanth Menon <nm@ti.com>
| * | arm: am437: Fix offset for USB registersDan Murphy2013-12-12-2/+2
| | | | | | | | | | | | | | | | | | Fix the offset for the USB clock registers Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | ARM: OMAP4: Move TEXT_BASE down to non-HS limitLokesh Vutla2013-12-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the current scenario SPL size is being overlapped with the public stack and not allowing any OMAP4 device to boot. So the suggestion came up was to move the TEXT_BASE down to non-HS limit. Fixing the same and also moving the SRAM_SCRATCH_SPACE_ADDR up to the end of image downloadable area. Discussion on this can be seen here: https://www.mail-archive.com/u-boot@lists.denx.de/msg127147.html Tested on OMAP4460 PANDA. Reported-by: Chao Xu <caesarxuchao@gmail.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFFTom Rini2013-12-12-0/+8
| | | | | | | | | | | | | | | | | | | | | Test on Beaglebone white over cpsw, usb ether and SD card (read and write), performance increased, crc32 of data matches. Signed-off-by: Tom Rini <trini@ti.com>
| * | Revert "ARM: move interrupt_init to before relocation"Albert ARIBAUD2013-12-11-1/+2
| | | | | | | | | | | | | | | | | | | | | Revert commit 0f5141e9 which causes boards starting in FLASH to try and write to a FLASH location. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini2014-01-09-0/+77
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| * | | socfpga/dwmmc: Adding DesignWare MMC driver support for SOCFPGAChin Liang See2014-01-09-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To add the DesignWare MMC driver support for Altera SOCFPGA. It required information such as clocks and bus width from platform specific files (SOCFPGA handoff files) Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2014-01-09-19/+9
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| * | | | sh: sh2: Remove CONFIG_SH2A definition from asm/processor.hNobuhiro Iwamatsu2014-01-09-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SH2 and SH2A use a common header. Both checks are not necessary. This removes CONFIG_SH2A definition from asm/processor.h. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | sh: sh4: Remove CONFIG_SH4A definition from source codeNobuhiro Iwamatsu2014-01-09-13/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SH4 and SH4A are compatible. But some instructions are different from these. In Linux kernel, It is treated as a separate CPU, but for now, I think that there is no need to divide especially in the U-Boot. This removes CONFIG_SH4A definition from source code, SH4A is treated as SH4. And this fix white space. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | sh: sh2: Change CONFIG_SYS_HZ to CONFIG_SH_CMT_CLK_FREQNobuhiro Iwamatsu2014-01-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_HZ of SH2 is not used as frequency of base timer. This is the correct clock of CMT. This changes from CONFIG_SYS_HZ to CONFIG_SH_CMT_CLK_FREQ, in order to use CONFIG_SYS_HZ as clock of CMT. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | | | sh: sh4: Add CONFIG_SH4 definition to config.mk of SH4Nobuhiro Iwamatsu2014-01-08-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | sh: sh3: Add CONFIG_SH3 definition to config.mk of SH3Nobuhiro Iwamatsu2014-01-08-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | sh: sh2: Add CONFIG_SH2 definition to config.mk of SH2Nobuhiro Iwamatsu2014-01-08-1/+1
| |/ / / | | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | | sandbox: Add a prototype for cleanup_before_linux()Simon Glass2014-01-08-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This function is defined but has no prototype declaration. Add it. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | sandbox: Add facility to save/restore sandbox stateSimon Glass2014-01-08-4/+490
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is often useful to be able to save out the state from a sandbox test run, for analysis or to restore it later to continue a test. Add generic infrastructure for doing this using a device tree binary file. This is a flexible tagged file format which is already supported by U-Boot, and it supports hierarchy if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Hung-ying Tyan <tyanh@chromium.org>
* | | | sandbox: Allow reading/writing of RAM bufferSimon Glass2014-01-08-3/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is useful to be able to save and restore the RAM contents of sandbox U-Boot either for setting up tests, for later analysys, or for chaining together multiple tests which need to keep the same memory contents. Add a function to provide a memory file for U-Boot. This is read on start-up and written when shutting down. If the file does not exist on start-up, it will be created when shutting down. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | sandbox: Add -i option to enter interactive modeSimon Glass2014-01-08-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Normally when U-Boot starts with a command (-c option) it quits when the command completes. Normally this is what is requires, since the test is likely complete. Provide an option to jump into the console instead, so that debugging or other tasks may be performed before quitting. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | sandbox: Allow the console to work earlierSimon Glass2014-01-08-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With sandbox, errors and problems may be reported before console_init_f() is executed. For example, an argument may not parse correctly or U-Boot may panic(). At present this output is swallowed so there is no indication what is going wrong. Adjust the console to deal with a very early sandbox setup, by detecting that there is no global_data yet, and calling os functions in that case. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | sandbox: Implement the bootm command for sandboxSimon Glass2014-01-08-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When sandbox does a 'bootm' to run a kernel we cannot actually execute it. So just exit sandbox, which is essentially what U-Boot does on other archs. Also, allow sandbox to use bootm on any kernel, so that it can be used to test booting of kernels from any architecture. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | sandbox: Allow return from board_init_f()Simon Glass2014-01-08-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The execution flow becomes easier if we can return from board_init_f() as ARM does. We can control things from start.c instead of having to call back into that file from other places. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | sandbox: Correct help message <arg> garblingSimon Glass2014-01-08-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The <arg> is displayed for options with no argument, and omitted for those with an argument. Swap this around. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | sandbox: Improve/augment memory allocation functionsSimon Glass2014-01-08-2/+43
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement realloc() and free() for sandbox, by adding a header to each block which contains the block size. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Hung-ying Tyan <tyanh@chromium.org>
* | | powerpc/t208x: fix macro CONFIG_SYS_FSL_NUM_USB_CTRLSShengzhou Liu2014-01-02-1/+1
| | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_FSL_NUM_USB_CTRLS is no longer used, update it to new CONFIG_USB_MAX_CONTROLLER_COUNT. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* | | powerpc/mpc85xx: Add support for single source clockingPriyanka Jain2014-01-02-2/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Single-source clocking is new feature introduced in T1040. In this mode, a single differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-source clocking mode whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
* | | sh: add support for sh7753evb boardYoshihiro Shimoda2013-12-18-0/+199
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SH7753 EVB board has SH7753, 512MB DDR3-SDRAM, SPI ROM, Gigabit Ethernet, and eMMC. This patch support the following functions: - 512MB DDR3-SDRAM, SCIF4, SPI ROM, Gigabit Ethernet, eMMC Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-blackfinTom Rini2013-12-16-11/+20
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| * | | blackfin: remove build warningSonic Zhang2013-12-16-10/+15
| | | | | | | | | | | | | | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
| * | | blackfin: fixing warning by including proper headersSonic Zhang2013-12-16-1/+5
| | | | | | | | | | | | | | | | Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* | | | Makefile: Select objects by CONFIG_ rather than $(ARCH) or $(CPU)Masahiro Yamada2013-12-16-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert like follows: CPU mpc83xx -> CONFIG_MPC83xx CPU mpc85xx -> CONFIG_MPC85xx CPU mpc86xx -> CONFIG_MPC86xx CPU mpc5xxx -> CONFIG_MPC5xxx CPU mpc8xx -> CONFIG_8xx CPU mpc8260 -> CONFIG_8260 CPU ppc4xx -> CONFIG_4xx CPU x86 -> CONFIG_X86 ARCH x86 -> CONFIG_X86 ARCH powerpc -> CONFIG_PPC Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | common/cmd_bootm: extend do_bootm_vxworks to support the new VxWorks boot ↵Miao Yan2013-12-16-0/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interface. The next version VxWorks adopts device tree (for PowerPC and ARM) as its hardware description mechanism. For PowerPC, the boot interface conforms to the ePAPR standard, which is: void (*kernel_entry)(ulong fdt_addr, ulong r4 /* 0 */, ulong r5 /* 0 */, ulong r6 /* EPAPR_MAGIC */, ulong r7 /* IMA size */, ulong r8 /* 0 */, ulong r9 /* 0 */) For ARM, the boot interface is: void (*kernel_entry)(void *fdt_addr) Signed-off-by: Miao Yan <miao.yan@windriver.com> [trini: Fix build error when !CONFIG_OF_FDT is set, typo on PowerPC, missing extern ft_fixup_num_cores] Signed-off-by: Tom Rini <trini@ti.com>
* | | | PowerPC: merge commonly-defined flagsMasahiro Yamada2013-12-13-39/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PLATFORM_RELFLAGS += -meabi PLATFORM_CPPFLAGS += -ffixed-r2 were defined in all arch/powerpc/${CPU}/config.mk. This commit moves them to arch/powerpc/config.mk. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | ARM:PXA: Correct tick_to_time / us_to_tick to use lldivTom Rini2013-12-13-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Cc: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Marek Vasut <marex@denx.de>
* | | | ARM:zynq: Correct __udelay to use lldivTom Rini2013-12-13-2/+1
| | | | | | | | | | | | | | | | | | | | Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Tom Rini <trini@ti.com>
* | | | Makefile: use two double-quotations as a pairMasahiro Yamada2013-12-13-2/+2
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some editors such as Emacs can highlight source files. But their parser algorithm is not perfect. If you use one double-quotation alone, some editor cannot handle it nicely and mark source lines as a string by mistake. It is preferable to use two double-quotations as a pair. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | powerpc/mpc85xx: Update CONFIG_SYS_FSL_TBCLK_DIV for T1040Prabhakar Kushwaha2013-12-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The default value of CONFIG_SYS_FSL_TBCLK_DIV is 16. So, update its value as default. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | | powerpc/t4240: Add a frequency setting case for fman1Shaohui Xie2013-12-11-0/+3
|/ / | | | | | | | | | | | | A new valid setting case added for fman1, it uses platform frequency. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-12-10-480/+6018
|\ \ | | | | | | | | | | | | | | | | | | | | | Conflicts: board/samsung/trats2/trats2.c include/configs/exynos5250-dt.h Signed-off-by: Tom Rini <trini@ti.com>
| * \ Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-10-10441/+865
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/armv7/rmobile/Makefile doc/README.scrapyard Needed manual fix: arch/arm/cpu/armv7/omap-common/Makefile board/compulab/cm_t335/u-boot.lds
| * | | at91: switch coloured LED to gpio APIAndreas Bießmann2013-12-09-9/+7
| | | | | | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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