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* powerpc: mpc85xx watchdog init added to init_funcBoschung, Rainer2014-08-01-0/+3
| | | | | | | | | | | When CONFIG_WATCHDOG is defined the board initialization just performs a WATCHDOG_RESET, an initialization of the watchdog is not done. This has been modified fot the MPC85xx, the board initialization calls its watchdog initialitzation allowing for full watchdog configuration very early in the boot phase. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx: watchdog initialisation addedBoschung, Rainer2014-08-01-0/+8
| | | | | | | | Function to inititialize the cpu watchdog added. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> [York Sun: Add prototype in watchdog.h] Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc: macros for e500mc timer regs addedBoschung, Rainer2014-08-01-0/+5
| | | | | | | | | | | | | | | | For e500mc cores the watchdog timer period has to be set by means of a 6bit value, that defines the bit of the timebase counter used to signal a watchdog timer exception on its 0 to 1 transition. The macro used to set the watchdog period TCR_WP, was redefined for e500mc to support 6 WP setting. The parameter (x) given to the macro specifies the prescaling factor of the time base clock (fTB): watchdog_period = 1/fTB * 2^x Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx: fix interrupt init to not affect watchdogBoschung, Rainer2014-08-01-1/+1
| | | | | | | | TCR watchdog bit are overwritten when dec interrupt is enabled. This has been fixed with this patch. Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx/t104x: Enable L2 and CPC cache when resumeTang Yuantian2014-07-22-76/+98
| | | | | | | | | | | When resume from deep sleep, uboot needs to enable L2 and CPC cache, or they would be keeping unusable in kernel because kernel didn't enble or initialized them. This patch didn't change the existing L2 cache enabling code, just put them in a function. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/chassis2: Configure and enable L2 cache for PPC clusters onlyShaveta Leekha2014-07-22-1/+2
| | | | | | Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t4240qds: fix offset of serdes when checking reference clockShaohui Xie2014-07-22-0/+6
| | | | | | | | T4240 has 4 serdes, each serdes has 4k memory space, two PLLs. We use PLL1CR0 to check the serdes reference clock. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/ddr: Fix DDR4 driver for ARMYork Sun2014-07-22-0/+8
| | | | | | | Previously the driver was only tested on Power SoCs. Different barrier instructions are needed for ARM SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Removed support for G4060Sandeep Singh2014-07-22-2/+0
| | | | | | | G4060 has no PA cores, hence removing its support. Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* qe: move immap_qe.h from arch directory into common directoryZhao Qiang2014-07-22-584/+2
| | | | | | | | ls1021 is arm-core and supports qe too. Move immap_qe.h into common directory for both arm and powerpc. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/85xx: add fdt_fixup_dma3Shengzhou Liu2014-07-22-0/+47
| | | | | | | | On some SoC(e.g. T2080/T4240) the 3rd DMA is not functional if SRIO2 is chosen. we add fdt_fixup_dma3() to disable the 3rd DMA if SRIO2 is chosen. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* m68k: define __kernel_size_t as unsinged int againMasahiro Yamada2014-07-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ddc94378d changed the definition of __kernel_size_t from unsigned int to unsigned long. It is true that it fixed warnings on some crosstools but it increased warnings on the others. The problem is that we cannot see consistency in terms of the typedef of __kernel_size_t on M68K architecture. However, I'd like to suggest to have __kernel_size_t to be unsigned int again. Rationale: [1] Linux Kernel defines __kernel_size_t on M68K as unsigned int. Let's stick to the Linux's way. [2] We want to build boards with popular pre-built toolchains, not the one locally-built by indivisuals. I think m68-linux-gcc which can be downloaded from www.kernel.org is the candidate for our _recommended_ toolchains. With this patch, all the m68k boards can be built without any warnings. Give it a try with the following crosstools: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.6.3/ x86_64-gcc-4.6.3-nolibc_m68k-linux.tar.xz or https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/ x86_64-gcc-4.9.0-nolibc_m68k-linux.tar.xz (The latter is newer.) Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Cc: Jason Jin <Jason.jin@freescale.com>
* sparc: merge LEON2 and LEON3 linker scriptsMasahiro Yamada2014-07-22-4/+2
| | | | | | | | | | | | | | | | | | There is only one line diff between LEON2 and LEON3 linker scripts: - arch/sparc/cpu/leon2/start.o (.text) + arch/sparc/cpu/leon3/start.o (.text) They can be written in the same way: */start.o (.text) So, board/gaisler/grsim_leon2/u-boot.lds and arch/sparc/cpu/leon3/u-boot.lds can be merged into arch/sparc/cpu/u-boot.lds. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Daniel Hellstrom <daniel@gaisler.com>
* sparc: merge LEON3 linker scriptsMasahiro Yamada2014-07-22-0/+144
| | | | | | | | | | | | | | | | The linker scripts of LEON3 - board/gaisler/grsim/u-boot.lds - board/gaisler/gr_cpci_ax2000/u-boot.lds - board/gaisler/gr_ep2s60/u-boot.lds - board/gaisler/gr_xc3s_1500/u-boot.lds are the same (except cosmetic differences such as indentation). This commit merges them into arch/sparc/cpu/leon3/u-boot.lds. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Daniel Hellstrom <daniel@gaisler.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-07-11-2/+2
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| * i.MX6DL/S: add drive-strength back to pads DISP0_DAT2/DAT10Eric Nelson2014-07-10-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pad settings for DISP0_DATA02 and DISP0_DAT10 were not set in the same way as DISP0_DAT00-23, causing much flicker in parallel RGB displays on Dual-Lite and Solo processors. These settings now match the i.MX6 Dual and Quad core versions. Note that this fixes a regression in commit b47abc3 and that this is the second time we've had a regression on these two pads (See commit e654ddf). Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* | usb: phy: omap_usb_phy: implement usb_phy_power() for AM437xFelipe Balbi2014-07-09-0/+5
| | | | | | | | | | | | | | | | Newer AM437x silicon requires us to explicitly power up the USB2 PHY. By implementing usb_phy_power() we can achieve that. Signed-off-by: Felipe Balbi <balbi@ti.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-07-09-4/+3
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| * mx6: soc: Update the comments of set_ldo_voltage()Fabio Estevam2014-07-09-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 3d622b78 (mx6: soc: Introduce set_ldo_voltage()) introduces set_ldo_voltage() function that can be used to set the voltages of any of the three LDO regulators controlled by the PMU_REG_CORE register. Prior to this commit there was a single set_vddsoc() which only configured the VDDSOC regulator. Update the comments to align with the new set_ldo_voltage() implementation. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * MX6: Correct calculation of PLL_SYSAndre Renaud2014-07-09-1/+1
| | | | | | | | | | | | | | DIV_SELECT is used as Fout = Fin * div_select / 2.0, so we should do the shift after the multiply to avoid rounding errors Signed-off-by: Andre Renaud <andre@bluewatersys.com>
* | kmake: include DTB section into u-boot.bin if CONFIG_OF_EMBED enabledAlexey Ignatov2014-07-07-0/+4
| | | | | | | | | | Fixes a bug when objcopy doesn't put .dtb.init.rodata section to resulting u-boot.bin, so u-boot was unable to find embedded DTB.
* | blackfin, powerpc: remove redundant definitions of ARRAY_SIZEMasahiro Yamada2014-07-07-5/+0
| | | | | | | | | | | | | | | | | | Since ARRAY_SIZE macro is defined in include/common.h, re-defining it in arch-specific files is redundant. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Sonic Zhang <sonic.zhang@analog.com>
* | blackfin: Add more dcache functionsVasili Galka2014-07-07-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | Add invalidate_dcache_range() and flush_dcache_range() for the blackfin architecture. Such functions already exist on this arch with different names, so just forward the call. This fixes the build of bf609-ezkit board as it uses drivers/net/designware.c which requires the above functions. Cc: Sonic Zhang <sonic.adi@gmail.com>, Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Vasili Galka <vvv444@gmail.com>
* | m68k: Fix incorrect memory access on M5235Vasili Galka2014-07-07-16/+23
| | | | | | | | | | | | | | | | | | | | | | The csarX and cscrX registers in the fbcs_t struct are 16-bit for CONFIG_M5235 and 32-bit wide otherwise. The code in cpu_init.c accessed them always as 32-bit, effectively creating a wrong memory access on M5235. Fixed that by choosing out_be16/out_be32 depending on whether CONFIG_M5235 is defined or not. Cc: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Vasili Galka <vvv444@gmail.com>
* | m68k: Fix bug, "address of" operator was forgottenVasili Galka2014-07-07-1/+1
| | | | | | | | | | | | | | | | in_be16() shall be passed a pointer to register and not its value. This is clearly a typo resulting in a wrong memory access, so fix it. Cc: Alison Wang <b18965@freescale.com>, Jason Jin <Jason.jin@freescale.com> Signed-off-by: Vasili Galka <vvv444@gmail.com>
* | mpc8xx: remove spc1920 board supportMasahiro Yamada2014-07-07-1/+0
| | | | | | | | | | | | This board is old enough and has no maintainer. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | mpc8xx: remove fads board supportMasahiro Yamada2014-07-07-112/+2
| | | | | | | | | | | | These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | mpc8xx: remove netta, netta2, netphone board supportMasahiro Yamada2014-07-07-20/+0
| | | | | | | | | | | | These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | mpc8xx: remove RPXlite_dw, quantum board supportMasahiro Yamada2014-07-07-14/+0
| | | | | | | | | | | | These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | mpc8xx: remove qs850, qs860t board supportMasahiro Yamada2014-07-07-10/+0
| | | | | | | | | | | | These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | am43xx: Tune the system to avoid DSS underflowsCooper Jr., Franklin2014-07-07-4/+49
| | | | | | | | | | * This is done by limiting the ARM's bandwidth and setting DSS priority in the EMIF controller to ensure underflows do not occur.
* | am43xx: Update EMIF DDR3 Configuration for AM43x GPFranklin S. Cooper Jr2014-07-07-0/+2
| | | | | | | | | | | | | | | | | | * Boot failures have been discovered due to a combination of routing issues and non optimal ddr3 timings in the EMIF * Since ddr3 timings are different after significant board layout changes different timings are required for alpha, beta and production boards. Signed-off-by: Franklin S. Cooper Jr <fcooper@ti.com>
* | build: define CPU only when arch/${ARCH}/cpu/${CPU} existsMasahiro Yamada2014-07-07-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The directory arch/${ARCH}/cpu/${CPU} does not exist in avr32, blackfin, microblaze, nios2, openrisc, sandbox, x86. These architectures have only one CPU type. Defining CPU should not be required for such architectures. This commit allows cpu field (= the 3rd field of boards.cfg) to be kept blank. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Sonic Zhang <sonic.zhang@analog.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* | ARM: emif4: wait for CM_DLL_READYST to be setJeroen Hofstee2014-07-07-1/+1
| | | | | | | | | | | | | | | | | | The code intends for the CM_DLL_READYST to be set, but actually polls till any bit is set since the logical AND is used instead of the bitwise one is used. Fix it. cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2014-07-07-0/+2
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| * | i2c: tegra: use repeated start for readsStephen Warren2014-07-03-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I2C read transactions are typically implemented as follows: START(write) address REPEATED_START(read) data... STOP However, Tegra's I2C driver currently implements reads as follows: START(write) address STOP START(read) data... STOP This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board, leading to corrupted read data in some cases. Fix the driver to chain the transactions together using repeated starts to solve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
* | | socfpga: Relocate arch common functions away from boardChin Liang See2014-07-05-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To move the arch common function away from board folder to arch/arm/cpu/armv7/socfpga folder. Its to avoid code duplication for other non Altera dev kit which is using socfpga device. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: Detlev Zundel <dzu@denx.de>
* | | arm: Fix armv8 compilation errorShaibal.Dutta2014-07-05-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix following compilation error when CONFIG_ARM64 is defined Error: unknown or missing system register name at operand 2 -- `mrs x0,daifmsr daifset,#3' Signed-off-by: Shaibal.Dutta <shaibal.dutta@broadcom.com> Signed-off-by: Darwin Rambo <drambo@broadcom.com> Reviewed-by: Darwin Rambo <drambo@broadcom.com>
* | | arm: spl: fix include guardJeroen Hofstee2014-07-05-2/+2
| | | | | | | | | | | | | | | cc: Tom Rini <trini@ti.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | | socfpga: Adding Scan Manager driverChin Liang See2014-07-05-1/+305
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Scan Manager driver will be called to configure the IOCSR scan chain. This configuration will setup the IO buffer settings Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* | | socfpga: Adding DesignWare watchdog supportChin Liang See2014-07-05-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To enable the DesignWare watchdog support at SOCFPGA Cyclone V dev kit. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
* | | arm: ep9315: Return back Cirrus Logic EDB9315A board supportSergey Kostanbaev2014-07-04-27/+521
| | | | | | | | | | | | | | | | | | | | | This patch returns back support for old ep93xx processors family Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com> Cc: albert.u.boot@aribaud.net
* | | ARM: cache_v7: use __weakJeroen Hofstee2014-07-04-55/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is not only more readable but also prevents a warning about a missing prototype. The prototypes which are actually missing are added. cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: Tom Rini <trini@ti.com>
* | | ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board supportYork Sun2014-07-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2085A is an ARMv8 implementation. This adds board support for emulator and simulator: Two DDR controllers UART2 is used as the console IFC timing is tightened for speedy booting Support DDR3 and DDR4 as separated targets Management Complex (MC) is enabled Support for GIC 500 (based on GICv3 arch) Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
* | | armv8/fsl-lsch3: Add support to load and start MC FirmwareJ. German Rivera2014-07-03-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding support to load and start the Layerscape Management Complex (MC) firmware. First, the MC GCR register is set to 0 to reset all cores. MC firmware and DPL images are copied from their location in NOR flash to DDR. MC registers are updated with the location of these images. Deasserting the reset bit of MC GCR register releases core 0 to run. Core 1 will be released by MC firmware. Stop bits are not touched for this step. U-boot waits for MC until it boots up. In case of a failure, device tree is updated accordingly. The MC firmware image uses FIT format. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
* | | ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoCYork Sun2014-07-03-1/+937
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
* | | ARMv8: Adjust MMU setupYork Sun2014-07-03-30/+44
| | | | | | | | | | | | | | | | | | | | | Make MMU function reusable. Platform code can setup its own MMU tables. Signed-off-by: York Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
* | | Added 64-bit MMIO accessors for ARMv8J. German Rivera2014-07-03-0/+8
| | | | | | | | | | | | | | | | | | | | | This is needed for accessing peripherals with 64-bit MMIO registers, from ARMv8 processors. Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
* | | arm: Add support for semihosting for armv8 fastmodel targets.Darwin Rambo2014-07-03-0/+255
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The armv8 ARM Trusted Firmware (ATF) can be used to load various ATF images and u-boot, and does this for virtual platforms by using semihosting. This commit extends this idea by allowing u-boot to also use semihosting to load the kernel/ramdisk/dtb. This eliminates the need for a bootwrapper and produces a more realistic boot sequence with virtual models. Though the semihosting code is quite generic, support for armv7 in fastmodel is less useful due to the wide range of available silicon and the lack of a free armv7 fastmodel, so this change contains an untested armv7 placeholder for the service trap opcode. Please refer to doc/README.semihosting for a more detailed description of semihosting and how it is used with the armv8 virtual platforms. Signed-off-by: Darwin Rambo <drambo@broadcom.com> Cc: trini@ti.com Cc: fenghua@phytium.com.cn Cc: bhupesh.sharma@freescale.com
* | Merge remote-tracking branch 'u-boot-samsung/master'Albert ARIBAUD2014-07-01-193/+582
|\ \ | | | | | | | | | | | | | | | | | | | | | Conflicts: boards.cfg Conflict was trivial between goni maintainer change and lager_nor removal.
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