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* ARM: DRA7: Add macros for voltage values for all OPPsAnna, Suman2016-06-02-6/+23
| | | | | | | | | | | | | | Define specific macros for the voltage values for all voltage domains for all applicable OPPs - OPP_NOM, OPP_OD and OPP_HIGH. No separate macros are defined for VD_MPU and VD_CORE at OPP_OD and OPP_HIGH as these use the same values as OPP_NOM. The current macros will be used as common macros that can be redefined appropriately based on a selected OPP configuration at build time. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA7: Consolidate voltage macros across different SoCsAnna, Suman2016-06-02-23/+16
| | | | | | | | | | | | | The voltage values for each voltage domain at an OPP is identical across all the SoCs in the DRA7 family. The current code defines one set of macros for DRA75x/DRA74x SoCs and another set for DRA72x macros. Consolidate both these sets into a single set. This is done so as to minimize the number of macros used when voltage values will be added for other OPPs as well. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA7: Define common macros for efuse register offsetsAnna, Suman2016-06-02-10/+17
| | | | | | | | | | | | | | Define a set of common macros for the efuse register offsets (different for each OPP) that are used to get the AVS Class 0 voltage values and ABB configuration values. Assign these common macros to the register offsets for OPP_NOM by default for all voltage domains. These common macros can then be redefined properly to point to the OPP specific efuse register offset based on the desired OPP to program a specific voltage domain. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA7: Update/Correct MPU and CORE OPP_NOM voltage valuesAnna, Suman2016-06-02-4/+4
| | | | | | | | | | | | | | | | | The current OPP_NOM voltage values defined for the MPU and CORE voltage domains are based on the initial DRA75x_74x_SR1.1_DM data manual. As per this DM, the PMIC boot voltage can be set to either 1.10V or 1.15V for VD_MPU, and either 1.06V or 1.15V for VD_CORE. While the current values are correct, the latter set of values are the values that are common across all DRA75x, DRA72x SoCs and for all current Silicon revisions. So, update both the MPU and CORE OPP_NOM voltages to 1.15V. The macros are also slightly reorganized so that both the MPU and CORE voltage domain values are defined together. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* dra7xx: Enable USB_PHY3 32KHz clockRoger Quadros2016-06-02-2/+14
| | | | | | | DRA7xx has a 32KHz PHY clock for USB_PHY3 that must be enabled for USB1 instance in Super-Speed. Signed-off-by: Roger Quadros <rogerq@ti.com>
* ARM: OMAP5+: Provide enable/disable_usb_clocks() for CONFIG_USB_XHCI_OMAPRoger Quadros2016-06-02-2/+2
| | | | | | | | | CONFIG_USB_XHCI_OMAP is enabled for host mode independent of CONFIG_USB_DWC3 which is meant for gadget mode only. We need enable/disbale_usb_clocks() for host mode as well so provide for it. Fixes: 09cc14f4bcbf ("ARM: AM43xx: Add functions to enable and disable USB clocks" Signed-off-by: Roger Quadros <rogerq@ti.com>
* arm: lib: Split asm symbols into different .text subsectionsMarek Vasut2016-06-02-0/+38
| | | | | | | | | | | | | Split each symbol in lib1funcs into different .text.foo section instead of placing all of them into plain .text . This allows the linker to collect and discard unused assembler symbols. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: lib: Import Thumb1 functionsMarek Vasut2016-06-02-0/+53
| | | | | | | | | | | | Import functions into lib1funcs.S which are required for Thumb1 build. These functions come from gcc 5.3.1 release. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: lib: import muldi3.S from LinuxMarek Vasut2016-06-02-1/+48
| | | | | | | | | | | | | | | | | Import muldi3.S from Linux 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326 on arm32. This file implements __aeabi_lmul and it's alias __muldi3, which is needed when doing Thumb1 builds. This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED which is necessary for correct build of these files both in ARM and Thumb mode, just like Linux does. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: lib: Repair Warning: conditional infixes are deprecated in unified syntaxMarek Vasut2016-06-02-4/+4
| | | | | | | | | | | | | | Fix the following warning when building for thumb2 target by tweaking the instruction syntax: Warning: conditional infixes are deprecated in unified syntax Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: lib: Import __do_div64 from LinuxMarek Vasut2016-06-02-1/+213
| | | | | | | | | | | | | | | | | | | | Import __do_div64 from Linux 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326 on arm32. This function is for some toolchains, which generate _udivmoddi4() for 64 bit division. Since we do not support stack unwinding, instead of importing the whole asm/unwind.h and all the baggage, this patch defines empty UNWIND() macro. This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED which is necessary for correct build of these files both in ARM and Thumb mode, just like Linux does. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: lib: Fix uldivmod.S build on Thumb2Marek Vasut2016-06-02-5/+3
| | | | | | | | | | | | | | | | This assembler source won't build in Thumb2 mode, so fix it adding the necessary Thumb2 conditional macros from unified.h . This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED which is necessary for correct build of these files both in ARM and Thumb mode, just like Linux does. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: lib: Sync libgcc 32b division/modulo operationsMarek Vasut2016-06-02-430/+353
| | | | | | | | | | | | | | | | | | | | | | | | Sync the libgcc 32bit division and modulo operations with Linux 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326 . The functions in these four files are present in lib1funcs.S in Linux, so replace these files with lib1funcs.S from Linux. Since we do not support stack unwinding, instead of importing the whole asm/unwind.h and all the baggage, this patch defines empty UNWIND() macro in lib1funcs.S . Moreover, to make all of the functions available, define CONFIG_AEABI , which is safe, because U-Boot is always compiled with ARM EABI. This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED which is necessary for correct build of these files both in ARM and Thumb mode, just like Linux does. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: lib: Sync libgcc shift operationsMarek Vasut2016-06-02-12/+24
| | | | | | | | | | | | | | | | | | Sync the libgcc shift operations with Linux kernel 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326 . Syncing these three files is easy, as there is almost no change in them, except the addition of Thumb support. This patch also defines CONFIG_THUMB2_KERNEL and CONFIG_ARM_ASM_UNIFIED which is necessary for correct build of these files both in ARM and Thumb mode, just like Linux does. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: lib: Drop underscore from private libgcc filenamesMarek Vasut2016-06-02-3/+3
| | | | | | | | | | | | | Drop the underscore from the filenames of files implementing libgcc routines. There is no functional change. This change is done to make sync with Linux kernel easier. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: include: Import unified.h from Linux kernelMarek Vasut2016-06-02-7/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import unified.h from Linux kernel 4.4.6 , commit 0d1912303e54ed1b2a371be0bba51c384dd57326 . This header file contains macros used in libgcc functions in Linux kernel on ARM and will be needed for the libgcc sync. Since unified.h defines the W(instr) macro, we must drop this from the macro from memcpy.S , otherwise this triggers a warning about symbol redefinition. In order to keep the changes to unified.h to the minimum, tweak arch/arm/lib/Makefile such that it defines the CONFIG_ARM_ASM_UNIFIED macro, which places .syntax unified into all of the assembler files. This is mandatory. Moreover, for Thumb2 build, define CONFIG_THUMB2_KERNEL macro if and only if Thumb2 build is enabled. This macro is checked by unified.h and toggles between ARM and Thumb2 variant of the instructions in the assembler source files. Finally, this patch defines __LINUX_ARM_ARCH__=N macro based on the new CONFIG_SYS_ARM_ARCH Kconfig option. This macro selects between more optimal and more dense codepaths which work on armv5 and newer and less optimal codepaths which work on armv4 and possible armv3m. Tegra2 needs the same special handling as it does in arch/arm/Makefile to cater for the arm720t boot core. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: config: Introduce CONFIG_SYS_ARM_ARCHMarek Vasut2016-06-02-0/+14
| | | | | | | | | | | | | | Introduce new helper Kconfig option, which is automatically set to the version of ARM architecture for which the U-Boot is built. This is useful when selecting tuning options in the libgcc imported from Linux kernel. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: Select CONFIG_ARM64 for Cavium ThunderXMarek Vasut2016-06-02-0/+1
| | | | | | | | Select the config option, since this board is ARM64. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
* arm: Treat arm946es as v5teMarek Vasut2016-06-02-1/+1
| | | | | | | | The arm946es is armv5te , so use -march=armv5te instead of armv4t. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2016-05-31-115/+248
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| * mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro defineWills Wang2016-05-31-1/+2
| | | | | | | | | | | | Add AR933X_PLL_SWITCH_CLOCK_CONTROL_REG define for ar933x chip. Signed-off-by: Wills Wang <wills.wang@live.com>
| * mips: ath79: Add support for ungating USB and ethernet on qca953xWills Wang2016-05-31-0/+50
| | | | | | | | | | | | Add code to ungate USB and ethernet controller on qca953x Signed-off-by: Wills Wang <wills.wang@live.com>
| * mips: ath79: ap121: Enable ethernetWills Wang2016-05-31-2/+7
| | | | | | | | | | | | | | This patch enable network function for ap121 board. Signed-off-by: Wills Wang <wills.wang@live.com> Acked-by: Marek Vasut <marex@denx.de>
| * mips: ath79: Rename get_bootstrap into ath79_get_bootstrapWills Wang2016-05-31-28/+15
| | | | | | | | | | | | | | | | Add a platform prefix for function name in order to make more readable, and move it into ath79.h Signed-off-by: Wills Wang <wills.wang@live.com> Acked-by: Marek Vasut <marex@denx.de>
| * MIPS: Abstract cache op loops with a macroPaul Burton2016-05-31-41/+18
| | | | | | | | | | | | | | | | | | | | | | The various cache maintenance routines perform a number of loops over cache lines. Rather than duplicate the code for performing such loops, abstract it out into a new cache_loop macro which performs an arbitrary number of cache ops on a range of addresses. This reduces duplication in the existing L1 cache maintenance code & will allow for not adding further duplication when introducing L2 cache support. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Split I & D cache line size configPaul Burton2016-05-31-20/+25
| | | | | | | | | | | | | | | | | | | | | | | | Allow L1 Icache & L1 Dcache line size to be specified separately, since there's no architectural mandate that they be the same. The [id]cache_line_size functions are tidied up to take advantage of the fact that the Kconfig entries are always present to simply check them for zero rather than needing to #ifdef on their presence. Signed-off-by: Paul Burton <paul.burton@imgtec.com> [removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: Move cache sizes to KconfigPaul Burton2016-05-31-4/+32
| | | | | | | | | | | | | | | | | | | | | | | | Move details of the L1 cache line sizes & total sizes into Kconfig, defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is introduced to allow platforms to select auto-detection of cache sizes, and it defaults to being enabled if none of the cache sizes are set by the configuration (ie. sizes are all the default 0), and code is adjusted to #ifdef on that rather than on the definition of the sizes (which will always be defined even if 0). Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: remove dead code from asm/u-boot-mips.hDaniel Schwierzeck2016-05-31-18/+3
| | | | | | | | | | | | | | | | Those wrappers for linker symbols were once used in the MIPS specific board.c implementation. Since the migration to generic board.c, those wrappers are dead code and can be removed. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: add tune for MIPS 34kcDaniel Schwierzeck2016-05-31-0/+4
| | | | | | | | | | | | Add tune Kconfig option for MIPS 34kc. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: provide a default u-boot-spl.ldsDaniel Schwierzeck2016-05-31-2/+93
| | | | | | | | | | | | | | | | | | | | | | | | Provide a default linker script for SPL binaries. Start address and size of text section and BSS section are configurable. All sections are arranged in a way that only relevant sections are kept in the code section for maximum size reduction. All other sections are kept but moved outside the code section to help with debugging. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
| * malta: Allow MIPS64 buildsPaul Burton2016-05-31-0/+3
| | | | | | | | | | | | | | | | Both real Malta boards & emulators that mimic Malta (eg. QEMU) can support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards, which enables the user to make use of the whole 64 bit address space. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Use CPHYSADDR to implement mips32 virt_to_physPaul Burton2016-05-31-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use CPHYSADDR to implement the virt_to_phys function for converting from a virtual to a physical address for MIPS32, much as is already done for MIPS64. This allows for virt_to_phys to work regardless of whether the address being translated is in kseg0 or kseg1, unlike the previous subtraction based approach which only worked for addresses in kseg0. This allows for drivers to provide an address to virt_to_phys without needing to manually ensure that kseg1 addresses are converted to equivalent kseg0 addresses first. This patch is equivalent to this Linux patch currently waiting to be reviewed & merged: https://patchwork.linux-mips.org/patch/12564/ Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-05-30-30/+650
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| * x86: baytrail: acpi: Fix I/O APIC ID in the MADT tableBin Meng2016-05-30-1/+1
| | | | | | | | | | | | | | | | So far this is hardcoded to 2, but it should really be read from the I/O APIC register. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Generate ACPI FADT/MADT tablesBin Meng2016-05-30-0/+164
| | | | | | | | | | | | | | Generate quark platform-specific FADT/MADT tables. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add platform ASL filesBin Meng2016-05-30-0/+433
| | | | | | | | | | | | | | | | This adds basic quark platform ASL files. They are intended to be included in dsdt.asl of any board that is based on this platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Prepare device.h for inclusion by ASLBin Meng2016-05-30-6/+15
| | | | | | | | | | | | | | | | | | There is a device.h for quark on-chip devices, mainly for definitions of internal PCI device numbers, but it's not ready to be included by ASL files. Update to use hex numbers for PCI dev and __ASSEMBLY__. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: acpi: Make irqroute.asl commonBin Meng2016-05-30-2/+2
| | | | | | | | | | | | | | | | | | | | The irqroute.asl file is already common enough to all x86 platforms. Platform ASL files need only provide a irqroute.h to describe how internal PCI devices and PCIe downstream port devices' INTx pins are routed to which PIRQ pin. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: acpi: Create a common irqlinks ASL fileBin Meng2016-05-30-21/+35
| | | | | | | | | | | | | | | | | | | | | | Move the irqlinks.asl file currently in the BayTrail directory to a common place to be shared among all x86 platforms. As the PIRQ routing control programming interface is common to Intel chipsets, leave the common part in the common file, and move the platform specific part to the platform files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-05-27-35/+70
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For odroid-c2 (arch-meson) for now disable designware eth as meson now needs to do some harder GPIO work. Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: lib/efi_loader/efi_disk.c Modified: configs/odroid-c2_defconfig
| * | dm: rockchip: Enable CONFIG_BLKSimon Glass2016-05-27-0/+3
| | | | | | | | | | | | | | | | | | | | | Enable CONFIG_BLK to move to using driver model for block devices. This affects MMC booting in SPL, as well as MMC access in U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | mailbox: implement a sandbox testStephen Warren2016-05-26-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a sandbox mailbox implementation (provider), a test client device, instantiates them both from Sandbox's DT, and adds a DM test that excercises everything. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> # v1
| * | Rename reset to sysresetStephen Warren2016-05-26-35/+35
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | The current reset API implements a method to reset the entire system. In the near future, I'd like to introduce code that implements the device tree reset bindings; i.e. the equivalent of the Linux kernel's reset API. This controls resets to individual HW blocks or external chips with reset signals. It doesn't make sense to merge the two APIs into one since they have different semantic purposes. Resolve the naming conflict by renaming the existing reset API to sysreset instead, so the new reset API can be called just reset. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2016-05-27-1/+87
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| * | rockchip: rock2: dts: use status = "okay" not okSjoerd Simons2016-05-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | u-boot only recognize okay to enable a node (Linux seems to be more lenient here). So use okay instead. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288-firefly: Add gmac definitionSjoerd Simons2016-05-27-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | Add a definition for the gmac interface to the firefly device-tree. Copied verbatim from the linux kernel. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: grf: Define GRF_SOC_CON1 and GRF_SOC_CON3Sjoerd Simons2016-05-27-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | Add definitions for GRF_SOC_CON1 and GRF_SOC_CON3 which contain various GMAC related fields. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: Add clock support for the gmac ethernet interfaceSjoerd Simons2016-05-27-0/+17
| |/ | | | | | | | | | | | | | | | | Setup the clocks for the gmac ethernet interface. This assumes the mac clock is fed by an external clock which is common on RK3288 based devices. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
* | ARM: OMAP4+: Fix DPLL programming sequenceLokesh Vutla2016-05-27-3/+5
| | | | | | | | | | | | | | | | | | | | All the output clock parameters of a DPLL needs to be programmed before locking the DPLL. But it is being configured after locking the DPLL which could potentially bypass DPLL. So fixing this sequence. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
* | arm64: rename __asm_flush_dcache_level to __asm_dcache_levelMasahiro Yamada2016-05-27-6/+6
| | | | | | | | | | | | | | | | | | Since 1e6ad55c0582 ("armv8/cache: Change cache invalidate and flush function"), this routine can be used for both cache flushing and cache invalidation. So, it is better to not include "flush" in this routine name. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit v1.1 at 2024-11-08 21:06:39 +0000