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* T210: Add support for 64-bit T210-based P2571 boardTom Warren2015-07-28-0/+7
| | | | | | | | | | | Based on Venice2, incorporates Stephen Warren's latest P2571 pinmux table. With Thierry Reding's 64-bit build fixes, this will build and and boot in 64-bit on my P2571 (when used with a 32-bit AVP loader). Signed-off-by: Tom Warren <twarren@nvidia.com>
* P2571: dts: Add DT file for Tegra210 P2571 boardTom Warren2015-07-28-1/+108
| | | | | | Based on T124 Venice2. SDMMC1 is SD-card slot. Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: Tegra210: Add support to common Tegra source/config filesTom Warren2015-07-28-39/+453
| | | | | | | | | | | Derived from Tegra124, modified as appropriate during T210 board bringup. Cleaned up debug statements to conserve string space, too. This also adds misc 64-bit changes from Thierry Reding/Stephen Warren. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: Tegra210: Add SoC code/include files for T210Tom Warren2015-07-28-0/+2933
| | | | | | | | | | | All based off of Tegra124. As a Tegra210 board is brought up, these may change a bit to match the HW more closely, but probably 90% of this is identical to T124. Note that since T210 is a 64-bit build, it has no SPL component, and hence no cpu.c for Tegra210. Signed-off-by: Tom Warren <twarren@nvidia.com>
* Tegra: Rework KConfig options to allow 64-bit builds (T210)Tom Warren2015-07-28-11/+18
| | | | | | | | | | Moved Tegra config options to mach-tegra/Kconfig so that both 32-bit and 64-bit builds can co-exist for Tegra SoCs. T210 will be 64-bit only (no SPL) and will require a 32-bit AVP/BPMP loader. Signed-off-by: Tom Warren <twarren@nvidia.com>
* Tegra210: Fix 64-bit build warning about save_boot_params_ret()Tom Warren2015-07-28-0/+2
| | | | | | | | Simon's 'tegra124: Implement spl_was_boot_source()' needs a prototype for save_boot_params_ret() to build cleanly for 64-bit Tegra210. Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: Initialize timer earlierThierry Reding2015-07-28-6/+6
| | | | | | | | | | | | | A subsequent patch will enable the use of the architected timer on ARMv8. Doing so implies that udelay() will be backed by this timer implementation, and hence the architected timer must be ready when udelay() is first called. The first time udelay() is used is while resetting the debug UART, which happens very early. Make sure that arch_timer_init() is called before that. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: Use standard cache enable for 64-bitThierry Reding2015-07-28-1/+1
| | | | | | | | | On 64-bit SoCs the I-cache isn't enabled in early code, so the default cache enable functions for 64-bit ARM can be used. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: Restrict usable RAM to 32-bit on 64-bit SoCsThierry Reding2015-07-28-0/+16
| | | | | | | | | | | | | | | Most peripherals on Tegra can do DMA only to the lower 32-bit address space, even on 64-bit SoCs. This limitation is typically overcome by the use of an IOMMU. Since the IOMMU is not entirely trivial to set up and serves no other purpose (I/O protection, ...) in U-Boot, restrict 64-bit Tegra SoCs to the lower 32-bit address space for RAM. This ensures that the physical addresses of buffers that are programmed into the various DMA engines are valid and don't alias to lower addresses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* armv8/cache: Fix page table creationThierry Reding2015-07-28-2/+2
| | | | | | | | | | | | | | | | | | | While generating the page tables, a running integer index is shifted by SECTION_SHIFT (29) and causes overflow for any integer bigger than 7. The page tables therefore alias to the same 8 sections and cause U-Boot to hang once the MMU is enabled. Fix this by making the index a 64-bit unsigned integer and so avoid the overflow. swarren notes: currently "i" ranges from 0..8191 on all ARM64 boards, and "j" varies depending on RAM size; from 4 to 11 for a board with 4GB at physical address 2GB, as some Tegra boards have. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm64: Handle arbitrary CONFIG_SYS_MALLOC_F_LEN valuesThierry Reding2015-07-27-1/+2
| | | | | | | | | | | | | | | | The encoding of the sub instruction used to handle CONFIG_SYS_MALLOC_F_LEN can only accept certain values, and the set of acceptable values differs between the AArch32 and AArch64 instructions sets. The default value of CONFIG_SYS_MALLOC_F_LEN works with either ISA. Tegra uses a non-default value that can only be encoded in the AArch32 ISA. Fix the AArch64 crt0 assembly so it can handle completely arbitrary values. Signed-off-by: Thierry Reding <treding@nvidia.com> [twarren: trimmed Thierry's patch to remove changes already present] Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, cleaned up patch, wrote description, re-wrote subject] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: tegra: Build warning fixes for 64-bitThierry Reding2015-07-27-3/+3
| | | | | | | | Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> [swarren, stripped out changes not strictly related to warnings] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* tegra124: Implement spl_was_boot_source()Simon Glass2015-07-27-0/+16
| | | | | | | Add an implementation of this function for Tegra. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-07-25-29/+116
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| * sunxi: ga10h: Enable both otg and regular usb host controllersHans de Goede2015-07-25-0/+26
| | | | | | | | | | | | | | This allows using devices plugged into both ports of the tablet. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: musb: Stop treating not having a vbus-det gpio as an errorHans de Goede2015-07-25-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | On some boards the otg is wired up in host-only mode in this case we have no vbus-det gpio. Stop logging an error from sunxi_usb_phy_vbus_detect() in this case, and stop treating sunxi_usb_phy_vbus_detect() returning a negative errno, as if a charger is plugged into the otg port. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: musb: Use device-model for musb host modeHans de Goede2015-07-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Modify the sunxi musb glue to use the device-model for musb host mode. This allows using musb in host mode together with other host drivers such as ehci / ohci, which is esp. useful on boards which use the musb controller in host-only mode, these boards have e.g. an usb-a receptacle or an usb to sata converter attached to the musb controller. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: musb: Move musb config and platdata to the sunxi-musb glueHans de Goede2015-07-25-0/+7
| | | | | | | | | | | | | | | | | | Move the musb config and platdata to the sunxi-musb glue, which is where it really belongs. This is preparation patch for adding device-model support for the sunxi-musb-host code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: usb-phy: Add support for reading otg id pin valueHans de Goede2015-07-25-0/+35
| | | | | | | | | | | | | | | | Add support for reading the id pin value of the otg connector to the usb phy code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Enable CMD_USB and USB_STORAGE by default on sunxiHans de Goede2015-07-25-0/+2
| | | | | | | | | | | | | | | | | | | | Start using the new Kconfig options which are available for these now, and simply always enable them by selecting them as sunxi builds always include USB support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sunxi: Update selects in arch/arm/Kconfig for DM conversionsTom Rini2015-07-25-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | With certain features being convert to DM now we want sunxi to default to having DM enabled for ETH/SERIAL and USB in some cases. Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Rini <trini@konsulko.com> [hdegoede@redhat.com: Also select CONFIG_USB for all sunxi builds] Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sunxi: Remove bogus uart entry from utoo-p66 dts fileHans de Goede2015-07-25-14/+0
| | | | | | | | | | | | | | | | | | | | | | At one point in time the utoo-p66 dts file in the kernel had a bogus uart entry, and it seems like we synced with the kernel at just the wrong moment. This commit removes the bogus uart entry, which breaks booting the utoo-p66 when DM_SERIAL=y. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: spl: Detect at runtime where SPL was read fromDaniel Kochmański2015-07-24-12/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | Make possible using a single `u-boot-sunxi-with-spl.bin` binary for both NAND memory and SD card. Detection where SPL was read from is implemented in `spl_boot_device`. Signed-off-by: Daniel Kochmański <dkochmanski@turtle-solutions.eu> CC: Roy Spliet <r.spliet@ultimaker.com> Cc: Ian Campbell <ijc@hellion.org.uk> [hdegoede@redhat.com: Some small coding style fixes] Acked-by: Hans De Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Create helper function veryfing valid boot signature on MMCDaniel Kochmański2015-07-24-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch extracts checking for valid SD card "eGON.BT0" signature from `board_mmc_init` into function `sunxi_mmc_has_egon_boot_signature`. Buffer for mmc sector is allocated and freed at runtime. `panic` is triggered on malloc failure. Signed-off-by: Daniel Kochmański <dkochmanski@turtle-solutions.eu> CC: Roy Spliet <r.spliet@ultimaker.com> Cc: Ian Campbell <ijc@hellion.org.uk> [hdegoede@redhat.com: Small bugfix to make it work for devs other then mmc0] Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge git://git.denx.de/u-boot-usbTom Rini2015-07-24-1/+10
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| * | usb: gadget: bcm_udc_otg filesJiandong Zheng2015-07-22-0/+7
| | | | | | | | | | | | | | | | | | | | | Add the required files for the Broadcom UDC OTG interface. Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
| * | usb: Fastboot function config for better consistency with other functionsPaul Kocialkowski2015-07-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB download gadget functions such as thor and dfu have a separate config option for the USB gadget part of the code, independent from the command part. This switches the fastboot USB gadget to the same scheme, for better consistency. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)
| * | include: usb: Move USB controller base address mappingNikhil Badola2015-07-22-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move USB controller Base address mapping from ls102xa immap to fsl xhci header. This is required to remove any warnings when controller base addresses are mapped for multiple platforms in their respective files. Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
| * | arch: arm: fsl: Add XHCI support for LS1021ARamneek Mehresh2015-07-22-0/+11
| | | | | | | | | | | | | | | | | | | | | Add base register address information for USB XHCI controller on LS1021A Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* | | arm: mvebu: Add SPL SDIO/MMC boot supportStefan Roese2015-07-24-1/+12
| |/ |/| | | | | | | | | | | | | | | | | | | | | This patch adds basic SDIO/MMC booting support to MVEBU SoC's. Since I don't know of a way to test the boot-device upon runtime, this patch hardcodes the spl_boot_device instead. Tested on Marvell DB-88F6820-GP board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <eibach@gdsys.de>
* | Merge git://git.denx.de/u-boot-uniphierTom Rini2015-07-23-11/+446
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| * | ARM: dts: UniPhier: add I2C ch4 device node for PH1-sLD3Masahiro Yamada2015-07-23-0/+9
| | | | | | | | | | | | | | | | | | This I2C device is used SoC-internally for controlling the DMD core. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: UniPhier: add PH1-sLD3 SoC supportMasahiro Yamada2015-07-23-10/+436
| | | | | | | | | | | | | | | | | | | | | The init code for UMC (Unified Memory Controller) and PLL has not been mainlined yet, but U-boot proper should work. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: dts: UniPhier: add device-specific compatible string for EEPROMMasahiro Yamada2015-07-23-1/+1
| |/ | | | | | | | | | | | | | | | | | | For the record, describe exactly which device of which vendor is used on this board. I2C EEPROM is bound by the generic compatible string, "i2c-eeprom", so this commit has no impact on the functionality. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge git://git.denx.de/u-boot-marvellTom Rini2015-07-23-3/+5257
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| * | arm: mvebu: a38x: Use correct PEX register access macrosStefan Roese2015-07-23-0/+4
| | | | | | | | | | | | | | | | | | | | | Remove the incorrect PEX macros from the DDR header. And insert the correct ones in ctrl_pex.h instead. Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: drivers/ddr: Move Armada XP DDR init code into new directoryStefan Roese2015-07-23-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the upcoming addition of the Armada 38x DDR support, which is not compatible to the Armada XP DDR init code, we need to introduce a new directory infrastructure. To support multiple Marvell DDR controller. This will be the new structure: drivers/ddr/marvell/axp Supporting Armada XP (AXP) devices (and perhaps Armada 370) drivers/ddr/marvell/a38x Supporting Armada 38x devices (and perhaps Armada 39x) Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: Add Armada 38x SERDES / PHY init code from Marvell bin_hdrStefan Roese2015-07-23-0/+5204
| | | | | | | | | | | | | | | | | | | | | | | | This code is ported from the Marvell bin_hdr code into mainline SPL U-Boot. It needs to be executed very early so that the devices connected to the serdes PHY are configured correctly. Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: serdes: Move Armada XP SERDES / PHY init code into new directoryStefan Roese2015-07-23-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | With the upcoming addition of the Armada 38x SPL support, which is not compatible to the Armada XP SERDES init code, we need to introduce a new directory infrastructure. So lets move the AXP serdes init code into a new directory. This way the A38x code can be added in a clean way. Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: Disable MMU before changing register base addressStefan Roese2015-07-23-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | Only with disabled MMU its possible to switch the base register address on Armada 38x. Without this the SDRAM located at >= 0x4000.0000 is also not accessible, as its still locked to cache. Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: spl.c: Add call to board_early_init_f()Stefan Roese2015-07-23-0/+7
| | | | | | | | | | | | | | | | | | | | | Pin muxing needs to be done before UART output, since on A38x the UART pins need some re-muxing for output to work. Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: Use default reg base address for SPL on A38xStefan Roese2015-07-23-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | On A38x switching the regs base address without running from SDRAM doesn't seem to work. So let the SPL still use the default base address and switch to the new address in the mail u-boot later. Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: Call timer_init early before PHY and DDR initStefan Roese2015-07-23-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without calling timer_init(), the xdelay() functions return immediately. We need to call timer_init() early, so that these functions work and the PHY and DDR init code works correctly. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Anton Schubert <anton.schubert@gmx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: add Armada XP SATA supportAnton Schubert2015-07-23-0/+1
| |/ | | | | | | | | | | | | | | | | | | This patch initializes the SATA address windows on Armada XP and allows it to work with the existing mvsata_ide driver. It also adds the necessary configuration for the db-mv784mp-gp board. Signed-off-by: Anton Schubert <anton.schubert@gmx.de> Tested-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | x86: delete unneeded declarations of disable_irq() and enable_irq()Masahiro Yamada2015-07-22-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | These two declarations in arch/x86/include/asm/interrupt.h conflict with ones in include/linux/compat.h, so x86 boards cannot include <linux/compat.h>. The comment /* arch/x86/lib/interrupts.c */ is bogus now, and we do not see any definitions of disable_irq() and enable_irq() in there. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | dm: test: Add a size to each reg propertySimon Glass2015-07-21-12/+15
| | | | | | | | | | | | | | | | Each sandbox peripheral should have a size as well as a base address. This is required for regmaps to work, so make this change for all nodes that have an address. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: test: Add a test for the system controller uclassSimon Glass2015-07-21-0/+18
| | | | | | | | | | | | | | Add a test to confirm that we can access system controllers and find their driver data. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: test: Add a test for the LED uclassSimon Glass2015-07-21-0/+14
| | | | | | | | | | | | Add a test to confirm that we can adjust LEDs using the led_gpio driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: test: Add a test for the mmc uclassSimon Glass2015-07-21-0/+4
| | | | | | | | | | | | | | Add a test to confirm that we can probe this device. Since there is no MMC stack support in sandbox at present, this is as far as the test goes. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: test: Add a test for the ram uclassSimon Glass2015-07-21-0/+4
| | | | | | | | | | | | | | Add a test to confirm that we can probe this device and get information on the available RAM. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-10-10 07:29:43 +0000