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| * | | ARM64: zynqmp: Add support for DFU from SPLMichal Simek2016-09-22-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPL needs to have bigger stack size because of USB. Simple malloc needs to be disabled because dfu code requires different allocation functions. There is no space in OCM that's why random place in DDR is used. BOOTD must be disabled because it is causing compilation error. All variables are disabled and used only variables valid for DFU because they are simple huge. Including automatic variables added by CONFIG_ENV_VARS_UBOOT_CONFIG. Hardcode addresses for u-boot, atf, kernel and dtb just for SPL DFU code. Enable SPL DFU for zcu100. Create new usb_dfu_spl variable just to run Linux kernel loaded in SPL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: Add new BOOT_DEVICE_DFU boot modeMichal Simek2016-09-22-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This enum is needed when SPL_DFU is enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Add USB boot modeMichal Simek2016-09-22-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add USB boot mode. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM64: zynqmp: Force certain bootmode for SPLMichal Simek2016-09-22-0/+57
| |/ / | | | | | | | | | | | | | | | | | | | | | ZynqMP provides an option to overwrite bootmode setting which can change SPL behavior. For example: boot SPL via JTAG and then SPL loads images from SD. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2016-09-21-74/+904
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| * | MIPS: Hang if run on a secondary CPUPaul Burton2016-09-21-1/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some systems are configured such that multiple CPUs begin running from their reset vector following a system reset. If this occurs then U-Boot will be run on multiple CPUs simultaneously, which causes all sorts of issues as the multiple instances of U-Boot clobber each other. Prevent this from happening by simply hanging with an infinite loop if we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum as appropriate, is non-zero. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: Fix cache maintenance in relocate_code & simplifyPaul Burton2016-09-21-26/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The relocate_code function was handling cache maintenance incorrectly. It copied U-Boot to its new location, flushed the caches & then proceeded to apply relocations & jump to the new code without flushing the caches again. This is problematic as the instruction cache could potentially have already fetched instructions that hadn't had relocs applied. Rework this to perform the flush_cache call using the code in the original copy of U-Boot, after having applied relocations to the new copy of U-Boot. The new U-Boot can then be jumped to safely once that cache flush has been performed. As part of this, since the old U-Boot is used up until after that cache flush, complexity around loading values from the GOT using a jump & link instruction & loads from a table is removed. Instead we can simply load the needed values with PTR_LA fromt the original GOT. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | boston: Introduce support for the MIPS Boston development boardPaul Burton2016-09-21-0/+241
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces support for building U-Boot to run on the MIPS Boston development board. This is a board built around an FPGA & an Intel EG20T Platform Controller Hub, used largely as part of the development of new CPUs and their software support. It is essentially the successor to the older MIPS Malta board. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: Ensure cache ops complete in mips_cache_resetPaul Burton2016-09-21-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure that cache operations complete before returning from mips_cache_reset by placing a completion barrier (sync instruction) before the return. Without this there is no guarantee that the cache ops will complete before any subsequent memory accesses, since they are indexed cache ops & thus not implicitly ordered with memory accesses. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: Clear hazard between TagLo writes & cache opsPaul Burton2016-09-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Writing to the coprocessor 0 TagLo registers introduces an execution hazard in that we need that write to complete before any cache instructions execute. Ensure that hazard is cleared by inserting an ehb instruction between the TagLo writes & cache op loop. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: Ensure Config.K0=2 applies before any memory accessesPaul Burton2016-09-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During boot we set Config.K0=2 (uncached) such that any accesses to the kseg0 memory region are performed uncached before the caches are initialised. This write to the Config register introduces an execution hazard between it & any following memory accesses (such as the load of _gp), which we need to clear in order to ensure those memory accesses are actually performed uncached. Clear this execution hazard with the insertion of an ehb execution hazard barrier instruction. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: Malta: Enable CM & L2 supportPaul Burton2016-09-21-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable support for the MIPS Coherence Manager & L2 caches on the MIPS Malta board, removing the need for us to attempt to bypass the L2 during boot (which would fail with recent CPUs that expose L2 config via the CM anyway). Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: Join the coherent domain when a CM is presentPaul Burton2016-09-21-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS Linux expects the bootloader to leave the boot CPU a member of the coherent domain when running on a system with a CM, and we will need to do so if we wish to make use of IOCUs to have cache-coherent DMA in U-Boot (and on some systems there is no choice in that matter). When a CM is present, join the coherent domain after completing cache initialisation. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: L2 cache supportPaul Burton2016-09-21-6/+291
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for initialising & maintaining L2 caches on MIPS systems. The L2 cache configuration may be advertised through either coprocessor 0 or the MIPS Coherence Manager depending upon the system, and support for both is included. If the L2 can be bypassed then we bypass it early in boot & initialise the L1 caches first, such that we can start making use of the L1 instruction cache as early as possible. Otherwise we initialise the L2 first such that the L1s have no opportunity to generate access to the uninitialised L2. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: Map CM Global Control RegistersPaul Burton2016-09-21-0/+88
| | | | | | | | | | | | | | | | | | | | | Map the Global Control Registers (GCRs) provided by the MIPS Coherence Manager (CM) in preparation for using some of them in later patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: Define register names for cache initPaul Burton2016-09-21-19/+23
| | | | | | | | | | | | | | | | | | | | | | | | Define names for registers holding cache sizes throughout mips_cache_reset, in order to make the code easier to read & allow for changing register assignments more easily. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: If we don't need DDR for cache init, init cache firstPaul Burton2016-09-21-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On systems where cache initialisation doesn't require zeroed memory (ie. systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined) perform cache initialisation prior to lowlevel_init & DDR initialisation. This allows for DDR initialisation code to run cached & thus significantly faster. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: Preserve Config implementation-defined bitsPaul Burton2016-09-21-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The coprocessor 0 Config register includes 9 implementation defined bits, which in some processors do things like enable write combining or other functionality. We ought not to wipe them to 0 during boot. Rather than doing so, preserve their value & only clear the bits standardised by the MIPS architecture. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: Enable use of the instruction cache earlierPaul Burton2016-09-21-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable use of the instruction cache immediately after it has been initialised. This will only take effect if U-Boot was linked to run from kseg0 rather than kseg1, but when this is the case the data cache initialisation code will run cached & thus significantly faster. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: Probe cache line sizes once during bootPaul Burton2016-09-21-18/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than probing the cache line sizes on every call of any cache maintenance function, probe them once during boot & store the values in the global data structure for later use. This will reduce the overhead of the cache maintenance functions, which isn't a big deal yet but becomes more important once L2 caches which may expose their properties via coprocessor 2 or the CM are supported. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | MIPS: ath79: Use mach_cpu_init instead of arch_cpu_initPaul Burton2016-09-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | In order to prepare for MIPS arch code making use of arch_cpu_init in a later patch, stop using it from ath79 SoC code & instead use the new mach_cpu_init which is provided for this purpose. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | mips: Add MIPSfpga platform supportZubair Lutfullah Kakakhel2016-09-21-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPSfpga is an FPGA based dev platform. In a nutshell, its a microAptiv cpu core with lots of Xilinx IP blocks The FPGA dev board used is the Nexys4DDR board by Digilent. For more information, check the Readme file in board/imgtec/xilfpga Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | mips: xilfpga: Add device tree filesZubair Lutfullah Kakakhel2016-09-21-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mostly the same as the Kernel upstream device tree file except for - alias for the serial console node - ethernet node as the ethernet stuff isn't upstream on kernel.org yet - uart clock-frequency passed directly in the node Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | PowerPC: Update MIP405/MIP405T to use Kconfig betterTom Rini2016-09-20-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert CONFIG_MIP405T from SYS_EXTRA_OPTIONS to a real config There are two boards, MIP405 and MIP405T that have a few differences. Start by checking for CONFIG_TARGET_MIP405. Then introduce CONFIG_TARGET_MIP405T and use that not CONFIG_MIP405T. Next, convert also convert the usage of CONFIG_ISO_STRING to be based on Kconfig. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | Kconfig: Move config IDENT_STRING to KconfigSiva Durga Prasad Paladugu2016-09-20-34/+0
|/ / | | | | | | | | | | | | | | | | Move the config IDENT_STRING to Kconfig and migrate all boards [sivadur: Migrate zynq boards] Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> [trini: Update configs, add some default to sunxi Kconfig] Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-09-18-1025/+1148
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| * | ARM: uniphier: update DRAM init code for LD20 SoCMasahiro Yamada2016-09-19-62/+447
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import the latest version from the Diag software. - Support LD21 SoC (including DDR chips in the package) - Per-board granule adjustment for both reference and TV boards - Misc cleanups Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: add PLL init code for LD20 SoCMasahiro Yamada2016-09-19-5/+234
| | | | | | | | | | | | | | | | | | | | | | | | Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot proper. Split the common code into pll-base-ld20.c for easier re-use. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: collect clock/PLL init code into a single directoryMasahiro Yamada2016-09-19-24/+18
| | | | | | | | | | | | | | | | | | | | | | | | Now PLLs for DRAM controller are initialized in SPL, and the others in U-Boot proper. Setting up all of them in a single directory will be helpful when we want to share code between SPL and U-Boot proper. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: move PLL init code to U-Boot proper where possibleMasahiro Yamada2016-09-19-495/+365
| | | | | | | | | | | | | | | | | | | | | | | | The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: rename CONFIG_DPLL_SSC_RATE_1PERMasahiro Yamada2016-09-18-1/+1
| | | | | | | | | | | | | | | | | | Basically, this should not be configured by users. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: move XIRQ pin-mux settings of LD11/LD20Masahiro Yamada2016-09-18-31/+10
| | | | | | | | | | | | | | | | | | | | | This is the last code in the mach-uniphier/pinctrl/ directory. Push the remaining code out to delete the directory entirely. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: consolidate System Bus pin-mux settings for LD11/LD20Masahiro Yamada2016-09-18-44/+5
| | | | | | | | | | | | | | | | | | | | | Use the pin-mux data in the pinctrl drivers by directly calling pinctrl_generic_set_state(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: dts: uniphier: include System Bus pin group node in SPL DTMasahiro Yamada2016-09-18-0/+8
| | | | | | | | | | | | | | | | | | | | | This will be needed for setting up the System Bus pin-mux via the LD11/LD20 pinctrl driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: consolidate NAND pin-mux settingsMasahiro Yamada2016-09-18-274/+51
| | | | | | | | | | | | | | | | | | | | | | | | The NAND subsystem has not supported the Driver Model yet, but the NAND pin-mux data are already in the pinctrl drivers. Use them by calling pinctrl_generic_set_state() directly. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: remove ad-hoc pin-mux code for sLD3Masahiro Yamada2016-09-18-58/+0
| | | | | | | | | | | | | | | | | | These settings are nicely cared by the pinctrl driver now. Remove. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: remove redundant pin-muxing for EA24 pin of sLD3 SoCMasahiro Yamada2016-09-18-2/+0
| | | | | | | | | | | | | | | | | | This is enabled by default for all the supported boot modes. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: select PINCTRL and SPL_PINCTRLMasahiro Yamada2016-09-18-0/+2
| | | | | | | | | | | | | | | | | | | | | Now all UniPhier SoCs support a pinctrl driver. Select (SPL_)PINCTRL since it is mandatory even for base use. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: dts: uniphier: add pinctrl device node and pinctrl propertiesMasahiro Yamada2016-09-18-0/+43
| | | | | | | | | | | | | | | | | | DT-side updates to make pinctrl on sLD3 SoC really available. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: introduce flags to adjust DRAM timing for LD20/LD21Masahiro Yamada2016-09-17-4/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately, this SoC needs per-board adjustment between clock and address/command lines. This flag will be passed to the DRAM init function and used for compensating the difference of DRAM timing parameters. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: fix DRAM size of LD21 SoC packageMasahiro Yamada2016-09-17-1/+1
| | | | | | | | | | | | | | | | | | The channel 0 DRAM size of LD21 is half of that of LD20. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: merge board init functions into board_init()Masahiro Yamada2016-09-14-40/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the UniPhier platform calls several init functions in the following order: [1] spl_board_init() [2] board_early_init_f() [3] board_init() [4] board_early_init_r() [5] board_late_init() The serial console is not ready at the point of [2], so we want to avoid using [2] from the view point of debuggability. Fortunately, all of the initialization in [2] can be delayed until [3]. I see no good reason to split into [3] and [4]. So, merge [2] through [4]. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: use checkboard() instead of misc_init_f()Masahiro Yamada2016-09-14-24/+7
| | | | | | | | | | | | | | | | | | | | | We can use checkboard() stub to show additional board information, so misc_init_f() should not be used for this purpose. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: remove IECTRL setup code of LD4 SoCMasahiro Yamada2016-09-14-6/+0
| | | | | | | | | | | | | | | | | | This should be handled by the pinctrl driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | mmc: uniphier-sd: migrate to CONFIG_BLKMasahiro Yamada2016-09-14-0/+1
| | | | | | | | | | | | | | | | | | | | | This is the state-of-the-art MMC driver implementation. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | ARM: uniphier: delete unnecessary xHCI pin-mux settingsMasahiro Yamada2016-09-14-48/+0
| | | | | | | | | | | | | | | | | | | | | These ad-hoc pinmux settings were used for the legacy xHCI driver, which has gone now. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | usb: uniphier: remove UniPhier xHCI driver and select DM_USBMasahiro Yamada2016-09-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver has not been converted to Driver Model, and it is an obstacle to migrate other block device drivers. Remove it for now. The UniPhier SoCs already use a DM-based EHCI driver, so now ARCH_UNIPHIER can select DM_USB. These two changes must be done atomically because removing the legacy driver causes a build error. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
| * | ARM: uniphier: sort select:s alphabeticallyMasahiro Yamada2016-09-14-7/+7
| |/ | | | | | | | | | | | | ARCH_UNIPHIER is having more and more select:s. Sort them in case a select is accidentally duplicated. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-sunxiTom Rini2016-09-18-9/+127
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| * | sunxi: Add defconfig and dts for the NanoPi NEOJelle van der Waa2016-09-18-1/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | The NanoPi NEO is a simple h3 board with 512MB RAM, ethernet, one usb and one usb OTG connector. Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
generated by cgit v1.1 at 2024-11-08 14:55:07 +0000