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* | arm: mvebu: Setup the MBUS bridge registersStefan Roese2015-08-17-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With this patch, the MBUS bridge registers (base and size) are configured upon each call to mbus_dt_setup_win(). This is needed, since the board code can also call this function in later boot stages. As done in the maxbcm board. This is needed to fix a problem with the secondary CPU's not booting in Linux on AXP. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peter Morrow <peter@senient.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | arm: mvebu: Change MBUS base addresses and sizesStefan Roese2015-08-17-10/+16
| | | | | | | | | | | | | | | | | | This patch changes the MBUS base addresses and sizes to use more generic names and also adds defines for the sizes. It also moves the base address to higher addresses. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | arm: mvebu/armada100: dram.c: Remove CONFIG_SYS_BOARD_DRAM_INITStefan Roese2015-08-17-4/+0
| | | | | | | | | | | | | | | | CONFIG_SYS_BOARD_DRAM_INIT is not defined anywhere. So lets get rid of all references here. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | arm: lpc32xx: gpio macro for pin mappingSylvain Lemieux2015-08-17-0/+40
| | | | | | | | | | | | Add LPC32xx GPIO interface macro for pin mapping. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* | lpc32xx: cpu: add support for soft resetSylvain Lemieux2015-08-17-6/+17
| | | | | | | | | | | | | | | | Add support for optional soft reset (i.e. "RESOUT_N" not asserted during reset). To be compatible with the original U-Boot code, when the "addr" parameter is 0, a hard is performed; for any other values, a soft reset is done. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* | arm: lpc32xx: mux: add missing registersSylvain Lemieux2015-08-17-1/+18
|/ | | | | | | Add missing registers in struct definition. Update GPIO MUX base register to match GPIO base (refer to "LPC32x0 User manual" Rev. 3 - 22 July 2011). Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-08-14-189/+386
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| * x86: minnowmax: Define and enable interrupt setupSimon Glass2015-08-14-3/+66
| | | | | | | | | | | | | | | | Set up interrupts correctly so that Linux can use all devices. Use savedefconfig to regenerate the defconfig file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Return -1 when reading a PCI config register failsSimon Glass2015-08-14-3/+6
| | | | | | | | | | | | | | | | This can fail for internal reasons, so return a sensible value rather than a random one. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Drop FSP error defines and use EFI insteadSimon Glass2015-08-14-12/+1
| | | | | | | | | | | | | | | | Now that we have an efi.h header we can use that for FSP error defines. Drop the FSP ones. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Set APs' req_seq to the reg number from device treeBin Meng2015-08-14-0/+7
| | | | | | | | | | | | | | | | | | Multiple APs are brought up simultaneously and they may get the same seq num in the uclass_resolve_seq() during device_probe(). To avoid this, set req_seq to the reg number in the device tree in advance. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Show the un-relocated IP address in exceptionsSimon Glass2015-08-14-0/+2
| | | | | | | | | | | | | | | | | | | | When trying to figure out where an exception has occured, the relocated address is not a lot of help. Its value depends on various factors. Show the un-relocated IP as well. This can be looked up in System.map directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Switch to using generic global_data setupSimon Glass2015-08-14-83/+16
| | | | | | | | | | | | | | | | | | | | | | There is quite a bit of assembler code that can be removed if we use the generic global_data setup. Less arch-specific code makes it easier to add new features and maintain the start-up code. Drop the unneeded code and adjust the hooks in board_f.c to cope. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Move the GDT into global_dataSimon Glass2015-08-14-5/+8
| | | | | | | | | | | | | | | | | | Rather than keeping track of the Global Descriptor Table in its own memory we may as well put it in global_data with everything else. As a first step, stop using the separately allocated GDT. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Remove init_gd() functionSimon Glass2015-08-14-1/+0
| | | | | | | | | | | | | | This is declared but no-longer exists. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: baytrail: Support running as an EFI payloadSimon Glass2015-08-14-0/+2
| | | | | | | | | | | | | | | | We should not fiddle with interrupts or the FSP when running as an EFI payload. Detect this and skip this code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: baytrail: Tidy up interrupt and FSP initSimon Glass2015-08-14-1/+8
| | | | | | | | | | | | | | | | We should signal to the FSP that PCI enumeration is complete. Perform this task in a suitable place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Allow pirq_init() to return an errorSimon Glass2015-08-14-19/+18
| | | | | | | | | | | | | | | | This function can fail. In this case we should return the error rather than swallowing it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Split out fsp_init_phase_pci() code into a new functionSimon Glass2015-08-14-3/+15
| | | | | | | | | | | | | | | | | | | | | | This code may be useful for boards that use driver model for PCI. Note: It would be better to have driver model automatically call this function somehow. However for now it is probably safer to have it under board control. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Tidy up the PIRQ routing code a littleSimon Glass2015-08-14-28/+13
| | | | | | | | | | | | | | | | | | This code could use a little tightening up. There is some repetition and an odd use of fdtdec_get_int_array(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: fsp: Do not assert VPD_IMAGE_REV when DEBUGBin Meng2015-08-14-4/+1
| | | | | | | | | | | | | | | | | | | | When using different release version of Intel FSP, the VPD_IMAGE_REV is different (ie: BayTrail Gold 3 is 0x0303 while Gold 4 is 0x0304). Remove the asserting of this so that U-Boot does not hang in a debug build. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: baytrail: Configure FSP UPD from device treeAndrew Bradford2015-08-14-30/+226
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself. Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used. Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Removed fsp,mrc-debug-msg and fsp,enable-xhci for minnowmax, bayleybay Fixed lines >80col Signed-off-by: Simon Glass <sjg@chromium.org>
* | sun6i: clock: Add support for the mipi pllHans de Goede2015-08-14-0/+70
| | | | | | | | | | | | | | | | Add support for the mipi pll, this is necessary for getting higher dotclocks with lcd panels. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: clock: Add clock_get_pll3() helper functionHans de Goede2015-08-14-0/+29
| | | | | | | | | | | | | | Add a helper function to get the pll3 clock rate. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Fix gmac not working on the Colombus boardHans de Goede2015-08-14-0/+12
| | | | | | | | | | | | | | | | | | The phy is using a RGMII interface, which we need to specify in our board-config, and the dts needs a gmac section (the dts changes have also been submitted to the kernel). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Add support for the Auxtek-T003 HDMI stickHans de Goede2015-08-14-0/+160
| | | | | | | | | | | | | | | | The Auxtek-T003 HDMI stick is an A10s based HDMI stick with USB wifi, and composite video out support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: dts: Sync with kernelHans de Goede2015-08-14-39/+910
| | | | | | | | | | | | | | | | Sync the sunxi dts files with the changes queued up for kernel-4.3 in mripard's sunxi/dt-for-4.3 branch. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: display: Fix composite video out on sun5iHans de Goede2015-08-14-1/+16
|/ | | | | | | | The tv-encoder on sun5i is slightly different compared to the one on sun4i/sun7i. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: tegra: represent RAM in 1 or 2 banksStephen Warren2015-08-13-14/+106
| | | | | | | | | | | | | | | | | | | | | Represent all available RAM in either one or two banks. The first bank describes any RAM below 4GB. The second bank describes any RAM above 4GB. This split is driven by the following requirements: - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg property for memory below and above the 4GB boundary. The layout of that DT property is directly driven by the entries in the U-Boot bank array. - On systems with RAM beyond a physical address of 4GB, the potential existence of a carve-out at the end of RAM below 4GB can only be represented using multiple banks, since usable RAM is not contiguous. While making this change, add a lot more comments re: how and why RAM is represented in banks, and implement a few more "semantic" functions that define (and perhaps later detect at run-time) the size of any carve-out. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: query_sdram_size() cleanupStephen Warren2015-08-13-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The return value of query_sdram_size() is assigned directly to gd->ram_size in dram_init(). Adjust the return type to match the field it's assigned to. This has the beneficial effect that on 64-bit systems, the return value can correctly represent large RAM sizes over 4GB. For similar reasons, change the type of variable size_bytes in the same way. query_sdram_size() would previously clip the detected RAM size to at most just under 4GB in all cases, since on 32-bit systems, larger values could not be represented. Disable this feature on 64-bit systems since the representation restriction does not exist. On 64-bit systems, never call get_ram_size() to validate the detected/ calculated RAM size. On any system with a secure OS/... carve-out, RAM may not have a single contiguous usable area, and this can confuse get_ram_size(). Ideally, we'd make this call conditional upon some other flag that indicates specifically that a carve-out is actually in use. At present, building for a 64-bit system is the best indication we have of this fact. In fact, the call to get_ram_size() is not useful by the time U-Boot runs on any system, since U-Boot (and potentially much other early boot software) always runs from RAM on Tegra, so any mistakes in memory controller register programming will already have manifested themselves and prevented U-Boot from running to this point. In the future, we may simply delete the call to get_ram_size() in all cases. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Correct logic for reading pll_misc in clock_start_pll()Simon Glass2015-08-13-13/+31
| | | | | | | | | | | | The logic for simple PLLs on T124 was broken by this commit: 722e000c Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. Correct it by reading from the same pll_misc register that it writes to and adding an entry for the DP PLL in the pllinfo table. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: Make pinmux.h standalone includibleThierry Reding2015-08-13-0/+2
| | | | | | | | | | | This header file uses type definitions (u8, u32) from linux/types.h but doesn't include it. If includes aren't carefully ordered this can cause build failures. Cc: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* apalis/colibri_t30: fix usb dm regressionMarcel Ziswiler2015-08-13-2/+2
| | | | | | | | | | | | | | | | Unfortunately currently both Apalis T30 as well as Colibri T30 crash upon starting USB host support. This is due to the following patch not having taken into account that our T30 device trees were defaulting to peripheral only mode instead of otg: commit ddb9a502d18008e845d5a8fa03ec48630fa77fb7 dm: usb: tegra: Move most of init/uninit into a function This patch fixes this by defaulting to otg now. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* apalis/colibri_t20/30: clean-upMarcel Ziswiler2015-08-13-2/+4
| | | | | | | | | | | | | | | Various clean-ups either in comments, order or spacing without any functional impact: - Add some comments in the device trees resp. reorder some parameters for consistency across all our modules. - Sort some include files alphabetically (while leaving common.h on top of course). - Streamline some comments in the configuration files and fix the spacing from using spaces to tabs. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* colibri_t20: add i2c supportMarcel Ziswiler2015-08-13-0/+28
| | | | | | | | | | Add I2C support in order to subsequently allow disabling the PMIC sleep mode on low supply voltage. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* colibri_t20: add lcd display supportMarcel Ziswiler2015-08-13-0/+29
| | | | | | | | | | Add LCD display support defaulting to VESA VGA resolution. Different resolutions configurable via device tree. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* colibri_t20: fix device-tree compatible nodeMarcel Ziswiler2015-08-13-1/+1
| | | | | | | | | | Use toradex,colibri_t20 as the device-tree compatible node value rather than toradex,t20 in accordance to our Apalis/Colibri T30 products. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: allow reading recovery mode boot typeMarcel Ziswiler2015-08-13-0/+2
| | | | | | | | | | Add defines to allow reading recovery mode (RCM) boot type from the boot information table (BIT) written by the boot ROM (BR) to the IRAM. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2015-08-13-1/+6
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| * net: lpc32xx: add RMII phy mode supportVladimir Zapolskiy2015-08-11-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LPC32xx MAC and clock control configuration requires some minor quirks to deal with a phy connected by RMII. It's worth to mention that the kernel and legacy BSP from NXP sets SUPP_RESET_RMII == (1 << 11) bit, however the description of this bit is missing in shared LPC32x0 User Manual UM10326 Rev. 3, July 22, 2011 and in LPC32x0 Draft User Mannual Rev. 00.27, November 20, 2008, also in my tests an SMSC LAN8700 phy device connected over RMII seems to work correctly without touching this bit. Add support of RMII, if CONFIG_RMII is defined, this option is aligned with a number of boards, which already define the same config value. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* | ARM: drop "optional" from target select in favor of ARCH_VERSATILEMasahiro Yamada2015-08-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit a26cd04920dc ("arch: Make board selection choices optional"), Kconfig could create such an insane .config file that no SoC/board is selected. This is now a real problem for Buildroot, for example. (http://lists.busybox.net/pipermail/buildroot/2015-July/135125.html) This commit drops the "optional" from the ARM target select menu in favor of "Versatile family". Rationale: - Historically, Linux chose versatile_defconfig as the default of ARM defconfig. (arch/arm/Makefile of Linux describes: KBUILD_DEFCONFIG := versatile_defconfig) - It was published by ARM Ltd. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | dra7xx: Add dra72_evm_defconfig using CONFIG_DMTom Rini2015-08-12-0/+4506
| | | | | | | | | | | | | | | | | | | | - Import various DT files for DRA7 / DR72x / dra72-evm from Linux Kernel v4.1 - Add config file for this board, enable DM and DM_GPIO Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | ARM: SPL: Use CONFIG_SPL_DM not CONFIG_DMTom Rini2015-08-12-3/+3
| | | | | | | | | | | | | | | | | | We now have the CONFIG_SPL_DM for code within SPL to toggle caring about DM or not. Without this change platforms that do enable CONFIG_DM but not CONFIG_SPL_DM may be broken (such as OMAP5). Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Tom Rini <trini@konsulko.com>
* | gpio: omap: Drop 'method' parameterTom Rini2015-08-12-38/+35
| | | | | | | | | | | | | | | | | | | | The "method" parameter was part of the original port of the driver from the kernel. At some point this may have been added to allow for future differentiation (as omap1 and omap2 have different GPIO IP blocks, so this wasn't an unreasonable thing to do). At this point however it's just extra overhead, so drop. Signed-off-by: Tom Rini <trini@konsulko.com>
* | am33xx: Update DT files, add am335x_gp_evm_config targetTom Rini2015-08-12-206/+2142
| | | | | | | | | | | | | | | | | | | | - Re-sync DT files for am33xx with Linux Kernel v4.1 - Include DT file now for the "AM335x GP EVM" and build target for it, via device tree and DM. - We only need to provide platform data for UART when OF_CONTROL isn't also enabled really. We can just push GPIO to coming from DT Signed-off-by: Tom Rini <trini@konsulko.com>
* | arm: am437x: Introduce new board cm-t43Nikita Kiryanov2015-08-12-0/+6
| | | | | | | | | | | | | | | | | | | | | | Add initial support for CM-T43, an AM437x based SoM. This support includes: serial, MMC/eMMC, NAND, USB, ETH, I2C, GPIO, DRAM detection. Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* | gpio: am43xx: expand gpio supportNikita Kiryanov2015-08-12-0/+4
| | | | | | | | | | | | | | | | | | AM43XX SoCs support up to 192 GPIO signals. Make this amount available to the driver. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* | arm: am43xx: enable spi clockNikita Kiryanov2015-08-12-0/+1
| | | | | | | | | | | | | | | | | | | | Add spi clock to the list of am43xx basic clocks to make the SPI subsystem available on am43xx systems. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | ARM64: hikey: hi6220: Add u-boot support for the 96boards CE HiKey board.Peter Griffin2015-08-12-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HiKey is the first 96boards consumer edition compliant board. It features a hi6220 SoC which has eight ARM A53 cpu's. This initial port adds support for: - 1) Serial 2) eMMC / SD card 3) USB 4) GPIO It has been tested with Arm Trusted Firmware running u-boot as the BL33 executable. Notes: eMMC has been tested with basic reading of eMMC partition into DDR. I have not tested writing / erasing. Due to lack of clock control it won't be running in the most performant high speed mode. SD card slot has been tested for reading and booting kernels into DDR. It is also currently configured to save the u-boot environment to the SD card. USB has been tested with ASIX networking adapter to tftpboot kernels into DDR. On v2015.07-rc2 dhcp now works, and also USB mass storage are correctly enumerated. GPIO has been tested using gpio toggle GPIO4_1-3 to flash the LEDs. Basic SoC datasheet can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf Board schematic can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ 96Boards-Hikey-Rev-A1.pdf Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
* | mmc: hi6220_dw_mmc: Add hi6220 glue code for dw_mmc controller.Peter Griffin2015-08-12-0/+8
| | | | | | | | | | | | | | | | | | This patch adds the glue code for hi6220 SoC which has 2x synopsis dw_mmc controllers. This will be used by the hikey board support in subsequent patches. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
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