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* powerpc/usb:Differentiate USB controller base addressramneek mehresh2013-10-24-14/+21
| | | | | | | | Introduce different macros for storing addresses of multiple USB controllers. This is required for successful initialization and usage of multiple USB controllers inside u-boot Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* powerpc/usb:Define CONFIG_USB_MAX_CONTROLLER_COUNT for all 85xx socsramneek mehresh2013-10-24-3/+29
| | | | | | | | CONFIG_USB_MAX_CONTROLLER_COUNT macro recently defined for initializing all USB controllers on a given platform. This macro is defined for all 85xx socs Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2013-10-22-10/+9
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| * sh: cache: Change cache API to defines as U-BootNobuhiro Iwamatsu2013-10-17-6/+3
| | | | | | | | | | | | | | | | | | A chache API of SH is developped by reference in linux kernel. And API was the same as the linux kernel. This patch change cache API to defines as U-Boot. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: timer: Remove static global variableNobuhiro Iwamatsu2013-10-17-4/+4
| | | | | | | | | | | | | | | | "static u16 bit" is not necessary to use this as static global variable. This patch fixes this. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * sh: timer: Mask bit of timer prescalerNobuhiro Iwamatsu2013-10-17-1/+3
| | | | | | | | | | | | | | | | | | timer_init function sets timer prescaler bit. The previous code so did not mask this bit, this function was to overwrite the bit. This will fix this problem. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2013-10-21-10/+184
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| * | usb: add enum usb_init_type parameter to usb_lowlevel_initTroy Kisky2013-10-20-4/+4
| | | | | | | | | | | | | | | | | | This parameter will later be used to verify OTG ports. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * | usb: am437x: Add support for am437x xhci USB hostDan Murphy2013-10-20-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the support for the am437x xhci usb host. The xHCI host on AM437 is connected to a usb2 phy so need to add support to enable those clocks. Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | usb: dra7xx: Add support for dra7xx xhci USB hostDan Murphy2013-10-20-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the support for the dra7xx xhci usb host. dra7xx does not contain an EHCI controller so the headers can be removed from the board file. The xHCI host on dra7xx is connected to a usb2 phy so need to add support to enable those clocks. Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | usb: omap: Move the xhci-omap header file to common locationDan Murphy2013-10-20-124/+0
| | | | | | | | | | | | | | | | | | | | | Moving the xhci-omap header to a more global location so that other code can reference this code. Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | usb: new board-specific USB init interfaceMateusz Zalega2013-10-20-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit unifies board-specific USB initialization implementations under one symbol (usb_board_init), declaration of which is available in usb.h. New API allows selective initialization of USB controllers whenever needed. Signed-off-by: Mateusz Zalega <m.zalega@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Lukasz Majewski <l.majewski@samsung.com>
| * | mx6: iomux: add GPR1 defines for use with nitrogen6xTroy Kisky2013-10-20-0/+6
| | | | | | | | | | | | | | | | | | Select GPIO1 as the USB OTG ID pin for Nitrogen6x Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * | OMAP5: USB: Add OMAP xHCI file and headerDan Murphy2013-10-20-0/+124
| | | | | | | | | | | | | | | | | | | | | | | | Add the OMAP file for the xHCI Host controller This code will initilialize the proper components within the OMAP5 to enable the xHCI host controller. Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | ARM: OMAP5: Add registers and defines for USBOTG SSDan Murphy2013-10-20-2/+20
| | | | | | | | | | | | | | | | | | | | | Add the prcm registers and the bit definitions to enable the USB SS port of the OMAP5 device. Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | exynos5: dts: Add device node for XHCIVivek Gautam2013-10-20-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding device node for xhci host controller to enable usb 3.0 on exynos5250. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Dan Murphy <dmurphy@ti.com> Cc: Marek Vasut <marex@denx.de>
| * | arm: exynos: Add methods to control power to USB 3.0 PHYVivek Gautam2013-10-20-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding methods to turn on/off power to USB3.0 type PHY as and when required by the controller. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Dan Murphy <dmurphy@ti.com> Cc: Marek Vasut <marex@denx.de>
| * | USB: XHCI: Add xHCI host controller support for Exynos5Vivek Gautam2013-10-20-0/+96
| |/ | | | | | | | | | | | | | | | | | | | | | | | | This adds driver layer for xHCI controller in Samsung's exynos5 soc. This interacts with xHCI host controller stack. Signed-off-by: Vikas C Sajjan <vikas.sajjan@samsung.com> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Dan Murphy <dmurphy@ti.com> Cc: Marek Vasut <marex@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2013-10-17-3/+3
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| * | i2c: mxc: move to new subsystemtrem2013-10-17-3/+3
| |/ | | | | | | Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
* | PCIe:change the method to get the address of a requested capability in ↵Zhao Qiang2013-10-16-18/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
* | powerpc/mpc85xx: Add workaround for erratum A006379York Sun2013-10-16-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com>
* | powerpc: Fix CamelCase warnings in DDR related codePriyanka Jain2013-10-16-464/+464
| | | | | | | | | | | | | | | | | | | | | | Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h has various parameters with embedded acronyms capitalized that trigger the CamelCase warning in checkpatch.pl Convert those variable names to smallcase naming convention and modify all files which are using these structures with modified structures. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
* | powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW acceleratorPrabhakar Kushwaha2013-10-16-60/+89
| | | | | | | | | | | | | | | | | | | | | | CHASSIS2 architecture never fix clock groups for Cluster and hardware accelerator like PME, FMA. These are SoC defined. SoC defines :- - NUM of PLLs present in the system - Clusters and their Clock group - hardware accelerator and their clock group if no clock group, then platform clock divider for FMAN, PME Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | powerpc/mpc85xx:Update processor defines for T1040Prabhakar Kushwaha2013-10-16-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040 SoC has - DDR controller ver 5.0 - 2 PLLs - 8 IFC Chip select - FMAN Muram 192K - No Srio - Sec controller ver 5.0 - Max CPU update for its personalities So, update the defines accordingly. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2Prabhakar Kushwaha2013-10-16-5/+5
| | | | | | | | | | | | | | | | | | | | CHASSIS2 architecture never defines type of L2 cache present in SoC. it is dependent upon the core present in the SoC. for example, - e6500 core has L2 cluster (Kibo) - e5500 core has Backside L2 Cache Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | powerpc: add CONFIG_SECURE_BOOT condition into fsl_secure_boot.hPo Liu2013-10-16-0/+2
|/ | | | | | | This patch is for board config file not to add CONFIG_SECURE_BOOT condition for include the asm/fsl_secure_boot.h. Signed-off-by: Po Liu <Po.Liu@freescale.com>
* microblaze: Fix watchdog initializationMichal Simek2013-10-16-4/+3
| | | | | | | | | | | The patch: "blackfin: Move blackfin watchdog driver out of the blackfin arch folder." (sha1: e9a389a18477c1c57a0b30e9ea8f4d38c6e26e63) changed hw_watchdog_init() prototype which didn't match with Microblaze one. This patch fixes the driver and Microblaze initialization. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Coding Style cleanup: drop some excessive empty linesWolfgang Denk2013-10-14-2/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Coding Style cleanup: remove trailing empty linesWolfgang Denk2013-10-14-5/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Coding Style cleanup: replace leading SPACEs by TABsWolfgang Denk2013-10-14-42/+42
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Drop changes for PEP 4 following python tools] Signed-off-by: Tom Rini <trini@ti.com>
* Coding Style cleanup: remove trailing white spaceWolfgang Denk2013-10-14-88/+88
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* ARM: omap4-panda: Add MAC address creation for pandaDan Murphy2013-10-14-0/+4
| | | | | | | | Add a MAC address create based on the OMAP die ID registers. Then poplulate the ethaddr enviroment variable so that the device tree alias can be updated prior to boot. Signed-off-by: Dan Murphy <dmurphy@ti.com>
* ARM: omap4: Update sdram setting for panda rev A6Dan Murphy2013-10-14-0/+4
| | | | | | | | | | OMAP4 panda rev A6 is a 4430 es2.3 IC with an updated memory part. The panda rev A6 uses Elpida 2x4Gb memory and no longer uses Micron so the timings needs to be updated Signed-off-by: Dan Murphy <dmurphy@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-10-08-621/+69
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| * socfpga: Adding System Manager driverChin Liang See2013-10-07-1/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding System Manager driver which will configure the pin mux for real hardware Cyclone V development kit (not Virtual Platform) Signed-off-by: Chin Liang See <clsee@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
| * omap1510inn: arm925t: remove supportAlbert ARIBAUD2013-10-07-608/+0
| | | | | | | | | | | | | | | | | | omap1510inn is orphan and has been for years now. Reove it and, as it was the only arm925t target, also remove arm925t support. Update doc/README.scrapyard accordingly. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * ARM: IGEP0033: Update timing to run DDR at 400MHz.Enric Balletbo i Serra2013-10-07-12/+12
| | | | | | | | | | | | | | We can run the DDR at 400MHz, so update the timings for that purpose. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com> Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2013-10-08-2/+25
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| * | spi: exynos: Support word transfersRajeshwari Shinde2013-10-08-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since SPI register access is so expensive, it is worth transferring data a word at a time if we can. This complicates the driver unfortunately. Use the byte-swapping feature to avoid having to convert to/from big endian in software. This change increases speed from about 2MB/s to about 4.5MB/s. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | armv7: hw_data: change clock divider setting.Poddar, Sourav2013-10-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clock requirement for qspi clk is 192 Mhz. According to the below formulae, f dpll = f ref * 2 * m /(n + 1) clockoutx2_Hmn = f dpll / (hmn+ 1) fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz For clockoutx2_Hmn to be 768, hmn + 1 should be 4. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | omap5: add qspi supportMatt Porter2013-10-07-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | Add QSPI definitions and clock configuration support. Signed-off-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | ARM: virtualization: replace verbose license with SPDX identifierAndre Przywara2013-10-07-35/+3
|/ / | | | | | | | | | | | | | | | | The original creation of arch/arm/cpu/armv7/{virt-v7.c,nonsec_virt.S} predates the SPDX conversion, so the original elaborate license statements sneaked in. Fix this by replacing them with the proper abbreviation. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-10-04-1/+455
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| * ARM: extend non-secure switch to also go into HYP modeAndre Przywara2013-10-03-9/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the KVM and XEN hypervisors to be usable, we need to enter the kernel in HYP mode. Now that we already are in non-secure state, HYP mode switching is within short reach. While doing the non-secure switch, we have to enable the HVC instruction and setup the HYP mode HVBAR (while still secure). The actual switch is done by dropping back from a HYP mode handler without actually leaving HYP mode, so we introduce a new handler routine in our new secure exception vector table. In the assembly switching routine we save and restore the banked LR and SP registers around the hypercall to do the actual HYP mode switch. The C routine first checks whether we are in HYP mode already and also whether the virtualization extensions are available. It also checks whether the HYP mode switch was finally successful. The bootm command part only calls the new function after the non-secure switch. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * ARM: add SMP support for non-secure switchAndre Przywara2013-10-03-1/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the non-secure switch is only done for the boot processor. To enable full SMP support, we have to switch all secondary cores into non-secure state also. So we add an entry point for secondary CPUs coming out of low-power state and make sure we put them into WFI again after having switched to non-secure state. For this we acknowledge and EOI the wake-up IPI, then go into WFI. Once being kicked out of it later, we sanity check that the start address has actually been changed (since another attempt to switch to non-secure would block the core) and jump to the new address. The actual CPU kick is done by sending an inter-processor interrupt via the GIC to all CPU interfaces except the requesting processor. The secondary cores will then setup their respective GIC CPU interface. While this approach is pretty universal across several ARMv7 boards, we make this function weak in case someone needs to tweak this for a specific board. The way of setting the secondary's start address is board specific, but mostly different only in the actual SMP pen address, so we also provide a weak default implementation and just depend on the proper address to be set in the config file. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * ARM: trigger non-secure state switch during bootm executionAndre Przywara2013-10-03-0/+13
| | | | | | | | | | | | | | | | | | To actually trigger the non-secure switch we just implemented, call the switching routine from within the bootm command implementation. This way we automatically enable this feature without further user intervention. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * ARM: add C function to switch to non-secure stateAndre Przywara2013-10-03-0/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core specific part of the work is done in the assembly routine in nonsec_virt.S, introduced with the previous patch, but for the full glory we need to setup the GIC distributor interface once for the whole system, which is done in C here. The routine is placed in arch/arm/cpu/armv7 to allow easy access from other ARMv7 boards. We check the availability of the security extensions first. Since we need a safe way to access the GIC, we use the PERIPHBASE registers on Cortex-A15 and A7 CPUs and do some sanity checks. Boards not implementing the CBAR can override this value via a configuration file variable. Then we actually do the GIC enablement: a) enable the GIC distributor, both for non-secure and secure state (GICD_CTLR[1:0] = 11b) b) allow all interrupts to be handled from non-secure state (GICD_IGROUPRn = 0xFFFFFFFF) The core specific GIC setup is then done in the assembly routine. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * ARM: add assembly routine to switch to non-secure stateAndre Przywara2013-10-03-0/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While actually switching to non-secure state is one thing, another part of this process is to make sure that we still have full access to the interrupt controller (GIC). The GIC is fully aware of secure vs. non-secure state, some registers are banked, others may be configured to be accessible from secure state only. To be as generic as possible, we get the GIC memory mapped address based on the PERIPHBASE value in the CBAR register. Since this register is not architecturally defined, we check the MIDR before to be from an A15 or A7. For CPUs not having the CBAR or boards with wrong information herein we allow providing the base address as a configuration variable. Now that we know the GIC address, we: a) allow private interrupts to be delivered to the core (GICD_IGROUPR0 = 0xFFFFFFFF) b) enable the CPU interface (GICC_CTLR[0] = 1) c) set the priority filter to allow non-secure interrupts (GICC_PMR = 0xFF) Also we allow access to all coprocessor interfaces from non-secure state by writing the appropriate bits in the NSACR register. The generic timer base frequency register is only accessible from secure state, so we have to program it now. Actually this should be done from primary firmware before, but some boards seems to omit this, so if needed we do this here with a board specific value. The Versatile Express board does not need this, so we remove the frequency from the configuration file here. After having switched to non-secure state, we also enable the non-secure GIC CPU interface, since this register is banked. Since we need to call this routine also directly from the smp_pen later (where we don't have any stack), we can only use caller saved registers r0-r3 and r12 to not mess with the compiler. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * ARM: add secure monitor handler to switch to non-secure stateAndre Przywara2013-10-03-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A prerequisite for using virtualization is to be in HYP mode, which requires the CPU to be in non-secure state first. Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine which switches the CPU to non-secure state by setting the NS and associated bits. According to the ARM architecture reference manual this should not be done in SVC mode, so we have to setup a SMC handler for this. We create a new vector table to avoid interference with other boards. The MVBAR register will be programmed later just before the smc call. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
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