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* ARM: tegra: fix ULPI PHY on Ventana and SeaboardStephen Warren2016-09-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Commit ce02a71c2374 "tegra: dts: Sync tegra20 device tree files with Linux" enabled the ULPI USB port on Ventana, but made no attempt to ensure that U-Boot code could handle this. In practice, various code is missing, and various configuration options are not enabled, which causes U-Boot to hang when attempting to initialize this USB port. This patch enables ULPI PHY support on Ventana, and adds the required pinmux setup for the port to operate. Note that Ventana is so similar to Seaboard that this change is made in the Seaboard board file, which is shared with Ventana. Seaboard also has the ULPI USB port wired up in hardware, although to an internal port that often doesn't have anything attached to it. However, the DT nodes for the USB controller and PHY had different status property values, so the port was not initialized by U-Boot. Fix this inconsistency, and enable the ULPI port, just like in the Linux kernel DT. This likewise requires enabling ULPI support in the Seaboard defconfig. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: fix USB controller aliasesStephen Warren2016-09-27-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards have a different set of USB controllers enabled in DT than the set referenced by /alias entries. This patch fixes that. For example, this avoids the following message while booting on Ventana, which is caused by the fact that the USB0 controller had no alias, and defaulted to wanting a sequence number of 0, which was later explicitly requested by the alias for USB controller 2. USB2: Device 'usb@c5008000': seq 0 is in use by 'usb@c5000000' This didn't affect USB operation in any way though. Related, there's no need for the USB controller aliases to have an order that's different from the HW order, so re-order any aliases to match the HW ordering. This has the benefit that since USB controller 0 is the only one that supports device-mode in HW, and U-Boot only supports enabling device move on controller 0, there's now good synergy in the ordering! For Tegra20, that's not relevant at present since USB device mode doesn't work correctly on that SoC, but it will save some head-scratching later. This patch doesn't fix the colibri_t20 board, even though it has the same issue, since Marcel already sent a patch for that. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Harmony and Ventana
* ARM: tegra: fix USB ULPI PHY reset signal inversion confusionStephen Warren2016-09-27-2/+4
| | | | | | | | | | | | | | | | | USB ULPI PHY reset signals are typically active low. Consequently, they should be marked as GPIO_ACTIVE_LOW in device tree, and indeed they are in the Linux kernel DTs, and in DT properties that U-Boot doesn't yet use. However, in DT properties that U-Boot does use, the value has been set to 0 (== GPIO_ACTIVE_HIGH) to work around a bug in U-Boot. This change fixes the DT to correctly represent the HW, and fixes the Tegra USB driver to cope with the fact that dm_gpio_set_value() internally handles any inversions implied by the DT value GPIO_ACTIVE_LOW. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: enable standard clock/reset APIs everywhereStephen Warren2016-09-27-3/+11
| | | | | | | | | | | Implementations of the standard clock and reset APIs are available on all Tegra SoCs now, so enable compilation of those uclasses. Enable the Tegra CAR drivers for all SoCs prior to the BPMP being available. This provides an implementation of those APIs everywhere. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: fix clock_get_periph_rate() for UART clocksStephen Warren2016-09-27-2/+36
| | | | | | | | | | | | | | | | | | | | | | Make clock_get_periph_rate() return the correct value for UART clocks. This change needs to be applied before the patches that enable CONFIG_CLK for Tegra SoCs before Tegra186, since enabling that option causes ns16550_serial_ofdata_to_platdata() to rely on clk_get_rate() for UART clocks, and clk_get_rate() eventually calls clock_get_periph_rate(). This change is a rather horrible hack, as explained in the comment added to the clock driver. I've tried fixing this correctly for all clocks as described in that comment, but there's too much fallout elsewhere. I believe the clock driver has a number of bugs which all cancel each-other out, and unravelling that chain is too complex at present. This change is the smallest change that fixes clock_get_periph_rate() for UART clocks while guaranteeing no change in behaviour for any other clock, which avoids other regressions. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: add APIs the clock uclass driver will needStephen Warren2016-09-27-86/+323
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | A future patch will implement a clock uclass driver for Tegra. That driver will call into Tegra's existing clock code to simplify the transition; this avoids tieing the clock uclass patches into significant refactoring of the existing custom clock API implementation. Some of the Tegra clock APIs that manipulate peripheral clocks require both the peripheral clock ID and parent clock ID to be passed in together. However, the clock uclass API does not require any such "parent" parameter, so the clock driver must determine this information itself. This patch implements new Tegra- specific clock API clock_get_periph_parent() for this purpose. The new API is implemented in the core Tegra clock code rather than SoC- specific clock code. The implementation uses various SoC-/clock-specific data. That data is only available in SoC-specific clock code. Consequently, two new internal APIs are added that enable the core clock code to retrieve this information from the SoC-specific clock code. Due to the structure of the Tegra clock code, this leads to some unfortunate code duplication. However, this situation predates this patch. Ideally, future work will de-duplicate the Tegra clock code, and migrate it into drivers/clk/tegra. However, such refactoring is kept separate from this series. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: add peripheral clock init tableStephen Warren2016-09-27-0/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, Tegra peripheral drivers control two aspects of their HW module clock(s): 1) The clock enable/rate for the peripheral clock itself. 2) The system-level clock tree setup, i.e. the clock parent. Aspect 1 is reasonable, but aspect 2 is a system-level decision, not something that an individual peripheral driver should in general know about or influence. Such system-level knowledge ties the driver to a specific SoC implementation, even when they use generic APIs for clock manipulation, since they must have SoC-specific knowledge such as parent clock IDs. Limited exceptions exist, such as where peripheral HW is expected to dynamically switch between clock sources at run-time, such as CPU clock scaling or display clock conflict management in a multi-head scenario. This patch enhances the Tegra core code to perform system-level clock tree setup, in a similar fashion to the Linux kernel Tegra clock driver. This will allow future patches to simplify peripheral drivers by removing the clock parent setup logic. This change is required prior to converting peripheral drivers to use the standard clock APIs, since: 1) The clock uclass doesn't currently support a set_parent() operation. Adding one is possible, but not necessary at the moment. 2) The clock APIs retrieve all clock IDs from device tree, and the DT bindings for almost all peripherals only includes information about the relevant peripheral clocks, and not any potential parent clocks. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: pull Tegra210 SoC DT from Linux v4.7Stephen Warren2016-09-27-80/+613
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The primary benefit of this change is that it adds all missing clocks and resets properties to peripherals. This will allow peripheral drivers to migrate to the standard clock and reset APIs in the future. Main changes: * Brought in the correct Tegra210 CAR binding; the old file in U-Boot appears to be a renamed version of the Tegra124 bindings rather than the real Tegra210 version. * Conversion of SPI and UART nodes to standard DMA bindings. U-Boot doesn't use DMA so isn't affected. * Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all information required by U-Boot, so U-Boot is not affected. * Conversion of many magic numbers to named defines. * Addition of many nodes not used by U-Boot, including separation of the Tegra LIC (Legacy IRQ controller) and GIC. * Node sort order fixes. Remaining deltas relative to the Linux DT: * U-Boot has enabled PCIe for Tegra210, but the kernel hasn't yet. * The GPIO node compatible value in the kernel explicitly includes Tegra124 values whereas U-Boot does not. I'll send a kernel patch to correct this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: pull Tegra124 SoC DT from Linux v4.7Stephen Warren2016-09-27-7/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | The primary benefit of this change is that it adds all missing clocks and resets properties to peripherals. This will allow peripheral drivers to migrate to the standard clock and reset APIs in the future. Main changes: * USB phy_type property is aligned with the kernel, so board files are updated so the final DT content doesn't change. I'm not convinved that Nyan uses HSIC phy_type. However, I'd rather this change be a no-op, and any DT bug-fixes be separate. * Sync misc changes from the kernel: missing DT content, minor compatible value fixes, typos. Remaining deltas relative to the Linux DT: * U-Boot uses #address-cells/#size-cells of 1 whereas the kernel uses 2. I believe U-Boot's DT parsing currently assumes that these values match the physical address size, so I didn't synchronize this part of the DT. * U-Boot uses the original XUSB PHY DT binding, wherease the kernel DT has moved to a newer version. Thus, XUSB client nodes include properties names phys and phy-names that do not appear in the kernel, and don't include pad definitions in the padctl node. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: pull Tegra114 SoC DT from Linux v4.7Stephen Warren2016-09-27-129/+627
| | | | | | | | | | | | | | | | | | | | | | | | The primary benefit of this change is that it adds all missing clocks and resets properties to peripherals. This will allow peripheral drivers to migrate to the standard clock and reset APIs in the future. Main changes: * Conversion of SPI nodes to standard DMA bindings. U-Boot doesn't use DMA so isn't affected. * Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all information required by U-Boot, so U-Boot is not affected. * Boards need to define the clk32k_in clock that feeds the Tegra PMC. * Addition of tegra114-mc.h since tegra114.dtsi now includes it. * Conversion of many magic numbers to named defines. * Addition of many nodes not used by U-Boot. * Node sort order fixes. Remaining deltas relative to the Linux DT: * USB node compatible values in U-Boot explicitly list Tegra114 values whereas the kernel does not. I'll send a kernel patch to correct this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: pull Tegra30 SoC DT from Linux v4.7Stephen Warren2016-09-27-143/+758
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The primary benefit of this change is that it adds all missing clocks and resets properties to peripherals. This will allow peripheral drivers to migrate to the standard clock and reset APIs in the future. Main changes: * Modification of PCIe memory region addresses. The HW memory layout is programmable, so this should work fine, and Beaver PCIe was tested without issue. * Removal of pcie_xclk from the PCIe node and clock binding header. This clock doesn't exist and isn't used; only a reset with this ID exists. * Conversion of SPI nodes to standard DMA bindings. U-Boot doesn't use DMA so isn't affected. * Split of EHCI and USB PHY nodes. The EHCI nodes continue to contain all information required by U-Boot, so U-Boot is not affected. * Changed the phy_type value for the second USB port. This required board DTs to be updated to keep the same configuration. * Boards need to define the clk32k_in clock that feeds the Tegra PMC. * Addition of tegra30-mc.h since tegra30.dtsi now includes it. * Conversion of many magic numbers to named defines. * Addition of many nodes not used by U-Boot. * Node sort order fixes. Remaining deltas relative to the Linux DT: * None. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: pull Tegra20 SoC DT from Linux v4.7Stephen Warren2016-09-27-2/+2
| | | | | | | | | | | | | This brings in a few minor fixes since the last sync. The largest change is the removal of the definition for TEGRA20_CLK_PCIE_XCLK. This clock doesn't actually exist. Remaining deltas: * Addition of u-boot,dm-pre-reloc property to a couple of nodes. * Addition of the NAND controller, which Linux doesn't yet support. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: remove "0, " from DT unit addressesStephen Warren2016-09-27-82/+82
| | | | | | | | | Apparently the unit address in a DT node name is now supposed to be a single integer value, rather than a comma-separated list of individual cell values. Fix the U-Boot DTs to comply with this naming convention. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* mmc: tegra: Add DM_MMC support to Tegra MMC driverTom Warren2016-09-27-35/+1
| | | | | | | | | | | Convert the Tegra MMC driver to DM_MMC. Support for non-DM is removed to avoid ifdefs in the code. DM_MMC is now enabled for all Tegra builds. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Tom Warren <twarren@nvidia.com> (swarren, fixed some NULL pointer dereferences, removed extraneous changes, rebased on various other changes, removed non-DM support etc.) Signed-off-by: Stephen Warren <swarren@nvidia.com>
* ARM: tegra: set MMC pin mux in board_init()Stephen Warren2016-09-27-7/+5
| | | | | | | | | Most other pin mux is configured in this function. This removes the need to do it in an MMC-specific initialization function, which is good since that function is going away later in this series. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* mmc: tegra: priv struct and naming cleanupStephen Warren2016-09-27-19/+0
| | | | | | | | | | | | | | | | | | | | struct mmc_host is a Tegra-specific structure, but the name implies it's something defined by core MMC code, which is confusing. Rename it to struct tegra_mmc_priv to make its purpose more obvious. The new name is also more appropriate for a DM driver private data structure, which will be relevant later in this series. Nothing needs access to this type except the MMC driver itself. Move the definition into the driver C file. Make sure all Tegra MMC functions are named tegra_mmc_*. Even though they're all static, it's useful to have good naming so that symbol tables are easy to interpret. A few functions aren't renamed by this patch since they'll be deleted by a subsequent patch in this series. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* mmc: tegra: move pad_init_mmc() into MMC driverStephen Warren2016-09-27-36/+0
| | | | | | | | | | pad_init_mmc() is performing an SoC-specific operation, using registers within the MMC controller. There's no reason to implement this code outside the MMC driver, so move it inside the driver. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* mmc: tegra: use correct alias for SDHCI/MMC nodesStephen Warren2016-09-27-48/+48
| | | | | | | | | | | | | | | The Tegra MMC driver currently honors "sdhci" entries in /aliases. The MMC core however uses "mmc" entries in /aliases. This difference will be relevant once the Tegra MMC driver is converted to DM, and the MMC core handles alias lookups. To avoid issues during that conversion, fix the Tegra MMC driver and all Tegra DTs to use the same alias name as the MMC core does. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: fdt: Add 'non-removable' property to all eMMC nodesTom Warren2016-09-27-0/+13
| | | | | | | | | | | During debug of the DM_MMC changes to the Tegra MMC driver, I noticed that the 'removable' property wasn't being set correctly for the eMMC parts on most Tegra boards. Since the kernel DTS has this property set correctly, it should be in U-Boot's Tegra DT too. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-09-26-47/+1246
|\ | | | | | | | | | | | | trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
| * armv7: ls102xa: Rename GIC_ADDR and DCSR_RCPM_ADDRYork Sun2016-09-26-4/+4
| | | | | | | | | | | | | | | | | | Instead of using CONFIG_* name space, rename these two macros to SYS_FSL_* space. Signed-off-by: York Sun <york.sun@nxp.com> CC: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * armv7: ls1021a: Convert CONFIG_LS1_DEEP_SLEEP to Kconfig optionYork Sun2016-09-26-0/+5
| | | | | | | | | | | | | | | | Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * Convert CONFIG_SYS_FSL_ERRATUM_A010315 to Kconfig optionYork Sun2016-09-26-2/+17
| | | | | | | | | | | | | | Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
| * armv8: ls1012a: Convert CONFIG_LS1012A to Kconfig option ARCH_LS1021AYork Sun2016-09-26-8/+16
| | | | | | | | | | | | | | | | | | Move this config to Kconfig option and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Calvin Johnson <calvin.johnson@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * armv8: ls1046a: Convert CONFIG_LS1046A to Kconfig option ARCH_LS1046AYork Sun2016-09-26-4/+11
| | | | | | | | | | | | | | | | | | Move this option to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> CC: Mingkai Hu <mingkai.hu@nxp.com> CC: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * armv8: ls1046aqds: Add LS1046AQDS board supportShaohui Xie2016-09-14-0/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1046AQDS Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: supports Gen 1 and Gen 2 SATA 3.0: one SATA 3.0 port USB 3.0: two micro AB connector and one type A connector UART: supports two UARTs up to 115200 bps for console Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046ardb: Add LS1046ARDB board supportMingkai Hu2016-09-14-0/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1046ARDB Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 512 Mbyte NAND flash * Two 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card * On-board 4G eMMC Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: * PCIe1 (SerDes2 Lane0) to miniPCIe slot * PCIe2 (SerDes2 Lane1) to x2 PCIe slot * PCIe3 (SerDes2 Lane2) to x4 PCIe slot SATA: * SerDes2 Lane3 to SATA port USB 3.0: one super speed USB 3.0 type A port one Micro-AB port UART: supports two UARTs up to 115200 bps for console Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046a: disable SATA ECC in DCSRShaohui Xie2016-09-14-0/+4
| | | | | | | | | | | | | | | | | | This is a workaround to fix SATA CRC error. Once the root cause is found the ECC disabling will be removed. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046a: Enable DDR erratum for ls1046aShengzhou Liu2016-09-14-0/+6
| | | | | | | | | | | | | | | | | | Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803, ERRATUM_A009942, ERRATUM_A010165 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: spl: remove BSS clearing and board_init_rQianyu Gong2016-09-14-5/+0
| | | | | | | | | | | | | | | | | | | | As per the top level U-Boot README "Board Initialisation Flow" section, board_init_f() should return without calling board_init_r() directly. Clearing BSS and calling board_init_r() will be done in crt0_64.S. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: add define CONFIG_STANDALONE_LOAD_ADDR for standalone appShaohui Xie2016-09-14-0/+2
| | | | | | | | | | | | | | | | The CONFIG_STANDALONE_LOAD_ADDR is set to 0x80300000 by default. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latencyMingkai Hu2016-09-14-0/+15
| | | | | | | | | | | | | | | | | | | | | | According to design specification, the L2 cache operates at the same frequency as the A72 CPUs in the cluster with a 3-cycle latency, so increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else, will run into different call trace issues. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012aShengzhou Liu2016-09-14-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future. Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/ LS1012AFRDM. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7:ls1021a: Enable workaround for DDR erratum A-009942Shengzhou Liu2016-09-14-0/+1
| | | | | | | | | | Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * nxp: ls102xa: add LS1 PSCI system suspendHongbo Zhang2016-09-14-1/+248
| | | | | | | | | | | | | | | | The deep sleep function of LS1 platform, is mapped into PSCI system suspend function, this patch adds implementation of it. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * nxp: ls102xa: add EPU Finite State MachineHongbo Zhang2016-09-14-0/+165
| | | | | | | | | | | | | | | | The EPU Finite State Machie (FSM) is used in both the last stage of system suspend and the earliest stage of system resume. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * nxp: ls102xa: add registers definition for system sleepHongbo Zhang2016-09-14-1/+53
| | | | | | | | | | | | | | | | This patch adds definitions of all the regesters necessary for system sleep. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv7: psci: make v7_flush_dcache_all public for all psci codeHongbo Zhang2016-09-14-3/+5
| | | | | | | | | | | | | | | | | | | | | | The v7_flush_dcache_all function will be called by ls102xa platform system suspend, it is necessary to make it a public call instead of a local one, but changing the LENTRY to ENTRY isn't enough, because there is another one using the same name, so this one gets a psci_ prefix. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls2080a: Remove debug server supportYork Sun2016-09-14-14/+0
| | | | | | | | | | | | Debug server feature has been dropped from roadmap. Signed-off-by: York Sun <york.sun@nxp.com>
| * fsl-layerscape: Add workaround for PCIe erratum A010315Hou Zhiqiang2016-09-14-0/+41
| | | | | | | | | | | | | | | | | | | | As the access to serders protocol unselected PCIe controller will hang. So disable the R/W permission to unselected PCIe controller including its CCSR, IO space and memory space according to the serders protocol field of RCW. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl: csu: add an API to set R/W permission to PCIeHou Zhiqiang2016-09-14-0/+1
| | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arm: fsl-layerscape: move forward the non-secure access permission setupHou Zhiqiang2016-09-14-4/+10
| | | | | | | | | | | | | | | | | | | | Move forward the basic non-secure access enable operation, so the subsequent individual device access permission can override it. And collect the dispersed callers in board level, and then move them to SoC level. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl: serdes: ensure accessing the initialized maps of serdes protocolHou Zhiqiang2016-09-14-9/+276
| | | | | | | | | | | | | | | | | | | | | | | | Up to now, the function is_serdes_configed() doesn't check if the map of serdes protocol is initialized before accessing it. The function is_serdes_configed() will get wrong result when it was called before the serdes protocol maps initialized. As the first element of the map isn't used for any device, so use it as the flag to indicate if the map has been initialized. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * ls1043ardb: PPA: add PPA validation in case of secure bootSumit Garg2016-09-14-0/+39
| | | | | | | | | | | | | | | | | | | | As part of Secure Boot Chain of trust, PPA image must be validated before the image is started. The code for the same has been added. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Update ddr erratum a008336Shengzhou Liu2016-09-14-2/+4
| | | | | | | | | | | | | | | | | | DDR erratum A008336 only applies to DDR controller v5.2.0. DDR controller v5.2.1 already has default 0x43b30002 in EDDRTQCR1 register for optimal performance. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | arm: mvebu: NAND support for DB-88F6820-AMCChris Packham2016-09-24-0/+8
| | | | | | | | | | | | | | Enable the NAND interface on this board. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | arm: mvebu: add DB-88F6820-AMC boardChris Packham2016-09-24-0/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board is a plug in card for Marvell's switch system development kits. Form-factor aside it is similar to the DB-88F6820-GP with the following differences. - TCLK is 200MHz - SPI1 is used - No SATA - No MMC - NAND flash Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | arm: mvebu: create generic 88F6820 config optionChris Packham2016-09-24-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | 88F6820 is a specific Armada-38x chip that is used on the DB-88F6820-GP board. Rather than having DB_88F6820_GP and TARGET_DB_88F6820_GP which selects the former. Rename DB_88F6820_GP to 88F6820 so that other boards using the 88F6820 can be added. Stefan: Change 88F6820 for clearfog as well. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | treewide: replace #include <asm-generic/errno.h> with <linux/errno.h>Masahiro Yamada2016-09-23-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Now, include/linux/errno.h is a wrapper of <asm-generic/errno.h>. Replace all include directives for <asm-generic/errno.h> with <linux/errno.h>. <asm-generic/...> is supposed to be included from <asm/...> when arch-headers fall back into generic implementation. Generally, they should not be directly included from .c files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Add drivers/usb/host/xhci-rockchip.c] Signed-off-by: Tom Rini <trini@konsulko.com>
* | Remove arch/${ARCH}/include/asm/errno.hMasahiro Yamada2016-09-23-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike Linux, nothing about errno.h is arch-specific in U-Boot. As you see, all of arch/${ARCH}/include/asm/errno.h is just a wrapper of <asm-generic/errno.h>. Actually, U-Boot does not export headers to user-space, so we just have to care about the consistency in the U-Boot tree. Now all of include directives for <asm/errno.h> are gone. Deprecate <asm/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
generated by cgit v1.1 at 2024-09-19 14:52:35 +0000