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* ARM: uniphier: consolidate System Bus pin-mux settings for LD11/LD20Masahiro Yamada2016-09-18-44/+5
| | | | | | | Use the pin-mux data in the pinctrl drivers by directly calling pinctrl_generic_set_state(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: include System Bus pin group node in SPL DTMasahiro Yamada2016-09-18-0/+8
| | | | | | | This will be needed for setting up the System Bus pin-mux via the LD11/LD20 pinctrl driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: consolidate NAND pin-mux settingsMasahiro Yamada2016-09-18-274/+51
| | | | | | | | The NAND subsystem has not supported the Driver Model yet, but the NAND pin-mux data are already in the pinctrl drivers. Use them by calling pinctrl_generic_set_state() directly. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove ad-hoc pin-mux code for sLD3Masahiro Yamada2016-09-18-58/+0
| | | | | | These settings are nicely cared by the pinctrl driver now. Remove. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove redundant pin-muxing for EA24 pin of sLD3 SoCMasahiro Yamada2016-09-18-2/+0
| | | | | | This is enabled by default for all the supported boot modes. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: select PINCTRL and SPL_PINCTRLMasahiro Yamada2016-09-18-0/+2
| | | | | | | Now all UniPhier SoCs support a pinctrl driver. Select (SPL_)PINCTRL since it is mandatory even for base use. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: add pinctrl device node and pinctrl propertiesMasahiro Yamada2016-09-18-0/+43
| | | | | | DT-side updates to make pinctrl on sLD3 SoC really available. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: introduce flags to adjust DRAM timing for LD20/LD21Masahiro Yamada2016-09-17-4/+32
| | | | | | | | | Unfortunately, this SoC needs per-board adjustment between clock and address/command lines. This flag will be passed to the DRAM init function and used for compensating the difference of DRAM timing parameters. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: fix DRAM size of LD21 SoC packageMasahiro Yamada2016-09-17-1/+1
| | | | | | The channel 0 DRAM size of LD21 is half of that of LD20. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: merge board init functions into board_init()Masahiro Yamada2016-09-14-40/+16
| | | | | | | | | | | | | | | | | | Currently, the UniPhier platform calls several init functions in the following order: [1] spl_board_init() [2] board_early_init_f() [3] board_init() [4] board_early_init_r() [5] board_late_init() The serial console is not ready at the point of [2], so we want to avoid using [2] from the view point of debuggability. Fortunately, all of the initialization in [2] can be delayed until [3]. I see no good reason to split into [3] and [4]. So, merge [2] through [4]. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: use checkboard() instead of misc_init_f()Masahiro Yamada2016-09-14-24/+7
| | | | | | | We can use checkboard() stub to show additional board information, so misc_init_f() should not be used for this purpose. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: remove IECTRL setup code of LD4 SoCMasahiro Yamada2016-09-14-6/+0
| | | | | | This should be handled by the pinctrl driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: uniphier-sd: migrate to CONFIG_BLKMasahiro Yamada2016-09-14-0/+1
| | | | | | | This is the state-of-the-art MMC driver implementation. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ARM: uniphier: delete unnecessary xHCI pin-mux settingsMasahiro Yamada2016-09-14-48/+0
| | | | | | | These ad-hoc pinmux settings were used for the legacy xHCI driver, which has gone now. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* usb: uniphier: remove UniPhier xHCI driver and select DM_USBMasahiro Yamada2016-09-14-0/+1
| | | | | | | | | | | | | | This driver has not been converted to Driver Model, and it is an obstacle to migrate other block device drivers. Remove it for now. The UniPhier SoCs already use a DM-based EHCI driver, so now ARCH_UNIPHIER can select DM_USB. These two changes must be done atomically because removing the legacy driver causes a build error. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
* ARM: uniphier: sort select:s alphabeticallyMasahiro Yamada2016-09-14-7/+7
| | | | | | | ARCH_UNIPHIER is having more and more select:s. Sort them in case a select is accidentally duplicated. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-09-09-4/+9
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| * mx6: ddr: Allow changing REFSEL and REFR fieldsFabio Estevam2016-09-06-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently MX6 SPL DDR initialization hardcodes the REF_SEL and REFR fields of the MDREF register as 1 and 7, respectively for DDR3 and 0 and 3 for LPDDR2. Looking at the MDREF initialization done via DCD we see that boards do need to initialize these fields differently: $ git grep 0x021b0020 board/ board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */ board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800 board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800 board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800 So introduce a mechanism for users to be able to configure REFSEL and REFR fields as needed. Keep all the mx6 SPL users in their current REF_SEL and REFR values, so no functional changes for the existing users. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
| * arm: imx: Add support for Advantech DMS-BA16 boardAkshay Bhat2016-09-06-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Advantech DMS-BA16 board. The board is based on Advantech BA16 module which has a i.MX6D processor. The board supports: - FEC Ethernet - USB Ports - SDHC and MMC boot - SPI NOR - LVDS and HDMI display Basic information about the module: - Module manufacturer: Advantech - CPU: Freescale ARM Cortex-A9 i.MX6D - SPECS: Up to 2GB Onboard DDR3 Memory; Up to 16GB Onboard eMMC NAND Flash Supports OpenGL ES 2.0 and OpenVG 1.1 HDMI, 24-bit LVDS 1x UART, 2x I2C, 8x GPIO, 4x Host USB 2.0 port, 1x USB OTG port, 1x micro SD (SDHC),1x SDIO, 1x SATA II, 1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2 Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Cc: u-boot@lists.denx.de Cc: sbabic@denx.de
* | ARM: am335x: select DM_GPIOMasahiro Yamada2016-09-07-0/+1
| | | | | | | | | | | | | | | | We are supposed to not add config entries with only "default y" in board/SoC Kconfig files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
* | ARM: armv7: move ARMV7_PSCI_NR_CPUS to KconfigMasahiro Yamada2016-09-07-0/+9
| | | | | | | | | | | | | | | | | | | | | | Move this option to Kconfig and set its default value to 4; this increases the number of supported CPUs for some boards. It consumes 1KB memory per CPU for PSCI stack, but it should not be a big deal, given the amount of memory used for the modern OSes. Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: armv7: move CONFIG_ARMV7_PSCI to KconfigMasahiro Yamada2016-09-07-0/+16
| | | | | | | | | | | | | | | | | | Add ARCH_SUPPORT_PSCI as a non-configurable option that platforms can select. Then, move CONFIG_ARMV7_PSCI, which is automatically enabled if both ARMV7_NONSEC and ARCH_SUPPORT_PSCI are enabled. Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: armv7: guard memory reserve for PSCI with #ifdef CONFIG_ARMV7_PSCIMasahiro Yamada2016-09-07-2/+2
| | | | | | | | | | | | | | | | If CONFIG_ARMV7_NONSEC is enabled, the linker script requires CONFIG_ARMV7_PSCI_NR_CPUS regardless of CONFIG_ARMV7_PSCI. Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: tegra: remove wrong dependency on SPL_BUILDMasahiro Yamada2016-09-07-2/+2
| | | | | | | | | | | | | | SPL_BUILD is not a CONFIG in Kconfig, so !SPL_BUILD is always true. Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | TI: Rework SRAM definitions and maximumsTom Rini2016-09-06-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On all TI platforms the ROM defines a "downloaded image" area at or near the start of SRAM which is followed by a reserved area. As it is at best bad form and at worst possibly harmful in corner cases to write in this reserved area, we stop doing that by adding in the define NON_SECURE_SRAM_IMG_END to say where the end of the downloaded image area is and make SRAM_SCRATCH_SPACE_ADDR be one kilobyte before this. At current we define the end of scratch space at 0x228 bytes past the start of scratch space this this gives us a lot of room to grow. As these scratch uses are non-optional today, all targets are modified to respect this boundary. Tested on OMAP4 Pandaboard, OMAP3 Beagle xM Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Felipe Balbi <balbi@ti.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Paul Kocialkowski <contact@paulk.fr> Cc: Enric Balletbo i Serra <eballetbo@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Stefan Roese <sr@denx.de> Cc: Thomas Weber <weber@corscience.de> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Heiko Schocher <hs@denx.de> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: "B, Ravi" <ravibabu@ti.com> Cc: "Matwey V. Kornilov" <matwey.kornilov@gmail.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: "Kipisz, Steven" <s-kipisz2@ti.com> Cc: Daniel Allred <d-allred@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Ladislav Michl <ladis@linux-mips.org>
* | meson: odroid-c2: enable Ethernet support through the device treeBeniamino Galvani2016-09-06-3/+0
| | | | | | | | | | | | | | | | Remove the device definition from board file, update the driver with the new compatible property and update config with necessary options. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | arm: dts: update DTS files for meson-gxbb and odroid-c2Beniamino Galvani2016-09-06-1/+188
| | | | | | | | | | | | | | Import DTS files and dt-bindings includes from Linux 4.8-rc1. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | bcm2835_gpio: Implement GPIOF_FUNCAlexander Graf2016-09-06-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | So far we could only tell the gpio framework that a GPIO was mapped as input or output, not as alternative function. This patch adds support for determining whether a function is mapped as alternative. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-09-06-51/+440
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| * | sunxi: Add defconfig and dts file for the Orange Pi Plus2E SBCHans de Goede2016-09-03-1/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Orange Pi Plus2E is an extended version of the Orange Pi Pc Plus, with 2G RAM and an external gbit ethernet phy. The dts file is identical to the one submitted to the upstream kernel, except that it has the pending patch to enable the ethernet controller squashed in, as u-boot already has sun8i-emac support. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Sync h3-orangepi dts files with kernelHans de Goede2016-09-03-47/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds an emac node to the orangepi-2 dts (not yet merged upstream, but in u-boot we already have emac support); fixes the alphetically sorting of nodes in sun8i-h3-orangepi-plus.dts and disables some usb controllers in sun8i-h3-orangepi-plus.dts which are only used on the plus2e, as upstream has decided to do a separate dts files for the plus2e. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Fix H3 EMAC syscon register addressChen-Yu Tsai2016-09-03-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sun8i-emac driver follows an old version of the proposed DT bindings, where the EMAC clock and EPHY control register range is listed directly, rather than through a syscon phandle. Add back the syscon register range to avoid an invalid data access. We should fix the driver once the Linux kernel bindings have been finalized. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Add support for A33-OLinuXino boardStefan Mavrodiev2016-09-03-0/+227
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A33-OLinuXino is A33 development board designed by Olimex LTD. It has AXP223 PMU, 1GB DRAM, a micro SD card, one USB-OTG connector, headphone and mic jacks, connector for LiPo battery and optional 4GB NAND Flash. It has two 40-pin headers. One for LCD panel, and one for additional modules. Also there is CSI/DSI connector. The dts files are identical to the ones submitted to the upstream kernel. Signed-off-by: Stefan Mavrodiev <stefan.mavrodiev@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: add proper device tree for iNet D978 rev2 boardsIcenowy Zheng2016-09-03-0/+89
| |/ | | | | | | | | | | | | | | Add a proper dts for the iNet D978 rev2 based A33 tablets. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | ARM: dts: dra72-evm: fix broken ethernetMugunthan V N2016-09-06-1/+1
|/ | | | | | | | | | | With commit ceec08f50b6, phy is connected to slave 0, but changing the phy node was missed, fix it by populating the phy node to proper cpsw slave node. Fixes: ceec08f50b6 ("ARM: dts: dra72-evm: Add mode-gpios entry for mac node") Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Cc: Vignesh R <vigneshr@ti.com> Tested-by: Tom Rini <trini@konsulko.com>
* ARM: tegra: Add support for TK1-SOM board from Colorado EngineeringPeter Chubb2016-09-01-0/+490
| | | | | | | | | | | | | | The Colorado TK1 SOM is a small form factor board similar to the Jetson TK1. The main differences lie in the pinmux, and in that the PCIe controller is set to use in 4lanes+1lane, rather than 2+2. The pinmux header here was generated from a spreadsheet provided by Colorado Engineering using the tegra-pinmux scripts. The spreadsheet was converted from v09 to v11 by me. Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: use numeric versioning for p2771-0000Stephen Warren2016-08-30-6/+6
| | | | | | | | | | | | | | | | | The board ID EEPROM and board ID stickers on p2771-0000 will use a numeric versioning scheme, with version numbers such as 000/100/200/300/400/500. Within NVIDIA, these versions are also known as A00/A01/A02/A03/A04/B00. However, that numbering scheme is not easily visible outside of NVIDIA, and so does not make much sense to use. Convert U-Boot to use the readily visible numeric scheme. Also, it turns out that the current A02 DT actually applies to board versions 000/100/200 (A00..A02). Consequently rename this to 000 not 200 so that all U-Boot builds are named after the first version of the HW they support. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* x86: efi: Fix EFI 64-bit payload build warningsBin Meng2016-08-30-4/+0
| | | | | | | | | | | | | | | | | There are lots of warnings when building EFI 64-bit payload. include/asm-generic/bitops/__fls.h:17:2: warning: left shift count >= width of type if (!(word & (~0ul << 32))) { ^ In fact, U-Boot itself as EFI payload is running in 32-bit mode. So BITS_PER_LONG needs to still be 32, but EFI status codes are 64-bit when booting from 64-bit EFI. Introduce EFI_BITS_PER_LONG to bridge those status codes with U-Boot's BITS_PER_LONG. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Add debugging when cpu_common_init() failsSimon Glass2016-08-30-1/+3
| | | | | | | Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Allow microcode to be collatedSimon Glass2016-08-30-1/+11
| | | | | | | | | | | Generally the microcode is combined into a single block only (and removed from the device tree) when there are multiple blocks. But this is not a requirement. Adjust the ivybridge code to avoid assuming this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add debugging when a microcode update failsSimon Glass2016-08-30-1/+3
| | | | | | | | Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher<hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-08-28-4/+35
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| * ARM: dts: uniphier: add u-boot, dm-pre-reloc to use eMMC boot on sLD3Masahiro Yamada2016-08-28-0/+9
| | | | | | | | | | | | | | The eMMC on sLD3 is assigned with dedicated pins (only multiplexed with GPIO), so it shouldn't hurt to enable eMMC on SPL all the time. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: display revision of Micro Support Card 3.6.x kindlyMasahiro Yamada2016-08-28-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The revision of the original support card (rev 3.5, rev 3.6) fits in the 8 bit width revision register. When it was extended in a weird way, it was versioned in the format of "3.6.x" (where it should have been "3.7", of course). What is worse, only the sub-level version "6.x" was recorded in the 8 bit width register, completely ignoring the compatibility of the revision register format. This patch saves madly-versioned support cards by assuming the major version "3" when the MSB 4 bit of the register is read as "6". With this, the support card revision that were displayed as "6.10" is now corrected to "3.6.10". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: support system reset functionality for PSCIMasahiro Yamada2016-08-28-2/+17
| | | | | | | | | | | | | | | | | | | | This supports the system reset via PSCI for ARMv7 SoCs. Because the system reset is not supported on PSCI 0.1, let's define CONFIG_ARMV7_PSCI_1_0. (it is supported since PSCI 0.2, but there is no CONFIG to enable it in U-Boot for now.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-08-26-2193/+3539
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| * | sunxi: Tune H3 DRAM PLL to improve lock timeJens Kuske2016-08-26-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The H3 PLL5 used for DRAM barely manages to lock to the required frequency before DRAM controller starts, sometimes leading to wrong delay-line calibration results. This patch changes the PLL tuning parameters to the same values as boot0 used, which speeds up the locking and fixes the problem. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: display: Use PWM to drive backlight where applicableHans de Goede2016-08-26-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the backlight's pwm input is connected to a pwm output of the SoC, actually use pwm to drive the backlight. The mean reason for doing this is to fix the backlight turning off for aprox. 1 second while the kernel is booting. This is caused by the kernel actually using pwm to drive the backlight, so that it can dim the backlight. First the pwm driver loads and switches the pinmux for the pin driving the backlight's pwm input to the pwm controller. Then about 1s later the actual backlight driver loads and tells the pwm driver to actually update the pwm settings, which have a power-on-reset value of "off". An additional advantage is that this allows us to initatiate the backlight at 80%, which is the kernel default, avoiding a brightness change while the kernel loads. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed by: Peter Korsgaard <peter@korsgaard.com>
| * | sun5i: Add defconfig and dts file for the Empire Electronix M712 tabletHans de Goede2016-08-26-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a defconfig and dts file for the Empire Electronix M712 tablet, this is a 7" A13 tablet, with micro-usb (otg), headphone and micro-sd slots on the outside. It uses a Goodix gt811 touchscreen controller, a RTL8188CTV wifi chip and a DMART06 (1238a4) accelerometer. The dts file is identical to the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Sync dts files with upstream kernelHans de Goede2016-08-26-2192/+3135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sync dts files with the current (Aug 18th 2016) state of Maxime's linux/sunxi/for-next repo. Note this commit also updates configs/MSI_Primo81_defconfig, adding: "# CONFIG_REQUIRE_SERIAL_CONSOLE is not set", this is necessary because the tablet does not have a reachable uart so the dts sync drops its serial0 alias. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
generated by cgit v1.1 at 2024-11-09 19:13:10 +0000