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| * | sun6i: Add defconfig and dts file for tablets using the inet-q972 PCBHans de Goede2016-08-26-0/+294
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a defconfig and dts file for tablets using the generic inet-q972 PCB. Tablets with this PCB feature a mini-hdmi output, micro-usb usb-host, micro-usb usb-otg, 3.5mm headphone jack, a micro sd slot, (mini) power-barrel and an usb wifi module. This has been tested on a 9.7" 1024x768 qware qw tb9718-qhd tablet. The dts files are identical to the ones submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | treewide: fix "followings" to "following"Masahiro Yamada2016-08-26-2/+2
| | | | | | | | | | | | Most of them are my mistakes. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | arm: cache: always flush cache line size for page tableStefan Agner2016-08-26-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | The page table is maintained by the CPU, hence it is safe to always align cache flush to a whole cache line size. This allows to use mmu_page_table_flush for a single page table, e.g. when configure only small regions through mmu_set_region_dcache_behaviour. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* | arm: cache: add support for LPAE for region D$ behaviorStefan Agner2016-08-26-0/+4
| | | | | | | | | | | | | | Add LPAE support for mmu_set_region_dcache_behaviour. The function is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
* | arch/arm/Kconfig: Whitespace correctionTom Rini2016-08-26-28/+28
| | | | | | | | | | | | Use a tab not 8 spaces. Signed-off-by: Tom Rini <trini@konsulko.com>
* | ARM: Move SYS_CACHELINE_SIZE over to KconfigTom Rini2016-08-26-46/+32
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefan Agner <stefan.agner@toradex.com> Acked-by: Heiko Schocher <hs@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Peter Griffin <peter.griffin@linaro.org> Acked-by: Paul Kocialkowski <contact@paulk.fr> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: "Pali Rohár" <pali.rohar@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Nishanth Menon <nm@ti.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Thomas Weber <weber@corscience.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Alison Wang <b18965@freescale.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com> Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Saksham Jain <saksham.jain@nxp.com> Cc: Qianyu Gong <qianyu.gong@nxp.com> Cc: Wang Dongsheng <dongsheng.wang@nxp.com> Cc: Alex Porosanu <alexandru.porosanu@freescale.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: tang yuantian <Yuantian.Tang@freescale.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Anand Moon <linux.amoon@gmail.com> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: huang lin <hl@rock-chips.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Xu Ziyuan <xzy.xu@rock-chips.com> Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com> Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Bernhard Nortmann <bernhard.nortmann@web.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Alexander Graf <agraf@suse.de> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: "Andrew F. Davis" <afd@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Carlos Hernandez <ceh@ti.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Daniel Allred <d-allred@ti.com> Cc: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Chin Liang See <clsee@altera.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Paul Kocialkowski <contact@paulk.fr>
* Merge branch 'master' of git://www.denx.de/git/u-boot-marvellTom Rini2016-08-26-21/+31
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| * arm: mvebu: a38x: typo fix cpabilities -> capbilitiesChris Packham2016-08-26-1/+1
| | | | | | | | | | Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: a38x: update serdes error handlingChris Packham2016-08-26-19/+20
| | | | | | | | | | | | | | | | | | Ensure appropriate error messages are generated. Previously all errors indicated that the serdes was already in use. Now appropriate error messages are given. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * arm: mvebu: Add support for NAND interface on A-38xChris Packham2016-08-26-1/+10
| | | | | | | | | | | | | | | | | | | | | | The NAND interface on the Armada-38x series is similar to that on the Armada-XP. The key difference is that the NAND ECC clock ratio is provided via the DFX Server registers instead of the Core Clock. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | ARM: tegra: remove stale nvidia, bpmp I2C DT propertyStephen Warren2016-08-25-1/+0
| | | | | | | | | | | | | | | | | | | | The nvidia,bpmp property is left over from an old BPMP I2C binding, and shouldn't be present. Remove it from the SoC DT file, and update the I2C driver not to parse it; the value wasn't used for anything any more anyway. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: fix Tegra186 SDHCI clock/reset namesStephen Warren2016-08-25-4/+2
| | | | | | | | | | | | | | | | | | The Tegra SDHCI binding dictates that the reseet name for the Tegra SDHCI clock be "sdhci" not "sdmmc", and that the clock is accessed by index rather than by name. Fix the Tegra186 DT and MMC driver to honor this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: fix Tegra186 I2C clock nameStephen Warren2016-08-25-8/+8
|/ | | | | | | | The Tegra I2C binding dictates that the clock name for the Tegra I2C clock be "div-clk" not "i2c". Fix the Tegra186 DT and I2C driver to honor this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2016-08-20-32/+9120
|\ | | | | | | | | [trini: Drop CMD_BOOTI as it's now on by default on ARM64] Signed-off-by: Tom Rini <trini@konsulko.com>
| * ARM: rmobile: r8a7795: Add MMU layoutNobuhiro Iwamatsu2016-08-17-1/+31
| | | | | | | | | | | | This add MMU layout for R8A7795 of Renesas ARM64 SoC. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arm: rmobile: Add BLANCHE board supportmasakazu.mochizuki.wd@hitachi.com2016-08-17-25/+2983
| | | | | | | | | | | | | | | | | | | | BLANCHE is development board based on R-Car V2H SoC (R8A7792) This commit supports the following periherals: - SCIF, Ethernet, QSPI, MMC Signed-off-by: Masakazu Mochizuki <masakazu.mochizuki.wd@hitachi.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Add support salvator-x boardNobuhiro Iwamatsu2016-08-17-0/+16
| | | | | | | | | | | | | | | | Salvator-x is an entry level development board based on R-Car H3 SoC (R8A7795). This commit supports SCIF only. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Add support R8A7795Nobuhiro Iwamatsu2016-08-17-0/+5874
| | | | | | | | | | | | | | | | | | Renesas R8A7795 is CPU with Cortex-a57. This supports the basic register definition and GPIO and framework of PFC. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Add support R-Car Generation 3Nobuhiro Iwamatsu2016-08-17-0/+193
| | | | | | | | | | | | | | This adds supporting R-Car Generation 3 (Gen3) as Renesas ARM64 SoC. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Create R-Car 32bit (Gen1 and Gen2) for KconfigNobuhiro Iwamatsu2016-08-17-82/+96
| | | | | | | | | | | | This creates Kconfig of R-Car 32bit for Kconfig of R-Car 64bit (Gen3). Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: Rmobile: Rename CONFIG_RMOBILE to CONFIG_ARCH_RMOBILENobuhiro Iwamatsu2016-08-17-5/+7
| | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Move SoC headers to mach-rmobile/include/machNobuhiro Iwamatsu2016-08-17-0/+0
| | | | | | | | | | | | Move form arch/arm/include/asm/arch-rmobile/ to arch/arm/mach-rmobile/include/mach/. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * ARM: rmobile: Move SoC sources to mach-rmobileNobuhiro Iwamatsu2016-08-17-2/+3
| | | | | | | | | | | | Move from arch/arm/cpu/armv7/rmobile/ to arch/arm/mach-rmobile/. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | ARM: OMAP4+: vcores: Remove duplicated codeLokesh Vutla2016-08-20-52/+10
| | | | | | | | | | | | | | | | | | | | There is no reason to duplicate code for DRA7xx platforms as there can be Rail grouping. The maximum voltage detection algorithm can still be run on other platforms with no Rail grouping and does not harm as it gives the same result. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: OMAP5+: vcores: Drop unnecessary #ifndefsLokesh Vutla2016-08-20-6/+3
| | | | | | | | | | | | | | | | | | | | gpio_en field is introduced to detect if pmic is controlled by GPIO. Make this field 0 on all TPS659* pmics available on DRA7/OMAP5 based platforms and remove the #ifndefs. Reviewed-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | cmd: Split 'bootz' and 'booti' out from 'bootm'Tom Rini2016-08-20-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | The bootz and booti commands rely on common functionality that is found in common/bootm.c and common/bootm_os.c. They do not however rely on the rest of cmd/bootm.c to be implemented so split them into their own files. Have various Makefiles include the required infrastructure for CONFIG_CMD_BOOT[IZ] as well as CONFIG_CMD_BOOTM. Move the declaration of 'images' over to common/bootm.c. Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-08-16-37/+426
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| * | x86: Add theadorable-x86-dfi-bt700 board supportStefan Roese2016-08-16-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the BayTrail based theadorable-x86-dfi-bt700 board which uses the DFI BT700 BayTrail Qseven SoM on a custom baseboard. The main difference to the DFI baseboard is, that it isn't equipped with a Super IO chip and uses the internal HS SIO UART (memory mapped PCI based) as the console UART. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Add DFI BT700 BayTrail board supportStefan Roese2016-08-16-0/+335
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the DFI BayTrail BT700 QSeven SoM installed on the DFI Q7X-151 baseboard. The baseboard is equipped with the Nuvoton NCT6102D Super IO chip providing the UART as console. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: conga-qeval20-qa3: Add SMBus support and SMSC2513 config codeStefan Roese2016-08-16-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch includes the following changes: - Remove Designware I2C support from dts as its not used - Configure SMBus PADs in dts - Enable I2C commands and I2C support - Configure SMSC2513 USB hub via SMBus upon startup - Move environment location to match Minnowmax example - Enhancement of the default environment Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | i2c: intel_i2c: SMBus driver PCI addition (e.g. BayTrail)Stefan Roese2016-08-16-26/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the SMBus block read/write functionality. Other protocols like the SMBus quick command need to get added if this is needed. This patch also removed the SMBus related defines from the Ivybridge pch.h header. As they are integrated in this driver and should be used from here. This change is added in this patch to avoid compile breakage to keep the source git bisectable. Tested on a congatec BayTrail board to configure the SMSC2513 USB hub. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de> Cc: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | x86: som-db5800-som-6867: fix SERIRQ on resetGeorge McCollister2016-08-16-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Explicitly enable ILB_SERIRQ function 1 in cfio_regs_pad_ilb_serirq_PCONF0. Pad configuration for SERIRQ is not set to enable the SERIRQ function after a reset though strangely, it is on initial boot. Rebooting from Linux, reset command in u-boot and even pushing the reset button on the development board all lead to the SERIRQ function being disabled (address 0xfed0c560 with value of 0x2003cc80). Signed-off-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: baytrail: Add SIO HS-UART clock setupStefan Roese2016-08-16-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support the BayTrail internal SIO HS UART, the internal UART clock needs to get configured. This patch adds support for this clock configuration which will be done, if the PCI device(s) are found. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: cache.h: Add default for CONFIG_SYS_CACHELINE_SIZEStefan Roese2016-08-16-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't just define ARCH_DMA_MINALIGN but also CONFIG_SYS_CACHELINE_SIZE if it's undefined. This is needed for the xhci driver to compile. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | ARM: dts: k2g-evm: enable mmc/sd suppportSekhar Nori2016-08-16-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The K2G EVM from TI has an SD card slot as well as onboard eMMC for data storage. Enable support for these. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Acked-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: dts: K2G: Add support for MMC controllerSekhar Nori2016-08-16-0/+23
|/ / | | | | | | | | | | | | | | | | K2G SoC from TI has two MMC/SD controllers. Add device tree data for these. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Acked-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | xtensa: add support for the 'xtfpga' evaluation boardChris Zankel2016-08-15-0/+263
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'xtfpga' board is actually a set of FPGA evaluation boards that can be configured to run an Xtensa processor. - Avnet Xilinx LX60 - Avnet Xilinx LX110 - Avnet Xilinx LX200 - Xilinx ML605 - Xilinx KC705 These boards share the same components (open-ethernet, ns16550 serial, lcd display, flash, etc.). Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | xtensa: add core information for the de212 processorMax Filippov2016-08-15-0/+839
| | | | | | | | | | | | | | | | | | | | DE212 is a general purpose xtensa processor without full MMU. Core information files are autogenerated from the processor description and are not meant to be edited. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | xtensa: add core information for the dc233c processorMax Filippov2016-08-15-0/+757
| | | | | | | | | | | | | | | | | | | | DC233C is an xtensa processor with full MMUv3 capable of running Linux. Core information files are autogenerated from the processor description and are not meant to be edited. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | xtensa: add core information for the dc232b processorChris Zankel2016-08-15-0/+674
| | | | | | | | | | | | | | | | | | | | | | DC232B is an xtensa processor with full MMUv2 capable of running Linux. Core information files are autogenerated from the processor description and are not meant to be edited. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | xtensa: add support for the xtensa processor architecture [2/2]Chris Zankel2016-08-15-0/+3107
| | | | | | | | | | | | | | | | | | | | | | | | | | The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | vexpress: Check TC2 firmware support before defaulting to nonsec bootingJon Medhurst \(Tixy\)2016-08-15-5/+10
| | | | | | | | | | | | | | | | | | | | The firmware on TC2 needs to be configured appropriately before booting in nonsec mode will work as expected, so test for this and fall back to sec mode if required. Signed-off-by: Jon Medhurst <tixy@linaro.org> Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-08-15-3/+1797
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| * | ARM: at91/dt: Add device tree for SAMA5D2 XplainedWenyou Yang2016-08-15-0/+874
| | | | | | | | | | | | | | | | | | Add device tree for SAMA5D2 Xplained board. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
| * | atmel: Bring in at91 pio4 device tree file and bindingsWenyou Yang2016-08-15-0/+880
| | | | | | | | | | | | | | | | | | | | | | | | Bring in required device tree file and bindings from Linux. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | gpio: atmel_pio4: Move PIO4 definitions to head fileWenyou Yang2016-08-15-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | In order to make these PIO4 definitions shared with AT91 PIO4 pinctrl driver, move them from the existing gpio driver to the head file, and rephrase them. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | clk: at91: Add clock driverWenyou Yang2016-08-15-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-08-15-38/+73
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| * | | net: mii: Changes not made by spatchJoe Hershberger2016-08-15-11/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the functions passed to the registration function are not in the same C file (extern) then spatch will not handle the dependent changes. Make those changes manually. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> For the 4xx related files: Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | | net: mii: Fix changes made by spatchJoe Hershberger2016-08-15-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the changes were a bit too complex. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-11-12 23:16:21 +0000