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| | * | malta: Use device model & tree for UARTPaul Burton2016-05-26-0/+37
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make use of device model & device tree to probe the UART driver. This is the initial step in bringing Malta up to date with driver model, and allows for cleaner handling of the different I/O addresses for different system controllers by specifying the ISA bus address instead of a translated memory address. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-05-25-202/+285
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| | * | sunxi: Enable a bunch of commands by default on sunxiHans de Goede2016-05-25-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recently a set of CONFIG_CMD_FOO defines was moved from being defined in config_distro_defaults to Kconfig, and added to all sunxi defconfigs to compensate. Instead of explictly selecting these in all sunxi defconfigs, simply always select these for sunxi boards. This makes the defconfigs simpler and ensures a consistent set of available commands across all sunxi boards. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * | arm64: Pine64: update FDT filesAndre Przywara2016-05-25-198/+255
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The originally committed .dts files for the Pine64 were from an early proof-of-concept version and should have never been committed upstream. Replace them with much more mature versions, which also use a different naming scheme. Please note that at this point there is at least one binding which has not been agreed upon, so this is subject to change. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * | sunxi: Properly announce BOOT_DEVICE_BOARD as "FEL"Bernhard Nortmann2016-05-25-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This addresses a cosmetic issue when booting a sunxi device over USB (FEL mode), where the SPL currently would just print "Trying to boot from ". The patch fixes that to properly read "Trying to boot from FEL". Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * | sunxi: Increase SPL header size to 64 bytes to avoid code corruptionSiarhei Siamashka2016-05-25-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current SPL header, created by the 'mksunxiboot' tool, has size 32 bytes. But the code in the boot ROM stores the information about the boot media at the offset 0x28 before passing control to the SPL. For example, when booting from the SD card, the magic number written by the boot ROM is 0. And when booting from the SPI flash, the magic number is 3. NAND and eMMC probably have their own special magic numbers too. Currently the corrupted byte is a part of one of the instructions in the reset vectors table: b reset ldr pc, _undefined_instruction ldr pc, _software_interrupt <- Corruption happens here ldr pc, _prefetch_abort ldr pc, _data_abort ldr pc, _not_used ldr pc, _irq ldr pc, _fiq In practice this does not cause any visible problems, but it's still better to fix it. As a bonus, the reported boot media type can be later used in the 'spl_boot_device' function, but this is out of the scope of this patch. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * | sunxi: power: add AXP809 supportChen-Yu Tsai2016-05-25-3/+4
| | |/ | | | | | | | | | | | | | | | | | | | | | The A80 uses the AXP809 as its primary PMIC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-05-25-21/+380
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| | * | ARM: uniphier: add EHCI nodes for PH1-LD11Masahiro Yamada2016-05-26-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | Make the USB feature really available. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| | * | ARM: uniphier: add PH1-LD11 SoC supportMasahiro Yamada2016-05-26-3/+312
| | | | | | | | | | | | | | | | | | | | | | | | This is a low-cost ARMv8 SoC from Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| | * | ARM: uniphier: rename UMC register macros of PH1-LD20Masahiro Yamada2016-05-26-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Correct some register names. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| | * | ARM: uniphier: rename umc-ld20-regs.h to umc64-regs.hMasahiro Yamada2016-05-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This header will be shared between PH1-LD11 and PH1-LD20 (and hopefully new ARMv8 SoCs developed in the future), so umc64-regs.h would be a better fit. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| | * | ARM: uniphier: clean up boot mode tablesMasahiro Yamada2016-05-26-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | Tidy up alignment of open parentheses. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| | * | ARM: uniphier: disable cache in SPL of PH1-LD20Masahiro Yamada2016-05-26-0/+2
| | |/ | | | | | | | | | | | | | | | | | | | | | The Boot ROM has enabled D-cache and MMU setting DDR memory area as Normal Memory in its page table. Disable D-cache and MMU before jumping to U-Boot proper. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2016-05-25-0/+27
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| | * powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cacheAneesh Bansal2016-05-24-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While enabling L2 cache, the value of L2PE (L2 cache parity/ECC error checking enable) must not be changed while the L2 cache is enabled. So, L2PE must be set before enabling L2 cache. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * powerpc: Disable flush or invalidate dcache by range for some SoCsYork Sun2016-05-19-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ac337168a unified functions to flush and invalidate dcache by range. These two functions were no-op for SoCs other than 4xx and MPC86xx. Adding these functions seemed to be correct but introduced issues when the dcache is flushed. While the root cause is under investigation, disable these functions for affected SoCs so various drivers can work. Signed-off-by: York Sun <york.sun@nxp.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-05-24-20/+109
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| | * | driver/ddr/fsl: Add workaround for erratum A-010165Shengzhou Liu2016-05-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During DDR-2133 operation, the transmit data eye margins determined during the memory controller initialization may be sub-optimal, set DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | crypto/fsl: add support for multiple SEC engines initializationAlex Porosanu2016-05-18-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For SoCs that contain multiple SEC engines, each of them needs to be initialized (by means of initializing among others the random number generator). Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | arch/arm, arch/powerpc: add # of SEC engines on the SOCAlex Porosanu2016-05-18-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SOCs, specifically the ones in the C29x familiy can have multiple security engines. This patch adds a system configuration define which indicates the maximum number of SEC engines that can be found on a SoC. Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | arch/arm: add SEC JR0 offsetAlex Porosanu2016-05-18-10/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts) Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | armv7: ls102xa: spl: fix the macro name of MMC modeQianyu Gong2016-05-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MMCSD_MODE_FAT has been renamed to MMCSD_MODE_FS by commit 205b4f33. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | armv8: fsl-layerscape: spl: fix the macro name of MMC modeQianyu Gong2016-05-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MMCSD_MODE_FAT has be renmaed to MMCSD_MODE_FS by commit 205b4f33. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | armv8: fsl-layerscape: spl: remove duplicate init_early_memctl_regs()Qianyu Gong2016-05-18-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | init_early_memctl_regs() is also be called in board_early_init_f(). So remove the duplicated call in spl code. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | armv8: fsl-layerscape: Remove unnecessary flushing dcacheAlison Wang2016-05-18-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | armv8/ls1043a: update the node for QSPI supportYuan Yao2016-05-18-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The address value and size value set for QSPI dts node "reg" property have type of u64 on arm64. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | armv8/fdt: add fixup_crypto_nodeAlex Porosanu2016-05-17-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Qoriq PPC&ARM v7 platforms, the crypto node is being fixup'ed in order to update the SEC internal version (aka SEC ERA). This patch adds the same functionality to the ARMv8 SoCs. Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | driver/ddr/fsl: Add workaround for erratum A-009801Shengzhou Liu2016-05-17-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| | * | armv8/ls1043: Add workaround for DDR erratum A-008850Shengzhou Liu2016-05-17-0/+37
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-05-24-1/+15
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: drivers/net/zynq_gem.c
| | * | arm: dts: dra7: fix ethernet name with proper device addressMugunthan V N2016-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix typo error for cpsw device name with proper device address Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| | * | arm: dts: dra7: add syscon node to cpsw to read mac addressMugunthan V N2016-05-24-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add syscon node to cpsw device node to read mac address from efuse. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| | * | arm: dts: am4372: add syscon node to cpsw to read mac addressMugunthan V N2016-05-24-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add syscon node to cpsw device node to read mac address from efuse. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| | * | ARM: omap5: add platform specific ethernet phy modes configurationsMugunthan V N2016-05-24-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add platforms specific phy mode configuration bits to be used to configure phy mode in control module. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-05-24-45/+150
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| | * | | ARM: zynq: Simplify zynq configurationMichal Simek2016-05-24-42/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extending Kconfig for adding new platform is a lot of work for nothing. Setting SYS_CONFIG_NAME directly in Kconfig and remove all dependencies on TARGET_ZYNQ_* options including SPL. As a side-effect it also remove custom init folder for ps7_init_gpl.* files. Folder is chosen based on device-tree file. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | | ARM64: zynqmp: Add SPL support supportMichal Simek2016-05-24-0/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support RAM and MMC boot mode in SPL also with SPL_FIT images. In MMC boot mode two boot options are available: 1) Boot flow with ATF(EL3) and full U-Boot(EL2): aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000 -d bl31.bin atf.ub cp spl/boot.bin <sdcard fat partition> cp atf.ub <sdcard fat partition> cp u-boot.bin <sdcard fat partition> 2) Boot flow with full U-Boot(EL3): cp spl/boot.bin <sdcard> cp u-boot*.img <sdcard> 3) emmc boot mode dd if=/dev/zero of=sd.img bs=1024 count=1024 parted sd.img mktable msdos parted sd.img mkpart p fat32 0% 100% kpartx -a sd.img mkfs.vfat /dev/mapper/loop0p1 mount /dev/mapper/loop0p1 /mnt/ cp spl/boot.bin /mnt cp u-boot.img /mnt cp u-boot.bin /mnt cp atf.ub /mnt umount /dev/mapper/loop0p1 kpartx -d sd.img cp sd.img /tftpboot/ and program it via u-boot tftpb 10000 sd.img mmcinfo mmc write 10000 0 $filesize mmc rescan mmc part ls mmc 0 psu_init() function contains low level SoC setup generated for every HW design by Xilinx design tools. xil_io.h is only supporting file to fix all dependencies from tools. The same solution was used on Xilinx Zynq. The patch also change CONFIG_SYS_INIT_SP_ADDR to the end of OCM which stays at the same location all the time. Bootrom expects starting address to be at 0xfffc0000 that's why this address is SPL_TEXT_BASE. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | | ARM64: zynqmp: Add missing u-boot,dm-pre-reloc to DTSIMichal Simek2016-05-24-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing u-boot,dm-pre-reloc to get IPs initialized. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | | ARM64: zynqmp: Align gic ranges for 64k in device treeAlexander Graf2016-05-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GIC ranges in the zynqmp device tree are only 4kb aligned. Since commit 12e14066f we automatically deal with aliases GIC regions though, so we can map them transparently into guests even on 64kb page size systems. This patch makes use of that features and sets GICC and GICV to 64kb aligned and sized regions. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | | ARM: zynq: Call ps7_post_config() for SPLMichal Simek2016-05-24-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If ps7_post_config() is defined call it. It is enabling for example level shifters for PL bitstreams. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | | ARM: zynq: Add support for SPL_LOAD_FITMichal Simek2016-05-24-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable minimal function to be able to compile SPL_LOAD_FIT. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | | ARM: dts: zynq: describe SLCR as simple-mfd rather than simple-busMasahiro Yamada2016-05-24-1/+1
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 9f56917ab88a ("dm: core: make simple-bus compatible to simple-mfd") made possible to import the following commit: Linux commit: bc5ba9b98435bf76d92e0954da1784695aa449f1 The SLCR (System-Level Control Registers) block is an MFD (Multi Function Device) rather than a bus. "simple-mfd" seems a more suitable compatible string than "simple-bus". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-05-24-1/+115
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| | * | | ARM: sama5d2: Implement boot device autodetectionMarek Vasut2016-05-24-1/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement support for saving ARM register R4 early during boot using save_boot_params . Implement support for decoding the stored register R4 value in spl_boot_device() to obtain boot device from which the SoC booted. This way, the SPL will always load U-Boot from the same device from which the SPL itself booted instead of using hard-coded boot device. This functionality is useful for example when booting sama5d2-xplained from SD card, where by default the SPL would try loading the U-Boot from eMMC and fail. This is because eMMC is on SDHCI0 (BOOT_DEVICE_MMC1), while SD slot is on SDHCI1 (BOOT_DEVICE_MMC2) and the SPL was hard-wired to always boot from BOOT_DEVICE_MMC1. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| | * | | ARM: at91: clock: complete the GCK's clock sourcesWenyou Yang2016-05-24-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the UPLL clock and master clock as a clock source for getting the generated clock frequency to complete its clock sources support. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| | * | | ARM: at91: clock: fix the GCK's clock sourceWenyou Yang2016-05-24-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before enabling a generated clock whose source is from the UPLL clock, check and enable the UPLL clock. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| | * | | board: atmel: add SAMA5D2 PTC Engineering boardWenyou Yang2016-05-24-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board supports following features: - Boot media support: NAND Flash/SPI Flash - Support ethernet - Support USB mass storage Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| | * | | ARM: at91: sama5d2: add macro & field definitionsWenyou Yang2016-05-24-0/+29
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | They will be used on SAMA5D2 PTC board. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-05-23-7891/+9259
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