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* arm64: Allow EFI payload code to take exceptionsAlexander Graf2016-03-15-0/+9
| | | | | | | | | | | | | | | There are 2 ways an EFI payload could return into u-boot: - Callback function - Exception While in EFI payload mode, x18 is owned by the payload and may not contain a valid pointer to gd, so we need to fix it up. We do that properly for the payload to callback path already. This patch also adds gd pointer restoral for the exception path. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm64: Allow exceptions to returnAlexander Graf2016-03-15-0/+34
| | | | | | | | | | | | | | Our current arm64 exception handlers all panic and never return to the exception triggering code. But if any handler wanted to continue execution after fixups, it would need help from the exception handling code to restore all registers. This patch implements that help. With this code, exception handlers on aarch64 can successfully return to the place the exception happened (or somewhere else if they modify elr). Signed-off-by: Alexander Graf <agraf@suse.de>
* efi_loader: Add runtime servicesAlexander Graf2016-03-15-0/+54
| | | | | | | | | | | | | | | | | After booting has finished, EFI allows firmware to still interact with the OS using the "runtime services". These callbacks live in a separate address space, since they are available long after U-Boot has been overwritten by the OS. This patch adds enough framework for arbitrary code inside of U-Boot to become a runtime service with the right section attributes set. For now, we don't make use of it yet though. We could maybe in the future map U-boot environment variables to EFI variables here. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* arm64: Only allow dcache disabled in SPL buildsAlexander Graf2016-03-15-0/+9
| | | | | | | | | Now that we have an easy way to describe memory regions and enable the MMU, there really shouldn't be anything holding people back from running with caches enabled on AArch64. To make sure people catch early if they're missing on the caching fun, give them a compile error. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm64: Remove non-full-va map codeAlexander Graf2016-03-15-216/+85
| | | | | | | | | | | By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de>
* tegra: Replace home grown mmu code with generic table approachAlexander Graf2016-03-15-115/+17
| | | | | | | Now that we have nice table driven page table creating code that gives us everything we need, move to that. Signed-off-by: Alexander Graf <agraf@suse.de>
* zymqmp: Replace home grown mmu code with generic table approachAlexander Graf2016-03-15-169/+48
| | | | | | | Now that we have nice table driven page table creating code that gives us everything we need, move to that. Signed-off-by: Alexander Graf <agraf@suse.de>
* thunderx: Move mmu table into board fileAlexander Graf2016-03-15-5/+5
| | | | | | | | | The MMU range table can vary depending on things we may only find out at runtime. While the very simple ThunderX variant does not change, other boards will, so move the definition from a static entry in a header file to the board file. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm64: Make full va map code more dynamicAlexander Graf2016-03-15-100/+494
| | | | | | | | | | | | | | | | | | | The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm64: Disable TTBR1 maps in EL1Alexander Graf2016-03-15-1/+2
| | | | | | | | | | | | When running in EL1, AArch64 knows two page table maps. One with addresses that start with all zeros (TTBR0) and one with addresses that start with all ones (TTBR1). In U-Boot we don't care about the high up maps, so just disable them to ensure we don't walk an invalid page table by accident. Reported-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* thunderx: Calculate TCR dynamicallyAlexander Graf2016-03-15-6/+59
| | | | | | | | Based on the memory map we can determine a lot of hard coded fields of TCR, like the maximum VA and max PA we want to support. Calculate those dynamically to reduce the chance for pit falls. Signed-off-by: Alexander Graf <agraf@suse.de>
* omap4: Check warm reset for reboot mode validityPaul Kocialkowski2016-03-15-0/+4
| | | | | | | Since the SAR registers are filled with garbage on cold reset, this checks for a warm reset to assert the validity of reboot mode. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Reboot mode supportPaul Kocialkowski2016-03-15-0/+49
| | | | | | | | | | Reboot mode is written to SAR memory before reboot in the form of a string. This mechanism is supported on OMAP4 by various TI kernels. It is up to each board to make use of this mechanism or not. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Properly enable USB PHY clocksPaul Kocialkowski2016-03-15-1/+9
| | | | | | | This correctly enables the USB PHY clocks, by enabling CM_ALWON_USBPHY_CLKCTRL and correctly setting CM_L3INIT_USBPHY_CLKCTRL's value. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap-common: clocks-common: Setup USB DPLL when MUSB is in usePaul Kocialkowski2016-03-15-2/+4
| | | | | | | | On (at least) OMAP4, the USB DPLL is required to be setup for the internal PHY to work properly. The internal PHY is used by default with the MUSB USB OTG controller. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* Amazon Kindle Fire (first generation) codename kc1 supportPaul Kocialkowski2016-03-15-0/+4
| | | | | | | | | | The Amazon Kindle Fire (first generation) codename kc1 is a tablet that was released by Amazon back in 2011. It is using an OMAP4430 SoC GP version, which allows running U-Boot and the U-Boot SPL from the ground up. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Move i2c clocks enable to enable_basic_clocksPaul Kocialkowski2016-03-15-4/+4
| | | | | | | I2C is often enabled withing the U-Boot SPL, thus those clocks are required to be enabled early (especially when the bootrom doesn't enable them for us). Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Remove duplicate CM_L3INIT_USBPHY_CLKCTRL reference and whitespacePaul Kocialkowski2016-03-15-2/+1
| | | | | | | This removes a duplicate reference to CM_L3INIT_USBPHY_CLKCTRLin enable_basic_uboot_clocks. Also, a doubled whitespace is removed. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap-common: Remove deprecated arch_cpu_init codePaul Kocialkowski2016-03-15-13/+0
| | | | | | | save_omap_boot_params is called from spl_board_init in the SPL context. Thus, there is no reason to duplicate that call on arch_cpu_init. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap-common: Rename set_muxconf_regs_essential to set_muxconf_regsPaul Kocialkowski2016-03-15-4/+4
| | | | | | | There is no distinction between essential and non-essential mux configuration, so it doesn't make sense to have an "essential" prefix. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Export jedec sdram timingsPaul Kocialkowski2016-03-15-2/+4
| | | | | | | Individual boards might provide their own emif_get_device_timings function and use the jedec timings in their own way, hence those have to be exported. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Export elpidia sdram timingsPaul Kocialkowski2016-03-15-1/+6
| | | | | | | Individual boards might provide their own emif_get_device_timings function and use the elpidia timings in their own way, hence those have to be exported. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Export elpidia sdram device detailsPaul Kocialkowski2016-03-15-2/+7
| | | | | | | | | Individual boards might provide their own emif_get_device_details function and use elpidia device details in their own way, hence those have to be exported. This also wraps existing definitions with the proper ifdef logic. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap3: Use a define for reboot reason offsetPaul Kocialkowski2016-03-15-3/+7
| | | | | | | | This introduces a define for the offset to the reboot reason, rather than hardcoding it. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap3: String-based reboot mode handlingPaul Kocialkowski2016-03-15-6/+12
| | | | | | | | This switches reboot mode handling to a string-based interface, that allows more flexibility to set a common interface with the next generations of OMAP devices. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2016-03-15-2/+156
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| * imx: mx6: hdmi: handle overflow conditionPeng Fan2016-03-14-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | If HDMI_IH_FC_STAT2_OVERFLOW_MASK is set, we need to do TMDS software reset and write to clear fc_invidconf register. We need minimum 3 times to write to clear the fc_invidconf register, so choose 5 loops here. Signed-off-by: Peng Fan <van.freenix@gmail.com> Signed-off-by: Sandor Yu <sandor.yu@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
| * rockchip: video: Add LVDS support in vop driverJacob Chen2016-03-14-0/+1
| | | | | | | | | | | | | | | | | | | | LVDS have a different display out mode, add code to get right flag. The vop_ip decide display device and the remote_vop_id decide which vop was being used. So we should use the remote_vop_id to set DCLK_VOP. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: dts: Add LVDS supportJacob Chen2016-03-14-1/+46
| | | | | | | | | | | | | | Add these node to be used in rockchip LVDS and VOP driver. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: video: Add a display driver for rockchip LVDSJacob Chen2016-03-14-0/+97
| | | | | | | | | | | | | | | | Some Rockchip SoCs support LVDS output. Add a display driver for this so that these displays can be used on supported boards. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-03-14-24/+14
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| * | dm: Use uclass_first_device_err() where it is usefulSimon Glass2016-03-14-24/+14
| |/ | | | | | | | | | | Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm64: define _image_binary_end to fix SPL_OF_CONTROLMasahiro Yamada2016-03-14-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To make SPL_OF_CONTROL work on ARM64 SoCs, _image_binary_end must be defined in the linker script. LD spl/u-boot-spl lib/built-in.o: In function `fdtdec_setup': lib/fdtdec.c:1186: undefined reference to `_image_binary_end' lib/fdtdec.c:1186: undefined reference to `_image_binary_end' make[1]: *** [spl/u-boot-spl] Error 1 make: *** [spl/u-boot-spl] Error 2 Note: CONFIG_SPL_SEPARATE_BSS must be defined as well on ARM64 SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7: Move emif settings to board specific filesLokesh Vutla2016-03-14-147/+2
| | | | | | | | | | | | | | | | | | | | The newer versions of DRA7 boards has EEPROM populated with DDR size specified in it. Moving DRA7 specific emif related settings to board files so that emif settings can be identified based on EEPROM. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: DRA7: Enable EEPROM supportLokesh Vutla2016-03-14-0/+1
| | | | | | | | | | | | | | | | Enable EEPROM support for DRA74-evm. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | ARM: Various: Future-proof serial platdataAdam Ford2016-03-14-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few boards still use ns16550_platdata structures, but assume the structure is going to be in a specific order. By explicitly naming each entry, this should also help 'future-proof' in the event the structure changes. Tested on the Logic PD Torpedo + Wireless. I only changed a handful of devices that used the same syntax as the Logic board. Appologies if I missed one or stepped on toes. Thanks to Derald Woods and Alexander Graf. Signed-off-by: Adam Ford <aford173@gmail.com> V6: Add fix to arch/arm/cpu/armv7/am33xx/board.c V5: Add fix to arch/arm/cpu/arm926ejs/lpc32xx/devices.c V4: Fix subject heading V3: Remove reg_offset out in all the structs. It was reverted out, and and if it did exist, it would get initialized to 0 by default. V2: I hastily copy-pasted the boards without looking at the UART number. This addresses 3 boards that use UART3 and not UART1. Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | ARM: OMAP4+: Allow arch specfic code to use early DMLokesh Vutla2016-03-14-9/+21
| | | | | | | | | | | | | | | | | | | | | | Early system initialization is being done before initf_dm is being called in U-Boot. Then system will fail to boot if any of the DM enabled driver is being called in this system initialization code. So, rearrange the code a bit so that DM enabled drivers can be called during early system initialization. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7: emif: Enable interleaving for higher address spaceLokesh Vutla2016-03-14-0/+5
| | | | | | | | | | | | | | | | Given that DRA7/OMAP5 SoCs can support more than 2GB of memory, enable interleaving for this higher memory to increase performance. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7: emif: Check for enable bits before updating leveling outputLokesh Vutla2016-03-14-24/+54
| | | | | | | | | | | | | | | | | | Read and write leveling can be enabled independently. Check for these enable bits before updating the read and write leveling output values. This will allow to use the combination of software and hardware leveling. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7: emif: Fix DDR init sequence during warm resetLokesh Vutla2016-03-14-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit (20fae0a - ARM: DRA7: DDR: Enable SR in Power Management Control) enables Self refresh mode by default and during warm reset the EMIF contents are preserved. After warm reset EMIF sees that it is idle and puts DDR in self-refresh. When in SR, leveling operations cannot be done as DDR can only accept SR exit command, so its hanging during warm reset. In order to fix this reset the power management control register before EMIF initialization if it is a warm reset. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7: emif: Fix updating of refresh ctrl shadowLokesh Vutla2016-03-14-1/+5
| | | | | | | | | | | | | | | | On DRA7, refresh ctrl shadow should be updated with the final value. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: keystone2: use detected ddr3a sizeVitaly Andrianov2016-03-14-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because KS2 u-boot works in 32 bit address space the existing ram_size global data field cannot be used. The maximum, which the get_ram_size() can detect is 2GB only. The ft_board_setup() needs the actual ddr3 size to fix up dtb. This commit introduces the ddr3_get_size() which uses SPD data to calculate the ddr3 size. This function replaces the "ddr3_size" environment variable, which was used to get the SODIMM size. For platforms, which don't have SODIMM with SPD and ddr3 is populated to a board a simple ddr3_get_size function that returns ddr3 size has to be implemented. See hardware-k2l.h Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: keystone2: use SPD info to configure K2HK and K2E DDR3Vitaly Andrianov2016-03-14-0/+463
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit replaces hard-coded EMIF and PHY DDR3 configurations for predefined SODIMMs to a calculated configuration. The SODIMM parameters are read from SODIMM's SPD and used to calculated the configuration. The current commit supports calculation for DDR3 with 1600MHz and 1333MHz only. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: keystone2: K2G: Add support for different arm/device speedsLokesh Vutla2016-03-14-4/+11
| | | | | | | | | | | | | | | | | | | | The maximum device and arm speeds can be determined by reading EFUSE_BOOTROM register. As there is already a framework for reading this register, adding support for all possible speeds on k2g devices. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: keystone2: Allow for board specific speed definitionsLokesh Vutla2016-03-14-8/+8
| | | | | | | | | | | | | | | | | | | | Its not compulsory that speed definition should be same on EFUSE_BOOTROM register for all keystone 2 devices. So, allow for board specific speed definitions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: keystone2: K2G: power-off DSP during bootSuman Anna2016-03-14-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | The DSPs are powered on by default upon a Power ON reset, and they are powered off on current Keystone 2 SoCs - K2HK, K2L, K2E during the boot in u-boot. This is not functional on K2G though. Extend the existing DSP power-off support to the only DSP present on K2G. Do note that the PSC clock domain module id for DSP on K2G differs from that of previous Keystone2 SoCs. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: keystone2: Use macro for DSP GEM power domainSuman Anna2016-03-14-1/+2
| | | | | | | | | | | | | | | | | | | | Define a macro for the DSP GEM power domain id number and use it instead of a hard-coded number in the code that disables all the DSPs on various Keystone2 SoCs. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: Add support for LEGO MINDSTORMS EV3David Lechner2016-03-14-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | This is based on the davinci da850evm. It can boot from either the on-board 16MB flash or from a microSD card. It also reads board information from an I2C EEPROM. The EV3 itself initally boots from write-protected EEPROM, so no u-boot SPL is needed. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: dts: k2g: Add support for PMMCNishanth Menon2016-03-14-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable support for PMMC the TI power processor on K2G. This processor manages all power management related activities on the SoC and and allows the Operating Systems on compute processors such as ARM, DSP to offload the power logic away into the power processor. U-boot just has a load responsibility, hence the view of the hardware from a bootloader perspective is different from the view of hardware from a Operating System perspective. While bootloader just loads up the firmware, Operating Systems look at the resultant system as "hardware". Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: keystone2: psc: introduce function to hold and release module in reset.Nishanth Menon2016-03-14-0/+108
| | | | | | | | | | | | | | | | | | These are useful for modules that need to be held in reset and are enabled for data to be loaded on to them. Typically these are microcontrollers or other processing entities in the system. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-10-30 17:28:30 +0000