summaryrefslogtreecommitdiff
path: root/arch
Commit message (Collapse)AuthorAgeLines
* board: Add Qualcomm Dragonboard 410C supportMateusz Kulikowski2016-04-01-0/+198
| | | | | | | | | | | | | | | | | | | | | | This commit add support for 96Boards Dragonboard410C. It is board based on APQ8016 Qualcomm SoC, complying with 96boards specification. Features (present out of the box): - 4x Cortex A53 (ARMv8) - 2x USB Host port - 1x USB Device port - 4x LEDs - 1x HDMI connector - 1x uSD connector - 3x buttons (Power, Vol+, Vol-/Reset) - WIFI, Bluetooth with integrated antenna - 8GiB eMMC U-Boot boots chained with fastboot in 64-bit mode. For detailed build instructions see readme.txt in board directory. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Tested-by: Simon Glass <sjg@chromium.org>
* arm: Add support for Qualcomm Snapdragon familyMateusz Kulikowski2016-04-01-0/+383
| | | | | | | | | | | First supported chip is APQ8016 (that is compatible with MSM8916). Drivers in SoC code: - Reset controller (PSHOLD) - Clock controller (very simple clock configuration for MMC and UART) Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* spmi: Add sandbox test driverMateusz Kulikowski2016-04-01-0/+40
| | | | | | | | This patch adds emulated spmi bus controller with part of pm8916 pmic on it to sandbox and tests validating SPMI uclass. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* usb: Rename ehci-fsl.h to ehci-ci.hMateusz Kulikowski2016-04-01-1/+1
| | | | | | | | | | | | | Most of ehci-fsl header describe USB controller designed by Chipidea and used by various SoC vendors. This patch renames it to a generic header: ehci-ci.h Contents of file are not changed (so it contains several references to freescale SoCs). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
* sniper: Change vendor name from lge to lg, matching devicetree vendor prefixPaul Kocialkowski2016-04-01-1/+1
| | | | | | | This moves the sniper board from the lge to lg, in order to match the devicetree vendor prefix already defined in the kernel. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* arm: spl: Align default board_init_f comment with codeAndreas Dannenberg2016-04-01-1/+1
| | | | | | | | The default board_init_f() implementation performs a call to board_init_r() as the last step of the sequence. Fix the comment for this function to reflect the actual execution flow. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
* rpi: BCM2837 and Raspberry Pi 3 32-bit supportStephen Warren2016-04-01-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Raspberry Pi 3 contains a BCM2837 SoC. The BCM2837 is a BCM2836 with the CPU complex swapped out for a quad-core ARMv8. This can operate in 32- or 64-bit mode. 32-bit mode is the current default selected by the VideoCore firmware on the Raspberry Pi 3. This patch adds a 32-bit port of U-Boot for the Raspberry Pi 3. >From U-Boot's perspective, the only delta between the RPi 2 and RPi 3 is a change in usage of the SoC UARTs. On all previous Pis, the PL011 was the only UART in use. The Raspberry Pi 3 adds a Bluetooth module which uses a UART to connect to the SoC. By default, the PL011 is used for this purpose since it has larger FIFOs than the other "mini" UART. However, this can be configured via the VideoCore firmware's config.txt file. This patch hard-codes use of the mini UART in the RPi 3 port. If your system uses the PL011 UART for the console even on the RPi 3, please use the RPi 2 U-Boot port instead. A future change might determine which UART to use at run-time, thus allowing the RPi 2 and RPi 3 (32-bit) ports to be squashed together. The mini UART has some limitations. One externally visible issue in the BCM2837 integration is that the UART divides the SoC's "core clock" to generate the baud rate. The core clock is typically variable, and under control of the VideoCore firmware for thermal management reasons. If the VC FW does modify the core clock rate, UART communication will be corrupted since the baud rate will vary from the expected value. This was not an issue for the PL011 UART, since it is fed by a fixed 3MHz clock. To work around this, the VideoCore firmware can be told not to modify the SoC core clock. However, the only way this can happen and be thermally safe is to limit the core clock to a low/minimum frequency. This leaves performance on the table for use-cases that don't care about a UART console. Consequently, use of the mini UART console must be explicitly requested by entering the following line into config.txt: enable_uart=1 A recent version of the VC firmware is required to ensure that the mini UART is fully and correctly initialized by the VC FW; at least firmware.git 046effa13ebc "firmware: arm_loader: emmc clock depends on core clock See: https://github.com/raspberrypi/firmware/issues/572". Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: bcm2835: expand Kconfig target descriptionsStephen Warren2016-04-01-1/+27
| | | | | | | | This adds an explanation of which Raspberry Pi models each target option supports. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: bcm2835: move CONFIG_BCM283* to KconfigStephen Warren2016-04-01-1/+11
| | | | | Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: keystone2: Add missing privilege ID settingsNishanth Menon2016-04-01-1/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing Privilege ID settings for KS2 SoCs. Based on: K2H/K: Table 6-7. Privilege ID Settings from SPRS866E (Nov 2013) http://www.ti.com/lit/ds/symlink/66ak2h14.pdf (page 99) K2L: Table 7-7. Privilege ID Settings from SPRS930 (April 2015) http://www.ti.com/lit/ds/symlink/66ak2l06.pdf (page 71) K2E: Table 7-7. Privilege ID Settings from SPRS865D (Mar 2015) http://www.ti.com/lit/ds/symlink/66ak2e05.pdf (page 75) K2G: Table 3-16. PrivIDs from SPRUHY8 (Jan 2016) http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf (page 238) Overall mapping: -------+-----------+-----------+-----------+--------- PrivID | KS2H/K | K2L | K2E | K2G -------+-----------+-----------+-----------+--------- 0 | C66x 0 | C66x 0 | C66x 0 | C66x 0 1 | C66x 1 | C66x 1 | Reserved | ARM 2 | C66x 2 | C66x 2 | Reserved | ICSS0 3 | C66x 3 | C66x 3 | Reserved | ICSS1 4 | C66x 4 | Reserved | Reserved | NETCP 5 | C66x 5 | Reserved | Reserved | CPIE 6 | C66x 6 | Reserved | Reserved | USB 7 | C66x 7 | Reserved | Reserved | Reserved 8 | ARM | ARM | ARM | MLB 9 | NetCP | NetCP | NetCP | PMMC 10 | QM_PDSP | QM_PDSP | QM_PDSP | DSS 11 | PCIe_0 | PCIe_0 | PCIe_0 | MMC 12 | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP 13 | Reserved | Reserved | PCIe_1 | Reserved 14 | HyperLink | PCIe_1 | HyperLink | Reserved 15 | Reserved | Reserved | TSIP | Reserved -------+-----------+-----------+-----------+--------- NOTE: Few of these might have default configurations, however, since most are software configurable, it is better to explicitly configure the system to have a known default state. Without programming these, we end up seeing lack of coherency on certain peripherals resulting in inexplicable failures (such as USB peripheral's DMA data not appearing on ARM etc and weird workarounds being done by drivers including cache flushes which tend to have system wide performance impact). By marking these segments as shared, we also ensure SoC wide coherency is enabled. Reported-by: Bin Liu <b-liu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: keystone2: Refactor MSMC macros to avoid #ifdefferyNishanth Menon2016-04-01-23/+53
| | | | | | | | | | | | | | | MSMC segment Privilege ID is not consistent accross the keystone2 SoCs. As the first step to ensure complete SoC wide coherency setup, lets refactor the macros to remove the #if-deffery around the code which obfuscates which IDs are actually enabled for which SoC. As a result of this change the PCIe configuration is moved after the msmc configuration is complete, but that should ideally have no functional impact. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: clang: Update support slightlyTom Rini2016-04-01-1/+8
| | | | | | | | | | | - Move most of the flags required into LLVM_RELFLAGS to test at build time instead of requiring them to be passed in. - Update doc/README.clang to reflect this - Switch to rpi_2 as the example as it's closer to working out of the box than rpi is. Cc: Jeroen Hofstee <jeroen@myspectrum.nl> Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-04-01-63/+1011
|\
| * sunxi: Add Pine64+ supportSiarhei Siamashka2016-04-01-0/+203
| | | | | | | | | | | | | | | | | | | | | | | | | | The Pine64+ is a system based on the Allwinner A64 SoC. It is capable of running AArch64 code and thus is the first of its kind for the sunxi target. This patch adds a defconfig and device tree chunks for it. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> [agraf: Change patch description] Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Add support for Allwinner A64 SoCsSiarhei Siamashka2016-04-01-6/+608
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A64 SoC is used in the Pine64. This patch adds all bits necessary to compile U-Boot for it running in AArch64 mode. Unfortunately SPL is not ready yet due to legal problems, so we need to boot using the binary boot0 for now. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> [agraf: remove SPL code, move to AArch64] Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Explicitly cast u32 pointer conversionsAlexander Graf2016-04-01-4/+4
| | | | | | | | | | | | | | | | | | | | | | Some parts of the sunxi code cast explicitly between u32 values and pointers. This is not a problem in practice, because all 64bit SoCs today only use the lower 32 bits for their phyical address space. But we need to make sure that the compiler is sure this is not an accident as well. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Depend SPL configs on SUPPORT_SPLAlexander Graf2016-04-01-2/+2
| | | | | | | | | | | | | | | | | | | | We currently depend SPL config options on specific machine types which doesn't scale. Fortunately there's already a kconfig variable that tells us whether we want to build SPL code at all, so just depend them on this. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Move cpu independent code to mach directoryAlexander Graf2016-04-01-37/+52
| | | | | | | | | | | | | | | | | | | | | | | | Some of the code in arch/arm/cpu/armv7/sunxi is actually armv7 specific, while most of it is just generic code that could as well be used on an AArch64 SoC. Move all files that are not really tied to armv7 into a new mach-sunxi directory. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Enable USB nodes for H8Homlet v2Chen-Yu Tsai2016-04-01-0/+12
| | | | | | | | | | | | | | | | | | This provides the minimal changes to the H8Homlet v2 dts to enable USB in U-boot. It is not what will be submitted to the kernel. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Enable USB on Cubietruck PlusChen-Yu Tsai2016-04-01-0/+12
| | | | | | | | | | | | | | | | | | This provides the minimal changes to the Cubietruck Plus dts to enable USB in U-boot. It is not what will be submitted to the kernel. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Add USB and R_PIO nodes to sun8i-a83t.dtsiChen-Yu Tsai2016-04-01-0/+34
| | | | | | | | | | | | | | | | | | This provides the minimal changes to the A83T dtsi to enable USB in U-boot. It is not what will be submitted to the kernel. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: clk: Fix USB PHY clock macros for A83TChen-Yu Tsai2016-03-31-3/+3
| | | | | | | | | | | | | | | | | | The A83T has 3 PHYs, the last one being HSIC, which has 2 clocks. Also there is only 1 OHCI. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: usb_phy: Add support for A83T USB PHYsChen-Yu Tsai2016-03-31-2/+46
| | | | | | | | | | | | | | | | | | The A83T has 3 USB PHYs: 1 for USB OTG, 1 for standard USB 1.1/2.0 host, 1 for USB HSIC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Print soc-id from sram controller for sun8i boardsHans de Goede2016-03-31-5/+19
| | | | | | | | | | | | | | | | | | As the need for various magic sram pokes has shown this maybe useful info to have. e.g. this shows one of my a23 tablets having an id of 1661 rather then the usual 1650 for the a23. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Add conditional magic sram poke for A33Hans de Goede2016-03-31-4/+16
| | | | | | | | | | | | | | | | | | I noticed that for certain SoC versions boot0 does a magic poke when build for A33. I'm not aware of this actually being necessary anywhere, but better safe then sorry. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | cosmetic: Fix typos "privide"Masahiro Yamada2016-04-01-7/+7
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: rename function names ph1_* to uniphier_*Masahiro Yamada2016-04-01-193/+197
| | | | | | | | | | | | | | Eliminate the "ph1"_ prefixes from function names because "uniphier_" describes the SoC familiy better. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: add pin-mux settings for NAND, eMMC, SD of PH1-sLD3Masahiro Yamada2016-04-01-0/+23
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: enable eMMC on PH1-sLD3 reference boardMasahiro Yamada2016-04-01-0/+4
| | | | | | | | | | | | | | On PH1-sLD3, eMMC and NAND are assigned to different I/O pins. Both devices can be enabled at the same time. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: adjust dram_init() and dram_init_banksize() for ARM64Masahiro Yamada2016-04-01-10/+35
| | | | | | | | | | | | | | | | | | | | | | Currently, these functions assume #address-cells and #size-cells are both one. Fix them to support 64bit DTB. Also, I am fixing a buffer overrun bug while I am here. The array size of gd->bd->bd_dram is CONFIG_NR_DRAM_BANKS. The number of iteration in the loop should be limited by that CONFIG. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: dts: uniphier: add NAND pinmux nodeMasahiro Yamada2016-04-01-0/+5
| | | | | | | | | | | | This will be used to set up pin-muxing for the NAND controller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: dts: uniphier: add clock-frequency to serial nodes of LD11/LD20Masahiro Yamada2016-04-01-0/+8
|/ | | | | | | | Since no clock driver is implemented for peripherals in U-Boot yet, this property is needed for the serial driver to set up the divisor register. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-03-29-0/+2
|\
| * ARM: tegra210: set PLLE_PTS bit when enabling PLLEStephen Warren2016-03-29-0/+2
| | | | | | | | | | | | | | | | This bit needs to be set for system suspend/resume to work. This setting will be documented in an updated TRM at some time in the future. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-03-29-8/+124
|\ \
| * | armv8/ls2080ardb: Enable VID supportRai Harninder2016-03-29-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | This patch enable VID support for ls2080ardb platform. It uses the common VID driver. Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/ls1043aqds: dts: Set SPI mode for DSPIQianyu Gong2016-03-29-1/+7
| | | | | | | | | | | | | | | | | | | | | Clock phase and polarity for DSPI flash need to be set. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Add LS1023A SVRMingkai Hu2016-03-29-0/+2
| | | | | | | | | | | | | | | | | | Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Fix LS1043A SVR registerMingkai Hu2016-03-29-1/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-lsch3: Disable SMMU during secure bootSaksham Jain2016-03-29-1/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During secure boot, SMMU is enabled on POR by SP bootrom. SMMU needs to be put in bypass mode in uboot to enable CAAM transcations to pass through. For non-secure boot, SP BootROM doesn't enable SMMU, which is in bypass mode out of reset. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080: Add config for endianess of CCSR GURSaksham Jain2016-03-29-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GUR (DCFG) registers in CCSR space are in little endian format. Define a config CONFIG_SYS_FSL_CCSR_GUR_LE in arch/arm/include/asm/arch-fsl-layerscape/config.h Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080: Change env variable "fdt_high"Saksham Jain2016-03-29-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "fdt_high" env variable was set to 0xcfffffff for secure boot. Change it to 0xa0000000 for LS2080 to be consistent with non-secure boot targets. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-lsch3: Copy Bootscript and header from NOR to DDRSaksham Jain2016-03-29-3/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To unify steps for secure boot for xip (eg. NOR) and non-xip memories (eg. NAND, SD), bootscipts and its header are copied to main memory. Validation and execution are performed from there. For other ARM Platforms (ls1043 and ls1020), to avoid disruption of existing users, this copy step is not used for NOR boot. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080: Add bootscript header addr for secure bootSaksham Jain2016-03-29-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During secure boot, Linux image along with other images are validated using bootscript. This bootscript also needs to be validated before it executes. This requires a header for bootscript. When secure boot is enabled, default bootcmd is changed to first validate bootscript using the header and then execute the script. For ls2080, NOR memory map is different from other ARM SoCs. So a new address on NOR is used for this bootscript header (0x583920000). The Bootscript address is mentioned in this header along with addresses of other images. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080rdb: ls2080qds: Add secure boot supportSaksham Jain2016-03-29-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sec_init has been called at the beginning to initialize SEC Block (CAAM) which is used by secure boot validation later for both ls2080a qds and rdb. 64-bit address in ESBC Header has been enabled. Secure boot defconfigs are created for boards (NOR boot). Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-lsch3: Add new header for secure bootSaksham Jain2016-03-29-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For secure boot, a header is used to identify key table, signature and image address. A new header structure is added for lsch3. Currently key extension (IE) feature is not supported. Single key feature is not supported. Keys must be in table format. Hence, SRK (key table) must be present. Max key number has increase from 4 to 8. The 8th key is irrevocable. A new barker Code is used. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080: Add configs for SEC, SecMon, SRK and DCFGSaksham Jain2016-03-29-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add configs for various IPs used during secure boot. Add address and endianness for SEC and Security Monitor. SRK are fuses in SFP (fuses for public key's hash). These are stored in little endian format. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080: Add SFP Configs for LS2080Saksham Jain2016-03-29-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | In LS2080, SFP has version 3.4. It is in little endian. The base address is 0x01e80200. SFP is used in Secure Boot to read fuses. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Skip reconfigure QSPI clock when booting from QSPIQianyu Gong2016-03-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The qspi_cfg register is set by PBI when booting from QSPI. No need to changing it again. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | dm: i2c: mxc_i2c: implement i2c_idle_busPeng Fan2016-03-28-0/+10
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement i2c_idle_bus in driver, then setup_i2c can be dropped for boards which enable DM_I2C/DM_GPIO/PINCTRL. The i2c_idle_bus force bus idle flow follows setup_i2c in arch/arm/imx-common/i2c-mxv7.c This patch is an implementation following linux kernel patch: " commit 1c4b6c3bcf30d0804db0d0647d8ebeb862c6f7e5 Author: Gao Pan <b54642@freescale.com> Date: Fri Oct 23 20:28:54 2015 +0800 i2c: imx: implement bus recovery Implement bus recovery methods for i2c-imx so we can recover from situations where SCL/SDA are stuck low. Once i2c bus SCL/SDA are stuck low during transfer, config the i2c pinctrl to gpio mode by calling pinctrl sleep set function, and then use GPIO to emulate the i2c protocol to send nine dummy clock to recover i2c device. After recovery, set i2c pinctrl to default group setting. " See Documentation/devicetree/bindings/i2c/i2c-imx.txt for detailed description. 1. Introuduce scl_gpio/sda_gpio/bus in mxc_i2c_bus. 2. Discard the __weak attribute for i2c_idle_bus and implement it, since we have pinctrl driver/driver model gpio driver. We can use device tree, but not let board code to do this. 3. gpio state for mxc_i2c is not a must, but it is recommended. If there is no gpio state, driver will give tips, but not fail. 4. The i2c controller was first probed, default pinctrl state will be used, so when need to use gpio function, need to do "pinctrl_select_state(dev, "gpio")" and after force bus idle, need to switch back "pinctrl_select_state(dev, "default")". This is example about how to use the gpio force bus idle function: " &i2c1 { clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; status = "okay"; [....] }; [.....] pinctrl_i2c1_gpio: i2c1grp_gpio { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 >; }; " Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com>
generated by cgit v1.1 at 2024-11-01 17:15:07 +0000