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| * | armv7: add appropriate headers for assembly functionsAneesh V2012-05-15-49/+58
| | | | | | | | | | | | | | | | | | | | | | | | Use ENTRY and ENDPROC with assembly functions to ensure necessary assembler directives for all functions. Signed-off-by: Aneesh V <aneesh@ti.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
| * | arm: adapt asm/linkage.h from LinuxAneesh V2012-05-15-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | This will add ARM specific over-rides for the defines from linux/linkage.h Signed-off-by: Aneesh V <aneesh@ti.com> Tested-by: Mike Frysinger <vapier@gentoo.org>
| * | OMAP5: reset: Use cold reset in case of 5430ES1.0SRICHARAN R2012-05-15-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | Warm reset is not functional in case of omap5430ES1.0. So override the weak reset_cpu function to use cold reset instead. Signed-off-by: R Sricharan <r.sricharan@ti.com>
| * | OMAP3+: reset: Create a common reset layer.SRICHARAN R2012-05-15-41/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | The reset.S has the function to do a warm reset on OMAP based socs. Moving this to a reset.c file so that this acts a common layer to add any reset related functionality for the future. Signed-off-by: R Sricharan <r.sricharan@ti.com>
| * | omap5: pbias ldo9 turn onBalaji T K2012-05-15-3/+4
| | | | | | | | | | | | | | | | | | | | | Add omap5 pbias configuration for mmc1/sd lines and set voltage for sd data i/o lines Signed-off-by: Balaji T K <balajitk@ti.com>
| * | arm: omap5: correct boot device mode7 for eMMCBalaji T K2012-05-15-1/+6
| | | | | | | | | | | | | | | | | | | | | In OMAP5 Boot device mode of 6 and 7 should be mapped to mmc2/eMMC Signed-off-by: Balaji T K <balajitk@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
| * | OMAP4/5: emif: Correct the emif power mgt shadow register bit fields.SRICHARAN R2012-05-15-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | PD_TIM bit field which specifies the power down timing is defined to occupy bits 8-11, where as it is actually from 12-15 bits. So correcting this. Signed-off-by: R Sricharan <r.sricharan@ti.com>
| * | OMAP5: ddr: Change the ddr device name.SRICHARAN R2012-05-15-16/+16
| | | | | | | | | | | | | | | | | | | | | The ddr part name used in OMAP5 ES1.0 soc is a SAMSUNG part and not a ELPIDA part. So change this. Signed-off-by: R Sricharan <r.sricharan@ti.com>
| * | OMAP4/5: device: Add support to get the device type.SRICHARAN R2012-05-15-1/+13
| | | | | | | | | | | | | | | | | | Add support to identify the device as GP/EMU/HS. Signed-off-by: R Sricharan <r.sricharan@ti.com>
| * | OMAP4/5: Make the sysctrl structure commonSRICHARAN R2012-05-15-14/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make the sysctrl structure common, so that it can be used in generic functions across socs. Also change the base address of the system control module, to include all the registers and not simply the io regs. Signed-off-by: R Sricharan <r.sricharan@ti.com>
| * | OMAP5: SRAM: Change the SRAM base address.SRICHARAN R2012-05-15-1/+1
| | | | | | | | | | | | | | | | | | | | | The full internal SRAM of size 128kb is public in the case of OMAP5 soc. So change the base address accordingly. Signed-off-by: R Sricharan <r.sricharan@ti.com>
| * | OMAP4/5: Make the silicon revision variable common.SRICHARAN R2012-05-15-25/+19
| | | | | | | | | | | | | | | | | | | | | | | | The different silicon revision variable names was defined for OMAP4 and OMAP5 socs. Making the variable common so that some code can be made generic. Signed-off-by: R Sricharan <r.sricharan@ti.com>
| * | OMAP5: hwinit: Add the missing break statementSRICHARAN R2012-05-15-0/+1
| | | | | | | | | | | | | | | | | | | | | The break statement is missing in init_omap_revision function, resulting in a wrong revision identification. So fixing this. Signed-off-by: R Sricharan <r.sricharan@ti.com>
| * | OMAP5: palmas: Configure nominal opp vdd valuesSRICHARAN R2012-05-15-23/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The nominal opp vdd values as recommended for ES1.0 silicon is set for mpu, core, mm domains using palmas. Also used the right sequence to enable the vcores as per a previous patch from Nishant Menon, which can be dropped now. http://lists.denx.de/pipermail/u-boot/2012-March/119151.html Signed-off-by: R Sricharan <r.sricharan@ti.com>
| * | OMAP5: emif/ddr: Change emif settings as required for ES1.0 silicon.SRICHARAN R2012-05-15-28/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | The OMAP5 silicon has new DDR PHY design, which includes a external PHY as well. So configuring the ext PHY parameters here. Also the EMIF timimg registers and a couple of DDR mode registers needs to be updated based on the testing from the actual silicon. Signed-off-by: R Sricharan <r.sricharan@ti.com>
| * | OMAP5: io: Configure the io settings for omap5430 sevm board.SRICHARAN R2012-05-15-24/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | The control module provides options to set various signal integrity parameters like the output impedance, slew rate, load capacitance for different pad groups. Configure these as required for the omap5430 sevm board. Signed-off-by: R Sricharan <r.sricharan@ti.com>
| * | OMAP5: board: Add pinmux data for omap5_evm board.SRICHARAN R2012-05-15-252/+250
| | | | | | | | | | | | | | | | | | Adding the full pinmux data for OMAP5430 sevm board. Signed-off-by: R Sricharan <r.sricharan@ti.com>
| * | OMAP5: clocks: Change clock settings as required for ES1.0 silicon.SRICHARAN R2012-05-15-39/+94
| | | | | | | | | | | | | | | | | | | | | | | | Aligning all the clock related settings like the dpll frequencies, their respective clock outputs, etc to the ideal values recommended for OMAP5430 ES1.0 silicon. Signed-off-by: R Sricharan <r.sricharan@ti.com>
| * | OMAP4: scale voltage of core before MPU scalesNishanth Menon2012-05-15-28/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP4 requires that parent domains scale ahead of dependent domains. This is due to the restrictions in timing closure. To ensure a consistent behavior across all OMAP4 SoC, ensure that vdd_core scale first, then vdd_mpu and finally vdd_iva. As part of doing this refactor the logic to allow for future addition of OMAP4470 without much ado. OMAP4470 uses different SMPS addresses and cannot be introduced in the current code without major rewrite. Reported-by: Isabelle Gros <i-gros@ti.com> Reported-by: Jerome Angeloni <j-angeloni@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
| * | OMAP4460: TPS Ensure SET1 is selected after voltage configurationNishanth Menon2012-05-15-5/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms. Currently we control this pin with a mux configuration as part of boot sequence. Current configuration results in the following voltage waveform: |---------------| (SET1 default 1.4V) | --------(programmed voltage) | <- (This switch happens on mux7,pullup) vdd_mpu(TPS) -----/ (OPP boot voltage) --------- (programmed voltage) vdd_core(TWL6030) -----------------------/ (OPP boot voltage) Problem 1) |<----- Tx ------>| timing violation for a duration Tx close to few milliseconds. Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP. By using GPIO as recommended as standard procedure by TI, the sequence changes to: -------- (programmed voltage) vdd_mpu(TPS) ------------/ (Opp boot voltage) --------- (programmed voltage) vdd_core(TWL6030) -------------/ (OPP boot voltage) NOTE: This does not attempt to address OMAP5 - Aneesh please confirm Reported-by: Isabelle Gros <i-gros@ti.com> Reported-by: Jerome Angeloni <j-angeloni@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
| * | OMAP3+: Introduce generic logic for OMAP voltage controllerNishanth Menon2012-05-15-75/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP Voltage controller is used to generically talk to PMICs on OMAP3,4,5 over I2C_SR. Instead of replicating code in multiple SoC code, introduce a common voltage controller logic which can be re-used from elsewhere. With this change, we replace setup_sri2c with omap_vc_init which has the same functionality, and replace the voltage scale replication in do_scale_vcore and do_scale_tps62361 with omap_vc_bypass_send_value. omap_vc_bypass_send_value can also now be used with any configuration of PMIC. NOTE: Voltage controller controlling I2C_SR is a write-only data path, so no register read operation can be implemented. Reported-by: Isabelle Gros <i-gros@ti.com> Reported-by: Jerome Angeloni <j-angeloni@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
| * | ARM:OMAP+:MMC: Add parameters to MMC initJonathan Solnit2012-05-15-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add parameters to the OMAP MMC initialization function so the board can mask host capabilities and set the maximum clock frequency. While the OMAP supports a certain set of MMC host capabilities, individual boards may be more restricted and the OMAP may need to be configured to match the board. The PRG_SDMMC1_SPEEDCTRL bit in the OMAP3 is an example. Signed-off-by: Jonathan Solnit <jsolnit@gmail.com>
| * | serial: add LPC32X0 high-speed UART devices supportVladimir Zapolskiy2012-05-15-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds an implementation of high-speed UART found on NXP LPC32X0 SoCs. Such UARTs are enumerated as UART1, UART2 and UART7. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Marek Vasut <marek.vasut@gmail.com>
| * | arm926ejs: add NXP LPC32x0 cpu series supportVladimir Zapolskiy2012-05-15-0/+985
| |/ | | | | | | | | | | | | | | This change adds initial support for NXP LPC32x0 SoC series. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Marek Vasut <marek.vasut@gmail.com>
* | mmc: support the sdhci instead of s5p_mmc for samsung-socJaehoon Chung2012-05-08-92/+94
|/ | | | | | | | | | | | In driver mmc, generic s5p_sdhci code is implemented. s5p_mmc file is dupulicated. we are good that use the generic sdhci. This patch supported the sdhci for Samsung-SoC. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Lei Wen<leiwen@marvell.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2012-04-30-197/+635
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mpc85xx: powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSR powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot cmd_bdinfo: display the address map size (32-bit vs. 36-bit) PowerPC: correct the SATA for p1/p2 rdb-pc platform powerpc/corenet_ds: Slave core in holdoff when boot from SRIO powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO powerpc/corenet_ds: Slave uploads ucode when boot from SRIO powerpc/corenet_ds: Slave module for boot from SRIO powerpc/corenet_ds: Master module for boot from SRIO powerpc/corenet_ds: Document for the boot from SRIO powerpc/corenet_ds: Correct the compilation errors about ENV powerpc/srio: Rewrite the struct ccsr_rio powerpc/85xx:Fix lds for nand boot debug info powerpc/p2041rdb: add env in NAND support powerpc/p2041rdb: add NAND and NAND boot support powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards powerpc/85xx:Avoid vector table compilation for nand_spl powerpc/85xx:Fix IVORs addr after vector table relocation powerpc/85xx:Avoid hardcoded vector address for IVORs powerpc/p1023rds: Disable nor flash node and enable nand flash node
| * powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSRTimur Tabi2012-04-24-2/+6
| | | | | | | | | | | | | | The CCSR relocation code in start.S writes to MAS7 on all e500 parts, but that register does not exist on e500v1. Signed-off-by: Timur Tabi <timur@freescale.com>
| * powerpc/corenet_ds: Slave core in holdoff when boot from SRIOLiu Gang2012-04-24-0/+131
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When boot from SRIO, slave's core can be in holdoff after powered on for some specific requirements. Master can release the slave's core at the right time by SRIO interface. Master needs to: 1. Set outbound SRIO windows in order to configure slave's registers for the core's releasing. 2. Check the SRIO port status when release slave core, if no errors, will implement the process of the slave core's releasing. Slave needs to: 1. Set all the cores in holdoff by RCW. 2. Be powered on before master's boot. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
| * powerpc/corenet_ds: Slave reads ENV from master when boot from SRIOLiu Gang2012-04-24-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When boot from SRIO, slave's ENV can be stored in master's memory space, then slave can fetch the ENV through SRIO interface. NOTE: Because the slave can not erase, write master's NOR flash by SRIO interface, so it can not modify the ENV parameters stored in master's NOR flash using "saveenv" or other commands. Master needs to: 1. Put the slave's ENV into it's own memory space. 2. Set an inbound SRIO window covered slave's ENV stored in master's memory space. Slave needs to: 1. Set a specific TLB entry in order to fetch ucode and ENV from master. 2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
| * powerpc/corenet_ds: Slave uploads ucode when boot from SRIOLiu Gang2012-04-24-4/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When boot from SRIO, slave's ucode can be stored in master's memory space, then slave can fetch the ucode image through SRIO interface. For the corenet platform, ucode is for Fman. Master needs to: 1. Put the slave's ucode image into it's own memory space. 2. Set an inbound SRIO window covered slave's ucode stored in master's memory space. Slave needs to: 1. Set a specific TLB entry in order to fetch ucode from master. 2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
| * powerpc/corenet_ds: Master module for boot from SRIOLiu Gang2012-04-24-2/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. For the master module, need to finish these processes: 1. Initialize the SRIO port and address space. 2. Set inbound SRIO windows covered slave's u-boot image stored in master's NOR flash. 3. Master's u-boot image should be generated specifically by make xxxx_SRIOBOOT_MASTER_config 4. Master must boot first, and then slave can be powered on. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
| * powerpc/srio: Rewrite the struct ccsr_rioLiu Gang2012-04-24-160/+270
| | | | | | | | | | | | | | Rewrite this struct for the support of two ports and two message units registers. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
| * powerpc/85xx:Fix lds for nand boot debug infoPrabhakar Kushwaha2012-04-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently "u-boot", the elf file generated via u-boot-nand.lds does not contain required debug information i.e. .debug_{line, info, abbrev, aranges, ranges} into their respective _global_ sections. The original ld script line arch/powerpc/cpu/mpc85xx/start.o KEEP(*(.bootpg)) is not entirely correct because the start.o file is already processed by the linker,therefore the file wildcard in "KEEP(*(.bootpg))" will not process start.o again for bootpg. So Fix u-boot-nand.lds to generate these debug information. Signed-off-by: Anmol Paralkar <b07584@freescale.com> Signed-off-by: John Russo <John.Russo@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx:Avoid vector table compilation for nand_splPrabhakar Kushwaha2012-04-24-0/+6
| | | | | | | | | | | | | | | | NAND SPL code never compile the vector table. So no need to setup interrupt vector table for NAND SPL. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx:Fix IVORs addr after vector table relocationPrabhakar Kushwaha2012-04-24-0/+33
| | | | | | | | | | | | | | | | | | | | | | After relocation of vector table in SDRAM's lower address, IVORs value should be updated with new handler addresses. As vector tables are relocated to 0x100,0x200... 0xf00 address in DDR.IVORs are updated with 0x100, 0x200,....f00 hard-coded values. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * powerpc/85xx:Avoid hardcoded vector address for IVORsPrabhakar Kushwaha2012-04-24-31/+34
| | | | | | | | | | | | | | | | | | | | | | | | For e500 and e500v2 architecturees processor IVPR address should be alinged on 64K boundary. in start.S, CONFIG_SYS_MONITOR_BASE is stored blindly in IVPR assuming it to be 64K aligned. It may not be true always. If it is not aligned, IVPR + IVORs may not point to an exception handler. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2012-04-30-146/+0
|\ \ | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-i2c: i2c:designware Turn off the ctrl when setting the speed i2c: Add support for designware i2c controller sh: i2c: Add support I2C controller of SH7734
| * | i2c: Add support for designware i2c controllerVipin KUMAR2012-04-24-146/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | Earlier, a driver exists in the u-boot source for designware i2c interface. That driver was specific to spear platforms. This patch implements the i2c controller as a generic driver which can be used by multiple platforms The driver files are now renamed to designware_i2c.c and designware_i2c.h and these are moved into drivers/i2c folder for reusability by other platforms Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2012-04-30-24/+44
|\ \ | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-blackfin: Blackfin: bfin_sdh: drop dos part hardcode Blackfin: move gd/bd to bss by default Blackfin: gd_t: relocate volatile markings
| * | Blackfin: move gd/bd to bss by defaultMike Frysinger2012-04-22-23/+43
| | | | | | | | | | | | | | | | | | | | | | | | We don't need these setup manually, so let the bss do the rest. On Blackfin systems, we clear the bss before executing any C code that would use these, so this should be fine. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: gd_t: relocate volatile markingsMike Frysinger2012-04-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This makes Blackfin behave the same as other ports, and fixes many gcc warnings that show up with 4.5+: board.c:40:1: warning: optimization may eliminate reads and/or writes to register variables Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-nds32Wolfgang Denk2012-04-30-0/+969
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-nds32: board/adp-ag102: add configuration of adp-ag102 board/adp-ag102: add board specific files nds32/ag102: add ag102 soc support nds32/ag102: add header support of ag102 soc
| * | | nds32/ag102: add ag102 soc supportMacpaul Lin2012-04-22-0/+804
| | | | | | | | | | | | | | | | | | | | | | | | Add lowlevel ag102 soc support. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
| * | | nds32/ag102: add header support of ag102 socMacpaul Lin2012-04-22-0/+165
| |/ / | | | | | | | | | | | | | | | | | | | | | Add device address offsets header of ag102 soc. Add ag102 into mach-types.h. Add asm-offsets.c for helping convert C headers into asm. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
* | | Merge branch 'marex@denx.de' of git://git.denx.de/u-boot-stagingWolfgang Denk2012-04-29-1/+1
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'marex@denx.de' of git://git.denx.de/u-boot-staging: CMD: CONFIG_CMD_SETECPR -> CONFIG_CMD_SETEXPR on omap3_logic CMD: Fix CONFIG_CMD_SAVEBP_WRITE_SIZE -> CONFIG_CMD_SPL_WRITE_SIZE CMD: Fix typo CMD_FSL -> CMD_MFSL in readme HWW1U1A: Fix CMD_SHA1 -> CMD_SHA1SUM CMD: Remove CMD_LOG, it's unused CMD: Fix typo KGBD -> KGDB on debris board CMD: Drop CONFIG_CMD_EMMC, it's not used CMD: Drop CONFIG_CMD_DFL, it's not used CMD: Drop CMD_DCR, it's not used CMD: Drop CMD_CAN, it's not used CMD: Remove CMD_AUTOSCRIPT, it's not used AT91: Drop AT91_SPIMUX command from cmd_all
| * | CMD: Fix CONFIG_CMD_SAVEBP_WRITE_SIZE -> CONFIG_CMD_SPL_WRITE_SIZEMarek Vasut2012-04-19-1/+1
| |/ | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: scottwood@freescale.com
* | sandbox: Use the new run_command()Simon Glass2012-04-23-6/+0
| | | | | | | | | | | | | | | | Now that run_command() handles both parsers, clean up sandbox to use it. This fixes a build error. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
* | arm: restore fdt_fixup_ethernet call to do_bootm_linuxStephen Warren2012-04-23-0/+1
| | | | | | | | | | | | | | | | | | | | Commit 0a672d4 "arm: Add Prep subcommand support to bootm" re-organized do_bootm_linux for ARM. During the re-organization, the call to fdt_fixup_ethernet() was removed. I assume this was useful, so add it back. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Tom Rini <trini@ti.com>
* | arm: fix bootm with device treeStephen Warren2012-04-23-1/+10
|/ | | | | | | | | | | | Commit 0a672d4 "arm: Add Prep subcommand support to bootm" re-organized do_bootm_linux() for ARM. During the re-organization, the code to pass the device tree to the kernel was removed. Add it back. This restores the ability to boot a kernel using device tree. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Tom Rini <trini@ti.com> Acked-by: Allen Martin <amartin@nvidia.com> Tested-by: Allen Martin <amartin@nvidia.com>
* Prepare v2012.04-rc2; minor Coding Style cleanupWolfgang Denk2012-04-16-1/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
generated by cgit v1.1 at 2024-11-06 03:40:09 +0000