summaryrefslogtreecommitdiff
path: root/arch
Commit message (Collapse)AuthorAgeLines
* MLK-14483 mx7ulp: Fix SPLL/APLL clock rate calculation issueYe Li2017-03-17-2/+6
| | | | | | | | The num/denom is a float value, but in the calculation it is convert to integer 0, and cause the result wrong. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 4a8f51499ca098637e9ee2036066374d34458865)
* MLK-14481 mx7ulp: Fix build issue when using M4 boot configurationYe Li2017-03-17-1/+1
| | | | | | | | Wrong SIZE_64K and SIZE_128K are used, and cause build break. Fix them in the patch. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit ef2a8a4d7e0c4557abf50dadb6f149afd5bfe956)
* MLK-14417 imx: Enable ACTLR.SMP bit for all i.MX cortex-a7 platformsYe Li2017-03-14-7/+41
| | | | | | | | | | | | According to the Cortex-A7 TRM, for ACTLR.SMP bit "You must ensure this bit is set to 1 before the caches and MMU are enabled, or any cache and TLB maintenance operations are performed". ROM sets this bit in normal boot flow, but when in serial download mode, it is not set. Here we add it in u-boot as a common flow for all i.MX cortex-a7 platforms, including mx7d, mx6ul/ull and mx7ulp. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 14990af03450f3e1898135c86fd8b93328007617)
* MLK-14312 mx7ulp: Fix incorrect DTB modification after using USBYe Li2017-03-02-16/+43
| | | | | | | | | | | | | | u-boot has feature that when booting for mfgtool, the u-boot will modify the DTB to disable SD 1.8v switch. But the judgement for mfgtool boot has a problem, it only checks whether the USB PHY power status is enabled. When a USB device (for example a USB ethernet) is used in u-boot, the power status is also enabled. So the u-boot incorrectly disable the SD 1.8v switch. The patch changes the get_boot_device to use the boot SW info provided by ROM. Only if it is a USB boot, we will start the DTB modification for SD. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 1fb61cd80af59c39d1ca01d833f566628ba48f32)
* MLK-13929-6 mx7ulp_evk: Enable the MIPI DSI splashscreenYe Li2017-02-16-1/+2
| | | | | | | Enable and setup board level codes for MIPI DSI splashscreen on EVK board. User needs set env variable"panel=HX8363_WVGA" for displaying. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13929-5 mx7ulp: Update clock and SoC functions for videoYe Li2017-02-16-0/+88
| | | | | | | | Add the clocks functions for enabling LCDIF and DSI clocks. Also add the arch_preboot_os to disable the video before enter into the kernel. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13929-4 mx7ulp: Update registers and memory map for DSI and LCDIFYe Li2017-02-16-3/+12
| | | | | | | Update the registers base address and LCDIF registers structure for mx7ulp. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13923 mx7ulp: Fix PCC register bits mask and offset issueYe Li2017-02-14-2/+2
| | | | | | | The offset for FRAC and the mask for PCD are not correct. If we set FRAC, we can't get the right frequency. Fix them to correct value. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13899 ARM: mx7ulp: Correct the clock index on imx7ulpBai Ping2017-02-09-1/+2
| | | | | | | | On i.MX7ULP, value zero is reserved in SCG1 RCCR register, so the val should be decreased by 1 to get the correct clock source index. Signed-off-by: Bai Ping <ping.bai@nxp.com>
* MLK-10647 armv7: Fix Dcache disable issue on i.MX7Ye.Li2017-02-08-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The issue on the i.MX7D is that, there is one cache-able memory access between the L1 and L2 cache flush by calling the flush_dache_all-> v7_maint_dcache_all() [Flush L1 and L2 cache) which written in the C code. L1-cache-flush -> This will flush L1 cache to L2 cache in the end. Cache-able memory access -> This will have the chance cause the L1 line-fill with dirty data from L2 cache(L1 cache-line dirty, L2 clean) L2-cache-flush -> This will only flush L2 cache to L3, but still some dirty data on the L1 cacheline. After C & M bit clean, -> The dirty data on the L1 cache line lost, which will cause memory coherent issue if that dirty cache line has some useful data The only problem here is: there is one cache-cable memory access between L1 and L2 cache flush. This patch should works fine on the i.MX6 and i.MX7. The second cache flush have zero impact on the i.MX6, but this is really need for the i.MX7D platform due to the L1 line-fill during the first dcache_flush. And the second flush will not bring in the L1 dirty cache line due to the C bit is clear now, which means the dcache is disabled. Acked-by: Jason Liu<r64343@freescale.com> Reviewed-by: Jason Liu<r64343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit f5d5f07fba936c4bb05c887de9d72fb75b3dc0f2) (cherry picked from commit 86c784cf4c4b633d37a76de7d47155c08f75dc82) (cherry picked from commit d85cd484e6825631aa1ab572e5e0539f2191d795)
* MA-9213 imx: mx7ulp-evk: Add android supportSanshan Zhang2017-01-25-0/+64
| | | | | | | | | Add android features on i.MX7ULP EVK board. Implement the code to get boot device and the serial number on mx7ulp. TODO: will add the code which check misc partition after porting BCB. Change-Id: I9d06fecba303fa4dfdcaf73da1b6246444697bba Signed-off-by: Sanshan Zhang <sanshan.zhang@nxp.com>
* MLK-13723 imx7d: restore epdc QoS setting after exit the lpsr modeRobby Cai2017-01-23-0/+5
| | | | | | | | without this patch, the QoS setting will be lost after exit LPSR mode. The patch moves the QoS setting into DDR setting group (in plugin mode), thus when exit LPSR mode, QoS setting will be restored as well as DDR setting. Signed-off-by: Robby Cai <robby.cai@nxp.com>
* MLK-13761 board: imx7ulp: Fix system reset after a7 rtc alarm expired.Bai Ping2017-01-20-0/+7
| | | | | | | | The board will reboot if A7 core enter mem mode by rtc, then M4 core enter VLLS mode after the RTC alarm expired. Enable the dumb PMIC mode to fix this issue. Signed-off-by: Bai Ping <ping.bai@nxp.com>
* MLK-13645 mx7ulp: Modify FDT file to disable SD3.0 for mfgtoolYe Li2016-12-23-0/+38
| | | | | | | | | Since the SD3.0 kernel driver needs M4 image support, this causes problem to mfgtool. To decouple the relationship, we modify the FDT file in u-boot to disable SD3.0 when booting for mfgtool. So the kernel won't depend on M4 image. Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Fugang Duan <fugang.duan@nxp.com>
* MLK-13602-1 mx6: Add i.MX6ULL fused modules checking supportYe Li2016-12-14-1/+44
| | | | | | | Add the modules disable fuses mapping with FDT nodes and devices name. Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Bai Ping <ping.bai@nxp.com>
* MLK-13546 mx7ulp_arm2: Add validation board supportYe Li2016-12-02-0/+9
| | | | | | | | | | | | | This patch addes board level codes for MX7ULP ARM2 board. Since only 14x14 ARM2 board is ready, we only support this board. 10x10 board will support in future. eMMC/SD1/UART are ready in this patch. Other modules need board rework to test. Build target: mx7ulp_14x14_arm2_config Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13545 mx7ulp: Add HAB boot supportYe Li2016-12-01-0/+21
| | | | | | | | | | Add CAAM clock functions, SEC_CONFIG[1] fuse checking, and default CSF size for HAB support boot on mx7ulp. Users need to uncomment the CONFIG_SECURE_BOOT in mx7ulp_evk.h to build secure uboot. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13544 mx7ulp: Modify MX7ULP arch codes to use imx-commonYe Li2016-12-01-39/+24
| | | | | | | | This patch modifies MX7ULP arch codes to reuse some functions already in imx-common, like cache and HAB. To do this, we need to add a dummy SOC type and chip type for MX7ULP and its relevant checking. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13532 misc: ocotp: ulp: fix fuse readPeng Fan2016-11-29-0/+1
| | | | | | | There is no hole in i.MX7ULP1 OCOTP space, so the phy_index is the same one with index. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13525-1 mx7ulp: Add common plugin codes for mx7ulpYe Li2016-11-25-0/+105
| | | | | | | Add common plugin codes to call ROM's hwcnfg_setup and generate IVT2 header. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-19 imx: mx7ulp_evk: Add EVK boards support codesYe Li2016-11-22-0/+11
| | | | | | | | | | | | | | Add basic support for i.MX7ULP EVK board. I2C, SD/eMMC, UART, QSPI and USB are added. Use target mx7ulp_evk_config to select the configuration. Use mx7ulp_evk_emmc_config for eMMC boot. Use mx7ulp_evk_m4boot_config for binding and booting m4 image in single boot mode. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13450-12 gpio: Add Rapid GPIO2P driver for i.MX7ULPYe Li2016-11-22-0/+22
| | | | | | | | | | | | | | Add the imx_rgpio2p driver for Rapid GPIO2P controllers on i.MX7ULP. Have added all ports on RGPIO2P_0 and RGPIO2P_1. The configurations CONFIG_IMX_RGPIO2P and CONFIG_DM_GPIO must be set to y to enable the drivers. To use the GPIO function, the IBE and OBE needs to set in IOMUXC. We did not set the bits in driver, but leave them to IOMUXC settings of the GPIO pins. User should use IMX_GPIO_NR to generate the GPIO number for gpio APIs access. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-11 mx7ulp: Implement the clock functions for i2c driverYe Li2016-11-22-0/+44
| | | | | | | Implement the i2c clock enable and get function for mx7ulp. These functions are required by imx_lpi2c driver. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-9 mx7ulp: Add lpuart DM device and clock supportYe Li2016-11-22-3/+45
| | | | | | | Add the DM device and re-implement the imx_get_uartclk according to the LPUART_BASE configuration. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-8 serial_lpuart: Add 32LE support for i.MX7ULPYe Li2016-11-22-0/+42
| | | | | | | | | | | | | Modify the lpuart to support the register access in little endian way with 32bits for i.MX7ULP. Need to enable CONFIG_LPUART_32LE_REG for the using. Also add the lpuart_fsl register structure and registers bits definitions in registers header file. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Teo Hall <teo.hall@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
* MLK-13450-7 mx7ulp: Add M4 core boot support when using single boot modeYe Li2016-11-22-0/+40
| | | | | | | | | | | | | | | | | | The single boot mode in MX7ULP will only boot up A7, the M4 is running in ROM by checking entry from SIM0 GP register. In this patch, We bind M4 image with u-boot.bin before attaching the imx header. So the whole image (included M4 image) will be loaded by A7 ROM into DDR. Then when u-boot is up, it will try to load M4 image into TCML and boot it there. Since M4 image will not be relocated in u-boot codes, we must load it during board_f. Current implementation put it in arch_cpu_init to get M4 booted as quick as possible. We requires the M4 image with IVT head and padding embedded, not a RAW binary. The image should be same as what is used for M4 QSPI boot in dual boot mode. Signed-off-by: Ye Li <ye.li@nxp.com>
* MLK-13450-6 mx7ulp: Add soc level initialization codes and functionsYe Li2016-11-22-1/+322
| | | | | | | | | | | | Implement soc level functions to get cpu rev, reset cause, enable cache, etc. We will disable the wdog and init clocks in s_init at very early u-boot phase. Since the we are seeking the way to get chip id for mx7ulp, the get_cpu_rev is hard coded to a fixed value. This may change in future. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13450-5 mx7ulp: Add clock framework and functionsYe Li2016-11-22-1/+2391
| | | | | | | | | | | | | | | | | Add a clock framework to support SCG1/PCC2/PCC3 for A7 to support get/set clock source, divider, clock rate and parent source. Users need to include pcc.h to use the APIs to for peripherals clock. Each peripheral clock is defined in enum pcc_clk type. SCG relevants APIs are defined in scg.h which supports clock rate get, PLL/PFD enablement and settings, and all SCG clock initialization. User need use enum scg_clk to access each clock source. In clock.c, we initialize necessary clocks at u-boot s_init and implement the clock functions used by driver modules to operate clocks dynamically. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13450-4 mx7ulp: Add iomux pins header fileYe Li2016-11-22-0/+910
| | | | | | | | | | | | Add the iomux pins header file from iomux tool team. Change the IOMUXC0 pins to add IOMUX_CONFIG_MPORTS flags. Note: The IOMUXC0 offset provided in this file is from 0xD000, this is not aligned with IOMUXC0 base address. We have adjusted the IOMUXC0 base address to aligin with it. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13450-3 mx7ulp: Add iomux driver to support IOMUXC0 and IOMUXC1Ye Li2016-11-22-0/+170
| | | | | | | | | | Add a new driver under ULP directory to support its IOMUXC controllers. The ULP has two IOMUXC, the IOMUXC0 is used for M4 domain, while IOMUXC1 is for A7. We set IOMUXC1 as the default IOMUX in this driver. Any pins in IOMUXC0 needs to configure with IOMUX_CONFIG_MPORTS in its mux_mode field. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13450-2 mx7ulp: Add registers address header fileYe Li2016-11-22-0/+1151
| | | | | | | | Add imx-regs.h for i.MX7ULP registers addresses definitions and some registers structures. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13450-1 mx7ulp: Add new i.MX series mx7ulp to KconfigYe Li2016-11-22-1/+19
| | | | | | | | | Since mx7ulp is a new series which have different architecture as previous i.MX platforms. We create a new cpu folder for it. This patch addes it to Kconfig. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
* MLK-13499 imx6sll: add epdc splash screen supportRobby Cai2016-11-21-1/+3
| | | | | | | add splash screen feature for epdc. it's tested on imx6sll arm2 board and evk board. Signed-off-by: Robby Cai <robby.cai@nxp.com>
* MLK-13476 imx: 6sx: fix ECSPI5 basePeng Fan2016-11-17-0/+2
| | | | | | ECSPI5 redefined. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13289 imx: mx6sxscm: generic mx6sxscm board supportJuan Gutierrez2016-10-26-0/+7
| | | | | | | | | | | | | | Provide the generic support for i.MX6SX SCM boards i.MX6SX SCM board file with the generic configuration, LPDDR2 memory calibration and build support is provided. - LPDDR2 memory configuration files for 1GB and 512MB. - plugin support for the above configurations. - driver support for: uart, qspi, i2c, usb, mmc. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
* MLK-13255 imx: mx6dqscm: generic mx6dqscm board supportJuan Gutierrez2016-10-21-0/+6
| | | | | | | | | | | | | Provide the generic support for i.MX6DQ SCM boards - LPDDR2 memory configuration files for 1GB, 2GB and 512MB. - plugin support for the above configurations. - fix and interleave memory mode (selected by CONFIG option) - driver support for: uart, spi, i2c, usb, sata and fec. - Android support Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com> Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
* MLK-13352 imx: mx6sll: support mx6sllevk boardPeng Fan2016-10-19-0/+7
| | | | | | | | | | Add mx6sll evk board support. USB/LCDIF/I2C/SD/EMMC/WDOG supported. The ddr script is from mx6sll lpddr3 arm2 board. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-15 imx: mx6sll: add mx6sll arm2 supportPeng Fan2016-10-11-0/+7
| | | | | | | | | | | Add mx6sll lpddr3/lpddr2 arm2 support. LCDIF/SPI/USB/PMIC supported. LPDDR3 DDR version: 1.2 LPDDR2 DDR version: initial version. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com>
* MLK-13307-14 imx-common: lcdif: update lcdif regs for i.MX6SLLPeng Fan2016-10-11-4/+5
| | | | | | | Update lcdif regs for i.MX6SLL Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-12 imx: mx6: update ccm macro settings for i.MX6SLLPeng Fan2016-10-11-6/+71
| | | | | | | Update CCM macros for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com>
* MLK-13307-9 imx: mx6sll: add Kconfig entry for i.MX6SLLPeng Fan2016-10-11-0/+4
| | | | | | add Kconfig entry for i.MX6SLL Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-8 imx-common: cache: configure L2 Cache for i.MX6SLLPeng Fan2016-10-11-1/+1
| | | | | | Configure L2 Cache for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-7 imx: mx6sll: update soc settingsPeng Fan2016-10-11-5/+16
| | | | | | Update soc settings for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-6 imx: mx6sll: add clock support for i.MX6SLLPeng Fan2016-10-11-36/+158
| | | | | | | Update clock settings for i.MX6SLL. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com>
* MLK-13307-5 imx: mx6sll: add iomux settingsPeng Fan2016-10-11-4/+10
| | | | | | | Add iomux settings for i.MX6 SLL Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye.Li <ye.li@nxp.com>
* MLK-13307-4 imx-common: timer: add i.MX6SLL supportPeng Fan2016-10-11-2/+4
| | | | | | Add i.MX6 SLL GPT timer support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-3 imx: mx6sll: update register addressPeng Fan2016-10-11-41/+52
| | | | | | Update register address for i.MX6 SLL Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-2 imx: mx6sll: add pinmux header filesPeng Fan2016-10-11-0/+1021
| | | | | | Add i.MX6SLL pinmux header files Signed-off-by: Peng Fan <peng.fan@nxp.com>
* MLK-13307-1 imx: Add MX6SLL CPU typePeng Fan2016-10-11-1/+4
| | | | | | | Add i.MX6SLL CPU type. MXC_CPU_MX6D is not a real value in chip, so change it to 0x6A. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* mx6: clock: Fix the logic for reading axi_alt_selFabio Estevam2016-09-18-2/+2
| | | | | | | | | | | | | | According to the IMX6DQRM Reference Manual, the description of bit 7 (axi_alt_sel) of the CCM_CBCDR register is: "AXI alternative clock select 0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock 1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock " The current logic is inverted, so fix it to match the reference manual. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> (cherry picked from commit 8f2e2f15ffa1bb03b6e6e189312426059f3215d1)
generated by cgit v1.1 at 2025-03-28 15:38:00 +0000