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| * | | rockchip: video: Check for device in useSimon Glass2016-11-25-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check whether a display device is in use before using it. Add a comment as to why two displays cannot currently be used at the same time. This allows us to remove the device-tree change that disables vopb on jerry. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | rockchip: Allow jerry to use of-platdataSimon Glass2016-11-25-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This board always boots from SPI, so update the code to support that with of-platdata. The boot source is not currently available with of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | dts: arm: rk3036: add usb vbus nodeKever Yang2016-11-25-4/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | add fix regulator node for usb vbus power control. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | | arm: rockchip: Fix typo in ROCKCHIP_RK3288 helpAndreas Färber2016-11-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | UART,s -> UARTs, to avoid this spreading via copy&paste. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
| * | | arm: dts: Fix Rockchip sort orderAndreas Färber2016-11-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Sort rk3036 before rk3288. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
* | | | Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-11-25-110/+909
|\ \ \ \ | |/ / / |/| | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/Kconfig
| * | | armv8: fsl-layerscape: Support loading 32-bit OS with PSCI enabledAlison Wang2016-11-22-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As PSCI and secure monitor firmware framework are enabled, this patch is to support loading 32-bit OS in such case. The default target exception level returned to U-Boot is EL2, so the corresponding work to switch to AArch32 EL2 and jump to 32-bit OS are done in U-Boot and secure firmware together. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-layerscape: SMP support for loading 32-bit OSAlison Wang2016-11-22-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Spin-table method is used for secondary cores to load 32-bit OS. The architecture information will be got through checking FIT image and saved in the os_arch element of spin-table, then the secondary cores will check os_arch and jump to 32-bit OS or 64-bit OS automatically. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: Support loading 32-bit OS in AArch32 execution stateAlison Wang2016-11-22-67/+378
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support loading a 32-bit OS, the execution state will change from AArch64 to AArch32 when jumping to kernel. The architecture information will be got through checking FIT image, then U-Boot will load 32-bit OS or 64-bit OS automatically. Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | arm: exynos7420: remove custome low level init functionThomas Abraham2016-11-22-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the custom low-level initialization function and reuse the default low-level initialization function. But this requires the ARMV8_MULTIENTRY config option to be enabled for Exynos7420. On Exynos7420, the boot CPU belongs to the second cluster and so with ARMV8_MULTIENTRY config option enabled, the 'branch_if_master' macro fails to detect the CPU as boot CPU. As a temporary workaround the CPU_RELEASE_ADDR is set to point to '_main'. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Alison Wang <alison.wang@nxp.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8/fsl-lsch3: Update code to release secondary coresPriyanka Jain2016-11-22-5/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-layerscape: Add NXP LS2088A SoC supportPriyanka Jain2016-11-22-2/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The QorIQ LS2088A SoC is built on layerscape architecture. It is similar to LS2080A SoC with some differences like 1)Timer controller offset is different 2)It has A72 cores 3)It supports TZASC module Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-layerscape : Check SVR for initializing TZASCPriyanka Jain2016-11-22-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2080 SoC and its personalities does not support TZASC But other new SoCs like LS2088A, LS1088A supports TZASC Hence, skip initializing TZASC for Ls2080A based on SVR Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-layerscape: Update TZASC registers typePriyanka Jain2016-11-22-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TZASC registers like TZASC_GATE_KEEPER, TZASC_REGION_ATTRIBUTES are 32-bit regsiters. So while doing register load-store operations, 32-bit intermediate register, w0 should be used. Update x0 register to w0 register type. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: lsch3: Use SVR based timer base address detectionPriyanka Jain2016-11-22-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: lsch3: Add generic get_svr() in assemblyPriyanka Jain2016-11-22-3/+14
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8/fsl-layerscape: Update CONFIG_LS2080A to CONFIG_FSL_LSCH3Shengzhou Liu2016-11-21-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update CONFIG_LS2080A to CONFIG_FSL_LSCH3 to make those workaround implementing of erratum reusable for more SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: fsl-layerscape: Add README for deploying QSPI imageYuan Yao2016-11-21-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Yuan Yao <yao.yuan@nxp.com> [YS: Reviese commit subject] Reviewed-by: York Sun <york.sun@nxp.com>
| * | | fsl: serdes: fix a deadloop issue for P4080Hou Zhiqiang2016-11-21-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This deadloop is introduced by commit: 71fe222 fsl: serdes: ensure accessing the initialized maps of serdes protocol deadloop detail: cpu_init_r => fsl_serdes_init => p4080_erratum_serdes_a005 => is_serdes_configured => fsl_serdes_init Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | powerpc: mpc512x: Add support for get_svr() for mpc512x devicesSriram Dash2016-11-21-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Defines get_svr() for mpc512x devices Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: ls2080a: Update serdes protocol supportPriyanka Jain2016-11-21-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add these serdes protocols Serdes1: 0x39, 0x4B, 0x4C, 0x4D Serdes2: 0x47, 0x57 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> [YS: Revise commit message] Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv8: ls1046aqds: add lpuart supportShaohui Xie2016-11-21-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | LPUART0 is used by default, and it's using platform clock. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | armv7: Add support of ls1021a-iot boardFeng Li2016-11-21-1/+136
| |/ / | | | | | | | | | | | | | | | | | | | | | The patch adds support for Freescale ls1021a-iot board. Signed-off-by: Feng Li <feng.li_2@nxp.com> [YS: rewrite commit message, fix whitespace in Kconfig] Reviewed-by: York Sun <york.sun@nxp.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2016-11-22-0/+4
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| * | | spi: kirkwood_spi: implement mvebu_spi_set_mode()Chris Packham2016-11-18-0/+4
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Set the appropriate bits in the interface config register based on the SPI_ mode flags. Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Chris Packham <judge.packham@gmail.com>
* | | arm: add save_boot_params for ARM1176Cédric Schieli2016-11-21-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a hook to allow boards to save boot-time CPU state for later use. When U-Boot is chain-loaded by another bootloader, CPU registers may contain useful information such as system configuration information. This feature mirrors the equivalent ARMv7 feature. Signed-off-by: Cédric Schieli <cschieli@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* | | TI: Remove CONFIG_OMAP_COMMON in favor of CONFIG_ARCH_OMAP2Tom Rini2016-11-21-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | With the move to arch/arm/mach-omap2 there are now very few uses of CONFIG_OMAP_COMMON and further they can all be replaced with CONFIG_ARCH_OMAP2, so do so. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | arm: Introduce arch/arm/mach-omap2 for OMAP2 derivative platformsTom Rini2016-11-21-72/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This moves what was in arch/arm/cpu/armv7/omap-common in to arch/arm/mach-omap2 and moves arch/arm/cpu/armv7/{am33xx,omap3,omap4,omap5} in to arch/arm/mach-omap2 as subdirectories. All refernces to the former locations are updated to the current locations. For the logic to decide what our outputs are, consolidate the tests into a single config.mk rather than including 4. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | arm: Introduce ARCH_OMAP2Tom Rini2016-11-21-30/+20
| | | | | | | | | | | | | | | | | | | | | | | | To start consolidating various TI-related code, introduce the ARCH_OMAP2 symbol. While we have removed omap2-specific boards some time ago, matching up with the kernel naming here will help overall. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | board: ti: amx3xx: Remove multiple EEPROM readsLokesh Vutla2016-11-21-0/+4
| | | | | | | | | | | | | | | | | | | | | Detect the board very early and avoid reading eeprom multiple times. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: AMx3xx: Centralize early clock initializationLokesh Vutla2016-11-21-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is similar to Commit 93e6253d11030 ("ARM: OMAP4/5: Centralize early clock initialization") that was done for OMAP4+, reflecting the same for AM33xx and AM43xx SoCs to centralize clock initialization. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Add setup_early_clocks that calls setup_clocks_for_console for ti81xx] Signed-off-by: Tom Rini <trini@konsulko.com>
* | | ARM: AMx3xx: Allow arch specific code to use early DMLokesh Vutla2016-11-21-6/+20
|/ / | | | | | | | | | | | | | | | | | | | | | | Early system initialization is being done before initf_dm is being called in U-Boot. Then system will fail to boot if any of the DM enabled driver is being called in this system initialization code. So, rearrange the code a bit so that DM enabled drivers can be called during early system initialization. This is inspired by commit e850ed82bce8 ("ARM: OMAP4+: Allow arch specific code to use early DM") Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Merge tag 'signed-efi-next' of git://github.com/agraf/u-bootTom Rini2016-11-17-30/+687
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch queue for efi - 2016-11-17 Highlights this time around: - x86 efi_loader support - hello world efi test case - network device name is now representative - terminal output reports modes correctly - fix psci reset for ls1043/ls1046 - fix efi_add_runtime_mmio definition for x86 - efi_loader support for ls2080
| * | armv8: fsl-layerscape: Add support for efi_loader RTS resetAlexander Graf2016-11-17-2/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080a: Declare spin tables as reserved for efi loaderAlexander Graf2016-11-17-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | The efi loader code has its own memory map, so it needs to be aware where the spin tables are located, to ensure that no code writes into those regions. Signed-off-by: Alexander Graf <agraf@suse.de>
| * | ls2080: Exit dpaa only right before exiting U-BootAlexander Graf2016-11-17-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ls2080 we have a separate network fabric component which we need to shut down before we enter Linux (or any other OS). Along with that also comes configuration of the fabric using a description file. Today we always stop and configure the fabric in the boot script and (again) exit it on device tree generation. This works ok for the normal booti case, but with bootefi the payload we're running may still want to access the network. So let's add a new fsl_mc command that defers configuration and stopping the hardware to when we actually exit U-Boot, so that we can still use the fabric from an EFI payload. For existing boot scripts, nothing should change with this patch. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: York Sun <york.sun@nxp.com> [agraf: Fix x86 build]
| * | efi_loader: Disable PSCI reset for ls1043 and ls1046Alexander Graf2016-11-17-2/+3
| | | | | | | | | | | | | | | | | | | | | The NXP ls1043 and ls1046 systems do not (yet) have PSCI enablement for reset. Don't enable generic PSCI reset code on them. Signed-off-by: Alexander Graf <agraf@suse.de>
| * | efi: x86: Adjust EFI files support efi_loaderSimon Glass2016-11-14-4/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add compiler flags and make a few minor adjustments to support the efi loader. Signed-off-by: Simon Glass <sjg@chromium.org> [agraf: Add Kconfig dep] Signed-off-by: Alexander Graf <agraf@suse.de>
| * | x86: Move efi .S files into the 'lib' directorySimon Glass2016-11-14-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | These files now need to be in a standard place so that they can be located by generic Makefile rules. Move them to the 'lib' directory. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Graf <agraf@suse.de>
| * | x86: Move efi .lds files into the 'lib' directorySimon Glass2016-11-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | These files now need to be in a standard place so that they can be located by generic Makefile rules. Move them to the 'lib' directory. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Graf <agraf@suse.de>
| * | efi: arm: Add aarch64 EFI app supportSimon Glass2016-11-14-0/+296
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for EFI apps on aarch64. This includes start-up and relocation code plus a link script. Signed-off-by: Simon Glass <sjg@chromium.org> [agraf: add kconfig dep] Signed-off-by: Alexander Graf <agraf@suse.de>
| * | efi: arm: Add EFI app supportSimon Glass2016-11-14-0/+291
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for EFI apps on ARM. This includes start-up and relocation code, plus a link script and some compiler setting changes. Signed-off-by: Simon Glass <sjg@chromium.org> [agraf: Remove whitespace change, add kconfig dep] Signed-off-by: Alexander Graf <agraf@suse.de>
| * | elf: arm: Add a few ARM relocation typesSimon Glass2016-11-14-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | Rather than hard-coding the relocation type, add it to the ELF header file and use it from there. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Graf <agraf@suse.de>
| * | x86: Correct a build warning in x86 tablesSimon Glass2016-11-14-0/+2
| |/ | | | | | | | | | | | | | | | | There is a build warning for three x86 boards since write_smbios_table_wrapper() is not used. Fix it. Fixes: e824cf3f (smbios: Allow compilation on 64bit systems) Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Alexander Graf <agraf@suse.de>
* | ARM64: zynqmp: Adding prefetchable memory space to pcieBharat Kumar Gogada2016-11-15-2/+3
| | | | | | | | | | | | | | | | | | | | Adding prefetchable memory space to pcie device tree node. Shifting configuration space to 64-bit address space. Removing pcie device tree node from amba as it requires size-cells=<2> in order to access 64-bit address space. Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add clocks for LPDDMAKedareswara rao Appana2016-11-15-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Zynqmp DMA driver expects two clocks (main clock and apb clock) For LPDDMA channels the two clocks are missing in the Dma node resulting probe failure. xilinx-zynqmp-dma ffa80000.dma: main clock not found. xilinx-zynqmp-dma ffa80000.dma: Probing channel failed xilinx-zynqmp-dma: probe of ffa80000.dma failed with error -2 This patch fixes this issue. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add description for LPDDMA channel usageKedareswara rao Appana2016-11-15-1/+4
| | | | | | | | | | | | | | | | | | | | | | LPDDMA default allows only secured access. inorder to enable these dma channels, one should ensure that it allows non secure access. This patch updates the same. Reported-by: Sai Pavan Boddu <saipava@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Use 64bit size cell format for main amba busMichal Simek2016-11-15-65/+65
| | | | | | | | | | | | | | Use 64bit size cell for main amba bus instead of 32bit because PCIe node requires it Change 64bit sizes also for all others IPs. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add ocm node in dtsiNaga Sureshkumar Relli2016-11-15-0/+7
| | | | | | | | | | | | | | | | This patch adds ocm controller node in zynqmp.dtsi. needed for OCM edac support. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM64: zynqmp: Add device tree properties for ZynqMP GT coreAnurag Kumar Vulisha2016-11-15-0/+23
| | | | | | | | | | | | | | | | | | This patch adds the ZynqMP GT core device-tree properties for zynqmp.dtsi file. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit v1.1 at 2024-11-10 12:33:15 +0000