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* ARM: cmd_clock: generalize command usage descriptionKhoronzhuk, Ivan2014-10-23-61/+61
| | | | | | | | The usage description of commands refers to headers of sources, that is not correct. This patch is intended to fix it. Also generalize code in order to reduce SoC dependent #ifdefs. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* keystone: usb: add support of usb xhciWingMan Kwok2014-10-23-0/+27
| | | | | | | | | | | | | Add support of usb xhci. xHCI controls all USB speeds of the Host mode, that is, the SS through the SS PHY, as well as the HS, FS, and LS through the USB2 PHY. xHCI replaces and supersedes all previous host HCIs (HS-only EHCI, FS/LS OHCI and UHCI), and is therefore not backwards compatible with any of them. The USB3SS’s USB Controller is fully compliant with xHC. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* dma: keystone_nav: generalize driver usageKhoronzhuk, Ivan2014-10-23-5/+7
| | | | | | | | | | | | | | | | | | | The keystone_nav driver is general driver intended to be used for working with queue manager and pktdma for different IPs like NETCP, AIF, FFTC, etc. So the it's API shouldn't be named like it works only with one of them, it should be general names. The names with prefix like netcp_* rather do for drivers/net/keystone_net.c driver. So it's good to generalize this driver to be used for different IP's and delete confusion with real NETCP driver. The current netcp_* functions of keystone navigator can be used for other settings of pktdma, not only for NETCP. The API of this driver is used by the keystone_net driver to work with NETCP, so net driver also should be corrected. For convenience collect pkdma configurations in drivers/dma/keystone_nav_cfg.c. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* dma: keystone_nav: move keystone_nav driver to driver/dma/Khoronzhuk, Ivan2014-10-23-355/+0
| | | | | | | | | | | | | | The keystone_nav is used by drivers/net/keystone_net.c driver to send and receive packets, but currently it's placed at keystone arch sources. So it should be in the drivers directory also. It's separate driver that can be used for sending and receiving pktdma packets by others drivers also. This patch just move this driver to appropriate directory and doesn't add any functional changes. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* keystone2: keystone_nav: don't use hard addresses in netcp_pktdmaKhoronzhuk, Ivan2014-10-23-29/+27
| | | | | | | | | Use definitions in netcp_pktdma instead direct addresses. The definitions can be set specifically for SoC, so there is no reason to check SoC type while initialization. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* keystone2: keystone_nav: don't use hard addresses in qm_configKhoronzhuk, Ivan2014-10-23-32/+30
| | | | | | | | Use definitions in qm_config. The definitions can be set specifically for SoC, so there is no reason to check SoC type while initialization. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* Merge git://git.denx.de/u-boot-dmTom Rini2014-10-22-212/+2525
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| * dm: rpi: Convert GPIO driver to driver modelSimon Glass2014-10-22-0/+9
| | | | | | | | | | | | | | | | | | Convert the BCM2835 GPIO driver to use driver model, and switch over Raspberry Pi to use this, since it is the only board. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
| * dm: imx: i2c: Use gpio_request() to request GPIOsSimon Glass2014-10-22-0/+25
| | | | | | | | | | | | | | | | | | | | GPIOs should be requested before use. Without this, driver model will not permit the GPIO to be used. Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
| * imx: Add error checking to setup_i2c()Simon Glass2014-10-22-7/+21
| | | | | | | | | | | | | | Since this function can fail, check its return value. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
| * dm: tegra: spi: Convert to driver modelSimon Glass2014-10-22-123/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This converts the Tegra SPI drivers to use driver model. This is tested on: - Tegra20 - trimslice - Tegra30 - beaver - Tegra124 - dalmore (not tested on Tegra124) Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: tegra: dts: Add aliases for spi on tegra30 boardsSimon Glass2014-10-22-0/+4
| | | | | | | | | | | | | | | | All boards with a SPI interface have a suitable spi alias except the tegra30 boards. Add these missing aliases. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dm: sf: sandbox: Convert SPI flash driver to driver modelSimon Glass2014-10-22-14/+0
| | | | | | | | | | | | | | Convert sandbox's spi flash emulation driver to use driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * exynos: universal_c210: Move to driver model soft_spiSimon Glass2014-10-22-0/+13
| | | | | | | | | | | | | | Adjust this board to use the driver model soft_spi implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dm: exynos: Convert SPI to driver modelSimon Glass2014-10-22-0/+9
| | | | | | | | | | | | | | | | | | | | Move the exynos SPI driver over to driver model. This removes quite a bit of boilerplate from the driver, although it adds some for driver model. A few device tree additions are needed to make the SPI flash available. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dm: sandbox: spi: Move to driver modelSimon Glass2014-10-22-0/+1
| | | | | | | | | | | | | | | | Adjust the sandbox SPI driver to support driver model and move sandbox over to driver model for SPI. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * sandbox: dts: Add a SPI device and cros_ec deviceSimon Glass2014-10-22-0/+26
| | | | | | | | | | | | | | | | | | | | | | Add a SPI device which can be used for testing SPI flash features in sandbox. Also add a cros_ec device since with driver model the Chrome OS EC emulation will not otherwise be available. Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: exynos: Mark exynos5 console as pre-relocSimon Glass2014-10-22-0/+1
| | | | | | | | | | | | We will need the console before relocation, so mark it that way. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: exynos: gpio: Convert to driver modelSimon Glass2014-10-22-43/+42
| | | | | | | | | | | | | | Convert the exynos GPIO driver to driver model. This implements the generic GPIO interface but not the extra Exynos-specific functions. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: exynos: Make sure that GPIOs are requestedSimon Glass2014-10-22-0/+3
| | | | | | | | | | | | | | | | | | | | With driver model GPIOs must be requested before use. Make sure this is done correctly. (Note that the soft SPI part of universal is omitted, since this driver is about to be replaced with a driver-model-aware version) Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: exynos: Tidy up GPIO headersSimon Glass2014-10-22-10/+1
| | | | | | | | | | | | | | | | | | The wrong header is being included, thus requiring the code to re-declare the generic GPIO interface in each GPIO header. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: exynos: Add pinctrl settings for s5p_goniSimon Glass2014-10-22-0/+280
| | | | | | | | | | | | | | These describe the GPIOs in enough detail for U-Boot's GPIO driver to operate. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: exynos: Add pinctrl settings for smdkc100Simon Glass2014-10-22-0/+187
| | | | | | | | | | | | | | These describe the GPIOs in enough detail for U-Boot's GPIO driver to operate. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: exynos: dts: Adjust device tree files for U-BootSimon Glass2014-10-22-0/+159
| | | | | | | | | | | | | | | | | | | | The pinctrl bindings used by Linux are an incomplete description of the hardware. It is possible in most cases to determine the register address of each, but not in all cases. By adding an additional property we can fix this, and avoid adding a table to U-Boot for every single Exynos SOC. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: exynos: dts: Remove unused pinctrl information to save spaceSimon Glass2014-10-22-2098/+0
| | | | | | | | | | | | | | | | | | | | We don't include the pinctrl functions for U-Boot as they use up quite a bit of space and are not used. We could instead perhaps eliminate this material with fdtgrep, but so far this tool has not made it to upstream. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: exynos: Bring in pinctrl dts files from Linux kernelSimon Glass2014-10-22-4/+3831
| | | | | | | | | | | | | | | | | | | | Bring in required device tree files for pinctrl from Linux v3.14. These are initially unchanged and have a number of pieces not needed by U-Boot. Note that exynos5420 is renamed to exynos54xx here since we want to support exynos5422 also. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: exynos: dts: Convert /include/ to #includeSimon Glass2014-10-22-15/+15
| | | | | | | | | | | | | | | | We should be consistent about this. The kernel has moved to #include which breaks error reporting to some extent but does allow us to include binding files. Signed-off-by: Simon Glass <sjg@chromium.org>
* | x86: Fix GDT limit in start16.SBin Meng2014-10-22-1/+1
| | | | | | | | | | | | | | GDT limit should be one less than an integral multiple of eight. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: Fix rom version build with CONFIG_X86_RESET_VECTORBin Meng2014-10-22-2/+2
| | | | | | | | | | | | | | | | | | | | When building U-Boot with CONFIG_X86_RESET_VECTOR, the linking process misses the resetvec.o and start16.o so it cannot generate the rom version of U-Boot. The arch/x86/cpu/Makefile is updated to pull them into the final linking process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: Allow cmdline setup in setup_zimage() to be optionalSimon Glass2014-10-22-9/+12
| | | | | | | | | | | | | | If we are passing this using the device tree then we may not want to set this up here. Signed-off-by: Simon Glass <sjg@chromium.org>
* | x86: Rewrite bootm.c to make it similar to ARMSimon Glass2014-10-22-53/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | The x86 bootm code is quite special, and geared to zimage. Adjust it to support device tree and make it more like the ARM code, with separate bootm stages and functions for each stage. Create a function announce_and_cleanup() to handle printing the "Starting kernel ..." message and put it in bootm so it is in one place and can be used by any loading code. Also move the board_final_cleanup() function into bootm. Signed-off-by: Simon Glass <sjg@chromium.org>
* | x86: Enable LMB and RAMDISK_HIGH by defaultSimon Glass2014-10-22-0/+3
|/ | | | | | | These options are used by the image code. To allow us to use the generic code more easily, define these for x86. Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure bootRuchika Gupta2014-10-16-1/+9
| | | | | | | | | | | By default, PAMU's (IOMMU) are enabled in case of secure boot. Disable/bypass them once the control reaches the bootloader. For non-secure boot, PAMU's are already bypassed in the default SoC configuration. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ls102x: configs - Add hash command in freescale LS1 platformsRuchika Gupta2014-10-16-0/+4
| | | | | | | | | Hardware accelerated support for SHA-1 and SHA-256 has been added. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* fsl_sec: Add hardware accelerated SHA256 and SHA1Ruchika Gupta2014-10-16-0/+16
| | | | | | | | | | SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam. The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to enable initialization of this hardware IP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* fsl_sec : Change accessor function to take care of endiannessRuchika Gupta2014-10-16-6/+7
| | | | | | | | | | | SEC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of SEC IP. So update acessor functions with common SEC acessor functions to take care both type of endianness. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* fsl_sec : Move SEC CCSR definition to common includeRuchika Gupta2014-10-16-66/+1
| | | | | | | | | Freescale SEC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of SEC to common include Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-10-11-526/+1461
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| * powerpc: mpc5xxx: remove board support for MVBC_P and MVSMRMasahiro Yamada2014-10-10-8/+0
| | | | | | | | | | | | These boards have been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * powerpc: mpc83xx: remove board support for MERGERBOX and MVBLM7Masahiro Yamada2014-10-10-8/+0
| | | | | | | | | | | | These boards have been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * powerpc: ppc4xx: remove board support for bluestoneMasahiro Yamada2014-10-10-180/+18
| | | | | | | | | | | | | | | | | | This board has been orphaned for more than 6 months. It is the last board defining CONFIG_APM821XX. The code inside #ifdef CONFIG_APM821XX should be removed too. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * powerpc: ppc4xx: remove board support for CRAYL1Masahiro Yamada2014-10-10-4/+0
| | | | | | | | | | | | This board has been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * powerpc: ppc4xx: remove board support for KAREF and METROBOXMasahiro Yamada2014-10-10-8/+0
| | | | | | | | | | | | These boards have been orphaned for more than 6 months. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * ARM: keystone: clock: fix main pll ratio div definitionsKhoronzhuk, Ivan2014-10-10-5/+5
| | | | | | | | | | | | | | The definitions for div ratio supposed to be in hex and were added in dec by mistake. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * ARM: OMAP5+: sata: Move scsi_scan() to the right placeRoger Quadros2014-10-10-1/+1
| | | | | | | | | | | | | | scsi_scan() must be called as part of scsi_init() and not as part of sata_init(). Signed-off-by: Roger Quadros <rogerq@ti.com>
| * OMAP5+: sata/scsi: Implement scsi_init()Roger Quadros2014-10-10-0/+6
| | | | | | | | | | | | | | | | | | | | On OMAP platforms, SATA controller provides the SCSI subsystem so implement scsi_init(). Get rid of the unnecessary sata_init() call from dra7xx-evm and omap5-uevm board files. Signed-off-by: Roger Quadros <rogerq@ti.com>
| * Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-10-07-28/+4608
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| * | arm: socfpga: Add command to control HPS-FPGA bridgesMarek Vasut2014-10-06-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add command to enable and disable the bridges between HPS and FPGA. This patch does have a checkpatch issue with the assembler portion, checkpatch correctly complains that there should be no whitespace before quoted newline. I do not agree that fixing this specific checkpatch issue will improve the readability, thus this one is not addressed. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de>
| * | arm: socfpga: Move cache_enable to CPU codeMarek Vasut2014-10-06-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move icache_enable() and dcache_enable() function calls from board code into the CPU code and into the enable_caches() function. This is how the cache enabling code was designed to work. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
| * | arm: socfpga: nic301: Add NIC-301 configuration codePavel Machek2014-10-06-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code which configures the AMBA NIC-301 and the SCU on the SoCFPGA . The code sets the access permissions for the CPU to the AMBA slaves such that the CPU can access them in both secure and non-secure mode. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
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