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| * | | mpc85xx: Add support for the Varisys Cyrus boardAndy Fleming2015-11-04-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board runs a P5020 or P5040 chip, and utilizes an EEPROM with similar formatting to the Freescale P5020DS. Large amounts of this code were developed by Adrian Cox <adrian at humboldt dot co dot uk> Signed-off-by: Andy Fleming <afleming@gmail.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | ARM: zynq: Remove zc70x targetMichal Simek2015-11-04-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove zc70x target which was one setting for zc702 and zc706. Currently zc702 and zc706 are separated. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | | | arm: zynq: Move serial driver to driver modelSimon Glass2015-11-04-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update this driver to use driver model and change all users. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | ARM: zynqmp: Enable DM and OF bindingMichal Simek2015-11-04-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI requires DM and OF that's why enable DM for ZynqMP and start to use configuration based on embedded OF. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | arm: zynq: dts: Add U-Boot device tree additionsSimon Glass2015-11-04-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to mark some device tree nodes so that they are available before relocation. This enables driver model to find these automatically. In the case of SPL it ensures that these nodes will be retained in SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | dm: arm: zynq: Enable device tree control in SPLSimon Glass2015-11-04-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move to using device tree control in SPL so that we can use the same driver code in both SPL and U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | arm: zynq: Support the debug UARTSimon Glass2015-11-04-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the debug UART to assist with early debugging. Enable it for Zybo as an example. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | arm: zynq: Drop unnecessary code in SPL board_init_f()Simon Glass2015-11-04-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move to the new way of starting up SPL. Clearing of BSS and calling board_init_r() is now handled by crt0.S. Also tidy up the header include order. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | ARM: zynqmp: Add DTS for ep108 boardMichal Simek2015-11-04-0/+963
|/ / / | | | | | | | | | | | | | | | | | | Add DTS for ep108 board. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Series-to: u-boot
* | | mmc: atmel: Add atmel sdhci supportWenyou Yang2015-11-03-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SDHCI is introduced by sama5d2, named as Secure Digital Multimedia Card Controller(SDMMC). It supports the embedded MultiMedia Card (e.MMC) Specification V4.41, the SD Memory Card Specification V3.0, and the SDIO V3.0 specification. It is compliant with the SD Host Controller Standard V3.0 specification. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | arm: at91: clock: Add the generated clock supportWenyou Yang2015-11-03-0/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some peripherals may need a second clock source that may be different from the system clock. This second clock is the generated clock (GCK) and is managed by the PMC via PMC_PCR. For simplicity, the clock source of the GCK is fixed to PLLA_CLK. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | arm: at91: Change the Chip ID registers' addressesWenyou Yang2015-11-03-7/+10
|/ / | | | | | | | | | | | | | | Provide the specific addresses for the Chip ID and Chip ID Extension registers, instead of the offset, which make it use on other chips. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | mpc85xx/t2081: enable parsing DDR ratio for T2081 rev1.1Shengzhou Liu2015-11-02-1/+2
| | | | | | | | | | | | | | | | T2081 rev 1.1 changes MEM_PLL_RAT in RCW which requires new parsing for PLL ratio. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | t1040d4rdb: assign muxed pins to qe-tdm when set hwconfig qe-tdmZhao Qiang2015-11-02-0/+22
| | | | | | | | | | | | | | | | | | qe-tdm is muxed with diu, if hwconfig setted as qe-tdm, assign muxed pins to qe-tdm, then delete diu node from device tree. Signed-off-by: Zhao Qiang <qiang.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | at91: simplify spl board_init_f functionJosh Wu2015-11-01-5/+0
|/ | | | | | | | | crt0.S do both memset the bss section and call board_init_r for us, so remove them from board_init_f(). Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-10-30-1517/+2362
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| * arm: ls1021a: Add sata support on qds and twr boardtang yuantian2015-10-29-0/+93
| | | | | | | | | | | | | | | | | | | | Freescale ARM-based Layerscape LS102xA contain a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls1021aqds and ls1021atwr boards. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043a: Enable secondary coresHou Zhiqiang2015-10-29-0/+15
| | | | | | | | | | | | | | | | | | | | After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to make secondary cores excute in spin loop. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardbYangbo Lu2015-10-29-1/+21
| | | | | | | | | | | | | | | | This patch adds esdhc support for ls1043ardb. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043a: Add Fman supportShaohui Xie2015-10-29-0/+41
| | | | | | | | | | | | | | | | Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: Add nand boot supportGong Qianyu2015-10-29-0/+4
| | | | | | | | | | | | | | | | Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/ls1043ardb: Add LS1043ARDB board supportMingkai Hu2015-10-29-0/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1043ARDB Specification: ------------------------- Memory subsystem: * 2GByte DDR4 SDRAM (32bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * XFI 10G port * QSGMII with 4x 1G ports * Two RGMII ports PCIe: * PCIe2 (Lanes C) to mini-PCIe slot * PCIe3 (Lanes D) to PCIe slot USB 3.0: two super speed USB 3.0 type A ports UART: supports two UARTs up to 115200 bps for console Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
| * armv8/fsl_lsch2: Add fsl_lsch2 SoCMingkai Hu2015-10-29-0/+1221
| | | | | | | | | | | | | | | | | | | | | | Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl_lsch3: Change arch to fsl-layerscapeMingkai Hu2015-10-29-509/+690
| | | | | | | | | | | | | | | | | | | | | | | | | | There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net: Move some header files to include/Shaohui Xie2015-10-29-897/+1
| | | | | | | | | | | | | | | | | | | | The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM and PPC, move it out of ppc to include/, and change the path in drivers accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv7/ls1021a: move ns_access to common fileMingkai Hu2015-10-29-21/+82
| | | | | | | | | | | | | | | | | | | | Config Security Level Register is different between different SoCs, so put the CSL register definition into the arch specific directory. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * arm: ls102xa: enable snooping for CAAM transactionshoria.geanta@freescale.com2015-10-29-0/+4
| | | | | | | | | | | | | | | | | | | | | | Enable snooping for CAAM read & write transactions by programming the SCFG snoop configuration register: SCFG_SNPCNFGCR[SECRDSNP] SCFG_SNPCNFGCR[SECWRSNP] Signed-off-by: Horia Geantă <horia.geanta@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * Data types defined for 64 bit physical addressAneesh Bansal2015-10-29-5/+9
| | | | | | | | | | | | | | | | Data types and I/O functions have been defined for 64 bit physical addresses in arm. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * ls102xa: fdt: Disable IFC in SD boot for QSPIAlison Wang2015-10-29-1/+1
| | | | | | | | | | | | | | | | | | As QSPI/DSPI and IFC are pin multiplexed, IFC is disabled in SD boot for QSPI. This patch will add fdt support for this rule. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: fdt: Check the pointer returned from call to a function may ↵Alison Wang2015-10-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | be NULL Pointer 'reg' returned from call to function 'fdt_getprop' may be NULL, will be passed to function and may be dereferenced there by passing argument 1 to function 'of_read_number'. So check pointer 'reg' first. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-10-28-1/+38
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| * | dts: zed: Enable zynq qspi controller nodeJagan Teki2015-10-25-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enabled zynq qspi controller node for zed board. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
| * | dts: zc770-xm010: Enable zynq qspi controller nodeJagan Teki2015-10-25-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabled zynq qspi controller node for zc770-xm010 board. => sf probe 0 -- bus1 for selecting qspi controller => sf probe 1 -- bus0 for selecting spi controller Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
| * | dts: zc706: Enable zynq qspi controller nodeJagan Teki2015-10-25-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enabled zynq qspi controller node for zc706 board. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
| * | dts: zc702: Enable zynq qspi controller nodeJagan Teki2015-10-25-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enabled zynq qspi controller node for zc702 board. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
| * | dts: microzed: Enable zynq qspi controller nodeJagan Teki2015-10-25-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabled zynq qspi controller node for microzed board, verified the same on spansion spi-nor flash. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
| * | dts: zynq: Add zynq qspi controller nodesJagan Teki2015-10-25-0/+12
| |/ | | | | | | | | | | | | | | | | | | This patch adds zynq qspi controller nodes in zynq-7000.dtsi. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Simon Glass <sjg@chromium.org> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* | arch/powerpc/cpu/ppc4xx/Kconfig: Finish removing boardsTom Rini2015-10-27-16/+0
|/ | | | | | | My patches to drop various ppc4xx boards were not build tested and omitted the Kconfig parts. Signed-off-by: Tom Rini <trini@konsulko.com>
* arm, powerpc: select SYS_GENERIC_BOARDMasahiro Yamada2015-10-24-1/+2
| | | | | | | | | | | We have finished Generic Board conversion for ARM and PowerPC, i.e. all the boards have been converted except OpenRISC, SuperH, SPARC, which have not supported Generic Board framework yet. Select SYS_GENERIC_BOARD in arch/Kconfig and delete all the macro defines in include/configs/*.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* zynq: Move SPL console init out of board_init_f()Simon Glass2015-10-24-1/+1
| | | | | | | | | | | | | | We should not init the console this early since it precludes using driver model for the UART, since it is not set up at the start of board_init_f(). See the README for more information. The debug UART does not have this restriction. If we want to do early init with the console on it can be done in spl_board_init(). Move the preloader_console_init() call from board_init_f() to board_init_r(). Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Michal Simek <michal.simek@xilinx.com>
* microblaze: Add a TODO to call board_init_f_mem()Simon Glass2015-10-24-0/+2
| | | | | | | | This C function should be used to do the early memory layout and init. This is beyond my powers, so just add a TODO for the maintainer. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Michal Simek <michal.simek@xilinx.com>
* arm: Switch 32-bit ARM to using generic global_data setupSimon Glass2015-10-24-24/+4
| | | | | | | | | | There is quite a bit of assembler code that can be removed if we use the generic global_data setup. Less arch-specific code makes it easier to add new features and maintain the start-up code. Drop the unneeded code and adjust the hooks in board_f.c to cope. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: Switch aarch64 to using generic global_data setupSimon Glass2015-10-24-12/+3
| | | | | | | | | | | | | There is quite a bit of assembler code that can be removed if we use the generic global_data setup. Less arch-specific code makes it easier to add new features and maintain the start-up code. Drop the unneeded code and adjust the hooks in board_f.c to cope. Tested on LS2085ARDB and LS2085AQDS (armv8 SoC). Tested-by: York Sun <yorksun@freescale.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* nios2: fix virt_to_phys for nios2 with MMUThomas Chou2015-10-23-1/+5
| | | | | | | | | As the virtual address and physical address mapping of nios2 with MMU are different. Add a check of MMU, and fix the mapping. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Ley Foon Tan <lftan@altera.com>
* nios2: zap nios2-generic board dirThomas Chou2015-10-23-10/+6
| | | | | | | As we use device tree to control u-boot now, the generic board can be removed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* nios2: convert dma_alloc_coherent to use malloc_cache_alignedThomas Chou2015-10-23-13/+14
| | | | | | | Convert dma_alloc_coherent to use memalign. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
* nios2: convert copy_exception_trampoline to use dm cpu dataThomas Chou2015-10-23-24/+25
| | | | | | Convert copy_exception_trampoline() to use dm cpu data. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* nios2: convert cache flush to use dm cpu dataThomas Chou2015-10-23-98/+133
| | | | | | | | | | | | | | | Convert cache flush to use dm cpu data. The original cache flush functions are written in assembly and use CONFIG_SYS_{I,D}CACHE_SIZE... macros. It is difficult to convert to use cache configuration in dm cpu data which is extracted from device tree. The cacheflush.c of Linux nios2 arch uses cpuinfo structure, which is very close to our dm cpu data. So we copy and modify it to arch/nios2/lib/cache.c to replace the old cache.S. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* nios2: set default cache configuration in start.SThomas Chou2015-10-23-7/+15
| | | | | | | | | | | | | | | | | | | Set default icache and dcache configuration for start.S. We want to remove the CONFIG_SYS_{I,D}CACHE_SIZE... configuration macros. As we are just barely starting from reset, there is no luxury of device tree. We will set some maximum cache configuration so that it will work for most configurations. This is used only in this start.S. The speed penalty is only once here. After start up, during board initialization, cpu information will be extracted from device tree. Then cache flush operations will have correct cache configurations. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Marek Vasut <marex@denx.de>
* nios2: clean up comments style in start.SThomas Chou2015-10-23-31/+30
| | | | | | Clean up comments style in start.S. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
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