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| * | sunxi: Add suport for A83T based Banana-pi M3 BoardVishnu Patekar2016-01-26-1/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add dts and defconfig for Banana-pi M3 board. It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI, mic, AP6212 Wifi, etc on it. It is paired with AXP813 PMIC which is almost same as AXP818. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> [hdegoede@redhat.com: rename to Sinovoip_BPI_M3_defconfig/sun8i-a83t-sinovoip-bpi-m3.dts] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Add support for LPDDR3 for A83TVishnu Patekar2016-01-26-5/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | Banana-pi M3 has LPDDR3 DRAM. this adds support for LPDDR3 for A83T. Mostly the timing parameters are different from DDR3. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Groundwork to support new dram type for A83TVishnu Patekar2016-01-26-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Different A83T boards have different DRAM types. Banapi M3 has LPDDR3, Allwinner Homlet v1.2 has DDR3. This adds groundwork to support for new DRAM type for A83T. Introduce CONFIG_DRAM_TYPE, It'll be 3 for DDR3 and 7 for LPDDR3, must be set in respective board defconfig. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Redundant code cleanup from a83t dram initVishnu Patekar2016-01-26-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | This removes the redundant lines of code from mctl_sys_init. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Support PSCI ops on Allwinner H3Chen-Yu Tsai2016-01-26-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | H3 has the same power sequencing procedure as the A31/A31s, which includes the power clamps. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Support H3 CCU security switchesChen-Yu Tsai2016-01-26-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | H3's CCU includes some switches which disable non-secure access to some of the more critical clock controls, such as MBUS, PLLs, and main platform busses. Configure them to enable non-secure access. For now the only SoC that has this feature is the H3. For other platforms just use a default (weak) empty function so things do not break. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Support Secure Memory Touch Arbiter (SMTA) in sun8i H3Chen-Yu Tsai2016-01-26-4/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Secure Memory Touch Arbiter is the same thing as the TrustZone Protection Controller found on A31/A31s. Access to many peripherals on the H3 can be controlled by the SMTA, and the settings default to secure access only. This patch supports the new settings, and sets them to allow non-secure access. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2016-01-26-0/+14
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| * | | video: Add support for Armada XP LCD controllerStefan Roese2016-01-23-0/+14
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic support for the LCD controller of the Marvell Armada XP SoC. An AXP based custom board port will be added later, to use this driver to display a splash screen via the bmp command later. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> [agust: rebased] Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | | mips: asm/io.h: Add in <linux/bug.h>Tom Rini2016-01-25-0/+1
| | | | | | | | | | | | | | | | | | As part of the bug.h / BUILD_BUG_* clean up, this file was missed. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2016-01-25-4/+15
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| * | arch/powperpc: Fix start_align due to use of __ffs64() instead ffs64()Ashish kumar2016-01-25-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Incorrect DDR law was created in case of B4860qds after commit 2d2f490d. Return value of ffs64() differs from __ffs64(), eg. ffs64(0x80000000) = 0x20 __ffs64(0x80000000) = 0x1f As a result of this change, callers need to adjust the expected return value by removing -1. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | powerpc: mpc85xx: Move set_liodns, setup_portals to common boot seqPrabhakar Kushwaha2016-01-25-0/+11
| |/ | | | | | | | | | | | | | | | | | | | | | | Users migrating Freescale's PowerPC SoC U-Boot code to their custom board, often overlook the need to execute set_liodns() and setup_portals() being called by platform files. So Move set_liodns() and setup_portals() to common u-boot boot sequence Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-imxTom Rini2016-01-25-10/+188
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| * | imx: mx7: default enable MDIO open drainPeng Fan2016-01-24-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The management data input/output (MDIO) requires open-drain, i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports this feature. So to TO1.1, need to enable open drain by setting bits GPR0[8:7] for TO1.1. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6ul/sx: fix mmdc_ch0 clk calculationPeng Fan2016-01-24-4/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications Processor Reference Manual and "Figure 18-5. BUS clock generation" of i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk sources from pll4_main_clk(pll_audio), the calculation is wrong. Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support for decode_pll. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6: add more entry for mxc_ccm_regPeng Fan2016-01-24-0/+91
| | | | | | | | | | | | | | | | | | | | | | | | Add more entries for structure mxc_ccm_reg. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: nand: update GPMI NAND driver to support MX7Peng Fan2016-01-24-2/+2
| | | | | | | | | | | | | | | | | | | | | Update GPMI NAND driver and BCH head file to support i.MX7 Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: apbh_dma: Update APBH-DMA for MX7DPeng Fan2016-01-24-4/+4
| |/ | | | | | | | | | | | | Update APBH-DMA driver and head files to support i.MX7D Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* | openrisc: Fix build errorsBin Meng2016-01-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With kernel.org toolchain, it reports: CC arch/openrisc/lib/board.o arch/openrisc/lib/board.c:56:2: error: 'console_init_f' undeclared here (not in a function) arch/openrisc/lib/board.c: In function 'board_init': arch/openrisc/lib/board.c:120:2: warning: implicit declaration of function 'console_init_r' make[1]: *** [arch/openrisc/lib/board.o] Error 1 make: *** [arch/openrisc/lib] Error 2 Include console.h will fix this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | bug.h: move BUILD_BUG_* defines to include/linux/bug.hMasahiro Yamada2016-01-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUILD_BUG_* macros have been defined in several headers. It would be nice to collect them in include/linux/bug.h like Linux. This commit is cherry-picking useful macros from include/linux/bug.h of Linux 4.4. I did not import BUILD_BUG_ON_MSG() because it would not work if it is used with include/common.h in U-Boot. I'd like to postpone it until the root cause (the "error()" macro in include/common.h causes the name conflict with "__attribute__((error()))") is fixed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | serial: Remove serial_putc_raw_devTom Rini2016-01-25-23/+0
| | | | | | | | | | | | | | | | | | clang-3.8 reports that serial_putc_raw_dev in serial_ns16550.c is unused. Further investigation shows that we have 3 places that implement this function and no callers, remove. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | arm, powerpc: Update cc-version tests to check for cc-name as wellTom Rini2016-01-25-2/+4
| | | | | | | | | | | | | | | | For compatibility clang will report some gcc version. However since we are checking gcc versions in order to then fail to build, we should limit these tests only to when we are using gcc and not clang. Signed-off-by: Tom Rini <trini@konsulko.com>
* | x86: ivybridge: Use syscon for the GMA deviceSimon Glass2016-01-24-15/+17
| | | | | | | | | | | | | | | | | | Until we have a proper video uclass we can use syscon to handle the GMA device, and avoid the special device tree and PCI searching. Update the code to work this way. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Set up a shared syscon numbering schemaSimon Glass2016-01-24-4/+14
| | | | | | | | | | | | | | | | | | Each system controller can have a number to identify it. It can then be accessed using syscon_get_by_driver_data(). Put this in a shared header file and update the only current user. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Drop the SMM-locking codeSimon Glass2016-01-24-57/+0
| | | | | | | | | | | | | | | | U-Boot does not support SMM yet, so we can drop this code. It is easy to bring back when needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Drop XHCI supportSimon Glass2016-01-24-34/+0
| | | | | | | | | | | | | | This is not used on link which is the only ivybridge board. Drop this code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Drop special EHCI initSimon Glass2016-01-24-34/+12
| | | | | | | | | | | | | | | | | | | | This is not needed. On reset wake-on-disconnect is already set. It may a problem during a soft reset or resume, but for now it does not seem important. Also drop the command register update since PCI auto-config does it for us. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Sort out the calls to bridge_silicon_revision()Simon Glass2016-01-24-42/+46
| | | | | | | | | | | | | | | | This function is called all over the place. Convert it use the driver model PCI API, and rationalise the calls. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Move code from pch.c to bd82x6x.cSimon Glass2016-01-24-145/+129
| | | | | | | | | | | | | | This code relates to the PCH, so we should move it into the same file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Convert pch.c to use DM PCI APISimon Glass2016-01-24-32/+76
| | | | | | | | | | | | | | Convert this file to use the driver model PCI API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Convert report_platform to DM PCI APISimon Glass2016-01-24-7/+8
| | | | | | | | | | | | | | Convert these functions to use the driver model PCI API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Convert SDRAM init to use driver modelSimon Glass2016-01-24-38/+101
| | | | | | | | | | | | | | | | | | SDRAM init needs access to the Northbridge controller and the Intel Management Engine device. Add the latter to the device tree and convert all of this code to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Convert sdram_initialise() to use DM PCI APISimon Glass2016-01-24-9/+10
| | | | | | | | | | | | | | | | Convert this function to use the the driver model PCI API. We just need to pass in the northbridge device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Convert dram_init() to use DM PCI APISimon Glass2016-01-24-14/+25
| | | | | | | | | | | | | | | | Convert the top part of the DRAM init to use the driver model PCI API. Further work will complete the transformation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Convert enable_usb_bar() to use DM PCI APISimon Glass2016-01-24-17/+17
| | | | | | | | | | | | | | | | | | Convert this function over to use the driver model PCI API. In this case we want to avoid using the real PCI devices since they have not yet been probed. Instead, write directly to their PCI configuration address. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Use the I2C driver to perform SMbus initSimon Glass2016-01-24-36/+9
| | | | | | | | | | | | | | | | Move the init code into the I2C driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Convert lpc init code to DM PCI APISimon Glass2016-01-24-63/+66
| | | | | | | | | | | | | | | | Adjust this code to use the driver model PCI API. This is all called through lpc_init_extra(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Drop the special PCI driverSimon Glass2016-01-24-48/+1
| | | | | | | | | | | | | | | | There is nothing special about the ivybridge pci driver now, so just use the generic one. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Move LPC init into the LPC probe() methodSimon Glass2016-01-24-14/+9
| | | | | | | | | | | | | | | | Drop the lpc_init_extra() function and just use the post-relocation LPC probe() instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Move lpc_enable() into gma.cSimon Glass2016-01-24-9/+4
| | | | | | | | | | | | | | | | This graphics init code is best placed in the gma init code. Move the code and drop the function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Use driver model PCI API in sata.cSimon Glass2016-01-24-49/+45
| | | | | | | | | | | | | | Adjust the functions in this file to use the driver model PCI API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Use the SATA driver to do the initSimon Glass2016-01-24-10/+8
| | | | | | | | | | | | | | | | Instead of manually initing the device, probe the SATA device and move the init there. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Drop the unused bd82x6x_init_extra()Simon Glass2016-01-24-18/+0
| | | | | | | | | | | | | | This function does nothing now so can be dropped. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Do the SATA init before relocationSimon Glass2016-01-24-11/+36
| | | | | | | | | | | | | | | | | | The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Drop unnecessary northbridge setupSimon Glass2016-01-24-20/+0
| | | | | | | | | | | | | | This is done by default with PCI auto-config. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Use driver model PCI API in bd82x6x.cSimon Glass2016-01-24-16/+7
| | | | | | | | | | | | | | | | | | Adjust most of the remaining functions in this file to use the driver model PCI API. The one remaining function is bridge_silicon_revision() which will need a little more work. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: ivybridge: Move northbridge and PCH init into driversSimon Glass2016-01-24-47/+12
| | | | | | | | | | | | | | | | | | | | Instead of calling the northbridge and PCH init from bd82x6x_init_extra() when the PCI bus is probed, call it from the respective drivers. Also drop the Northbridge init as it has no effect. The registers it touches appear to be read-only. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Bring up northbridge, pch and lpc after the CPUsSimon Glass2016-01-24-2/+18
| | | | | | | | | | | | | | | | | | | | These devices currently need to be inited early in boot. Once we have the init in the right places (with each device doing its own init and no problems with ordering) we should be able to remove this. For now it is needed to keep things working. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Don't show an error when the MRC cache is up to dateSimon Glass2016-01-24-1/+5
| | | | | | | | | | | | | | | | | | | | When the final MRC cache record is the same as the one we want to write, we skip writing since there is no point. This is normal behaviour. Avoiding printing an error when this happens. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-11-09 07:54:32 +0000