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* MLK-11159-1 Revert "MLK-11114 imx: mx6qp disable double line feature"Robby Cai2015-06-24-8/+0
| | | | | | | | | | | This reverts commit 046e55efa686f40b4cad312e1e64348f19107bd9. After further investigation, find the L2 cache double line fill is not the root cause for USB or SD3.0 stress reboot failure. With the fix in USB driver, and the L2 double line fill enabled, the reboot stress test has passed 4-days. So revert the patch to make L2 double line fill enabled on imx6qp by default. Signed-off-by: Robby Cai <r63905@freescale.com>
* MLK-11114 imx: mx6qp disable double line featurePeng Fan2015-06-16-0/+8
| | | | | | | | | | | With L2 double line fill enabled, the stress reboot test failure is met on USB(MLK10738) or SD3.0(MLK11072). By disabling L2 double line fill, the stress reboot can pass. Note we are still investigating on this issue to find the evidence how these issues are corelated with L2 double line fill. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Bai Ping <b51503@freescale.com>
* MLK-11028 imx: mx6qp change L2 prefetch offset to 0Peng Fan2015-06-12-1/+1
| | | | | | | Change L2 prefetch offset to 0 to make system stable. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 5cab58016a032ea364c8e5df3994ac51fdf60b0a)
* MLK-11035 imx: mx6 update thermal slope factorsPeng Fan2015-06-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | From temp sensor guys: " I confirmed the math with him(had do the accuracy study) today. The new, final equation is: Tmeas = (Nmeas - n1) / slope + t1 + offset n1= fused room count t1= 25 offset=3.580661 slope= 0.4148468 – 0.0015423*n1 " 87723f903454aaf17336e0fe9098ea7911c19f3c update the thermal with not accurate slope parameters. This patch fix it. Conflicts: drivers/thermal/imx_thermal.c Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit f02e68977da7d91d347f6015a5301fc82d72878f) (cherry picked from commit 5bf7dc588d3311a5493fe66cba9b36a239f3ddfd)
* MLK-10827 imx: mx6 update thermal driver according new equationPeng Fan2015-06-10-23/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From IC guys: " After a thorough accuracy study of the Temp sense circuit, we found that with our current equation, an average part can read 7 degrees lower than a known forced temperature. We also found out that the standard variance was around 2C; which is the tightest distribution that we could create. We need to change the temp sense equation to center the average part around the target temperature. Old Equation: Temp = Troom,cal – slope*(Count measured – Count room fuse) Where Troom,cal = 25C and Slope = 0.4297157 – (0.0015974 * Count room fuse) New Equation: Temp = Troom,cal – slope*(Count measured – Count room fuse) +offset Where Troom,cal = 25C and Slope = 0.4445388 – (0.0016549 * Count room fuse) Offset = 3.580661 " According the new equation, update the thermal driver. c1 and c2 changed to u64 type and update comments. Conflicts: drivers/thermal/imx_thermal.c since to imx_v2014.04, there is no imx_thermal driver, implement the new equation in arch/arm/cpu/armv7/mx6/soc.c. Also drop the orignial way to calculate temp, but use the way in imx_v2015.04 which aligns with linux kernel Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 87723f903454aaf17336e0fe9098ea7911c19f3c) (cherry picked from commit 7f8fa8b46f90d41fe3f37fbac40d8d773cdee5ce)
* MLK-11064 imx: mx6qp: Adjust AQos settings for peripheralsYe.Li2015-06-08-0/+3
| | | | | | | | | | To resolve USB camera bandwidth issue, the patch sets recommended AQoS setting from IC team value for peripheral and only on imx6qp. The address is: 0xbb0608, the value is: 0x80000201 Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit d00e9400bfbfb097ab5b0b26fae92db3dc1dd047)
* MLK-10957: ARM: mx6qp: do not turn off PURobin Gong2015-05-25-1/+2
| | | | | | | | | There is narrow window that PRE driver is ready but GPU driver probe later, and the later GPU driver turn on PU may cause 'PRE hang' issue. To simplify thing, do not turn off PU in u-boot. Signed-off-by: Robin Gong <b38343@freescale.com> (cherry picked from commit 6b0787b726e2ff32210d742d93ecd3f4bb2ae402)
* MLK-10708 imx:mx6qp Update Saturation THR for PRExPeng Fan2015-04-21-4/+4
| | | | | | | Update settings for PRE. Value for Saturation THR of PREx, changed from 0x20 to 0x10 to make system more stable. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10702 imx: mx7d: clock: correct fec MDC root clockFugang Duan2015-04-21-1/+1
| | | | | | | In i.MX7d platform, fec MDC root clock is ENET_AXI_ROOT_CLK, not ipg clock, correct it. Signed-off-by: Fugang Duan <B38611@freescale.com>
* MLK-10674-2 imx: mx6qp settings for PREPeng Fan2015-04-17-0/+38
| | | | | | | | | | | | | | | | | | | | | Since the following piece settings can not be in DCD table, we add them in enable_ipu_clock. " setmem /32 0x00bb048c = 0x00000002 ## Bypass IPU1 QoS generator setmem /32 0x00bb050c = 0x00000002 ## Bypass IPU2 QoS generator setmem /32 0x00bb0690 = 0x00000200 ## Bandwidth THR for of PRE0 setmem /32 0x00bb0710 = 0x00000200 ## Bandwidth THR for of PRE1 setmem /32 0x00bb0790 = 0x00000200 ## Bandwidth THR for of PRE2 setmem /32 0x00bb0810 = 0x00000200 ## Bandwidth THR for of PRE3 setmem /32 0x00bb0694 = 0x00000020 ## Saturation THR for of PRE0 setmem /32 0x00bb0714 = 0x00000020 ## Saturation THR for of PRE1 setmem /32 0x00bb0794 = 0x00000020 ## Saturation THR for of PRE2 setmem /32 0x00bb0814 = 0x00000020 ## Saturation THR for of PRE " CONFIG_VIDEO_IPUV3 is always defined in mx6sabre_common.h, the settings sure will effect. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10647 armv7: Fix Dcache disable issue on i.MX7Ye.Li2015-04-14-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The issue on the i.MX7D is that, there is one cache-able memory access between the L1 and L2 cache flush by calling the flush_dache_all-> v7_maint_dcache_all() [Flush L1 and L2 cache) which written in the C code. L1-cache-flush -> This will flush L1 cache to L2 cache in the end. Cache-able memory access -> This will have the chance cause the L1 line-fill with dirty data from L2 cache(L1 cache-line dirty, L2 clean) L2-cache-flush -> This will only flush L2 cache to L3, but still some dirty data on the L1 cacheline. After C & M bit clean, -> The dirty data on the L1 cache line lost, which will cause memory coherent issue if that dirty cache line has some useful data The only problem here is: there is one cache-cable memory access between L1 and L2 cache flush. This patch should works fine on the i.MX6 and i.MX7. The second cache flush have zero impact on the i.MX6, but this is really need for the i.MX7D platform due to the L1 line-fill during the first dcache_flush. And the second flush will not bring in the L1 dirty cache line due to the C bit is clear now, which means the dcache is disabled. Acked-by: Jason Liu<r64343@freescale.com> Reviewed-by: Jason Liu<r64343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10597: arm: imx7d: extend iomuxc-lpsr IO pads config optionsAdrian Alonso2015-04-08-4/+39
| | | | | | | | * Extend IOMUXC-LPSR IO pads configuration options * Add alternative configuration modes for IO pads from IOMUXC-LPSR Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* MLK-10569 imx7d: call set_epdc_qos unconditionallyRobby Cai2015-04-07-4/+1
| | | | | | | This EPDC/EPXP QoS setting is needed for EPDC stress test to pass. This patch remove the #ifdef to make sure set_epdc_qos be called always. Signed-off-by: Robby Cai <r63905@freescale.com>
* MLK-10590: arm :imx7d: correct iomuxc-lpsr daisy chainAdrian Alonso2015-04-06-3/+3
| | | | | | | | | * Correct daisy chain settings for LPSR iomux controller * Add IOMUX_LPSR_SEL_INPUT_OFS only when pad is identified to be part of lpsr-iomuxc domain Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* MLK-10522-2: arm: imx7d: add iomuxc-lpsr i2c pad settingsAdrian Alonso2015-04-03-1/+4
| | | | | | | | | | * Add IMX7D iomuxc-lpsr I2C1 and I2C2 pad configuration settings * Input select offset input_sel_ofs = 0x05xx + IOMUX_LPSR_SEL_INPUT_OFS allows to access register in iomuxc controller for imx_iomux_v3_setup_pad I2C daisy chaing configuration. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10566: arm :imx7d: fix iomuxc-lpsr daisy chain settingsAdrian Alonso2015-04-03-0/+4
| | | | | | | | | | | | | | * For IOMUXC LPSR pads when daisy chain register needs to be set the result offsets for sel_input register is incorrect as base address is 0x302C0000 and the passed offset does not resolve to the intended input sel pad register; input sel base offset should start in 0x30330000. * Add an addiotional fixed offset of 0x70000 to address the input sel offset: INPUT_SEL = 0x302C0000 + 0x70000 + sel_input_ofs. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10524: iMX6x: Implement workaround for Cortex-A9 errata 845369Nitin Garg2015-03-31-0/+5
| | | | | | | | | Under very rare timing circumstances, transitioning into streaming mode might create a data corruption. Present on Two or more processors or 1 core with ACP, all revisions. This erratum can be worked round by setting bit[22] of the undocumented Diagnostic Control Register to 1. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* MLK-10513 mx7: HAB: Fix HAB RVT addresses to unified sectionYe.Li2015-03-31-11/+5
| | | | | | | Incorrect hab_rvt addresses were used for getting HAB functions. Need to change to addresses in unified section. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10503 imx:mx6qp add missed macroPeng Fan2015-03-30-1/+4
| | | | | | is_mx6dqp should be only applied for MX6 Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10499 imx:mx6qp update printed cpu infoPeng Fan2015-03-30-5/+14
| | | | | | We should print "MX6QP Rev1.0", but not "MX6Q Rev2.0". Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10496: Check the PL310 version for applying errataNitin Garg2015-03-27-11/+15
| | | | | | | | | | | Apply errata based on PL310 version instead of compile time. Also set Prefetch offset to 15, since it improves memcpy performance by 35%. Don't enable Incr double Linefill enable since it adversely affects memcpy performance by about 32MB/s and reads by 90MB/s. Tested with 4K to 16MB sized src and dst aligned buffer. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* MLK-10492-1 imx: mx7d: Update LCDIF clock settingsYe.Li2015-03-27-7/+54
| | | | | | | | To support lower clock frequency, needs to set post divider and test divider in PLL_VIDEO. So update LCDIF clock settings function to support this feature. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10477-2 imx: mx7d: Add EPDC clock init and base addressYe.Li2015-03-27-0/+34
| | | | | | Ungate the EPDC clock at system up if the EPDC is enabled Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10477-1 imx: mx7d: Add QoS settings for EPDCYe.Li2015-03-27-0/+34
| | | | | | Add the QoS settings function which is used for EPDC Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10448-5 imx: mx6qp: Enable PRG clock for IPUYe.Li2015-03-23-0/+6
| | | | | | | | | The i.MX6QP has a PRG module, need to enable its clock for using IPU. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Brown Oliver <B37094@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10448-4 mx6: hab : Remove the cache issue workaroud in hab for i.MX6QPYe.Li2015-03-23-2/+3
| | | | | | | Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround for i.MX6QP. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10448-3 mx6: ccm: Change the clock settings for i.MX6QPYe.Li2015-03-23-22/+56
| | | | | | | | | | Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes. A new CONFIG_MX6QP is introduced here and is used for the CCM difference. At default CONFIG_MX6Q is enabled along with the CONFIG_MX6QP. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10448-2 mx6: L2cache: Enable the double line fill for i.MX6DQPYe.Li2015-03-23-0/+3
| | | | | | | Since i.MX6DQP has fixed the L2 cache issue, enable the double line fill feature to provide better performance. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10448-1 mx6: Add MX6DQP CPU rev typeYe.Li2015-03-23-2/+10
| | | | | | | | Add new cpu type for i.MX6DQP and providing a dynamical detecting function. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10385-3 imx: mx7: Enable rawnand clock at init for APBH-DMAYe.Li2015-03-10-0/+4
| | | | | | For APBH-DMA enabled case, we have to enable rawnand clock for mxs_dma_init. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10385-2 imx: nand: Update GPMI NAND driver to support MX7DYe.Li2015-03-09-3/+3
| | | | | | Update GPMI NAND driver and BCH head file with definitions for CONFIG_MX7 Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10385-1 imx: apbh_dma: Update APBH-DMA for MX7DYe.Li2015-03-09-6/+6
| | | | | | Update APBH-DMA driver and head files with definitions for CONFIG_MX7 Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10215 Add elan init in i.MX6SL-EVK boardHaibo Chen2015-03-05-1/+3
| | | | | | | | | | | | | | | | | | | | EPDC board contain a elan touch screen, this screen is a i2c slave. If this EPDC board connect to i.MX6SL-EVK board, after uboot boot up, if we do i2c operation, like i2c probe, then the i2c bus block. This is due to the elan touch screen i2c slave. This device needs to do some initialization opearation before its i2c operation, otherwise this i2c device pull down the i2c clk line, and make the i2c bus hang. This means elan needs a special flow on i2c before its address is acked, otherwise the i2c bus will be hang. This patch is a workaround, it add a void function which is defined as a weak symbol in i2c driver, and it is called before every i2c operation. In mx6slevk, this function was overwrite to execute elan initialization. So that, for mx6slevk board, it will initialize elan before every i2c operation, but for other boards, it just work as before. Signed-off-by: Haibo Chen <haibo.chen@freescale.com>
* MLK-10363-2 imx: mx7: Enable SNVS clockYe.Li2015-03-04-0/+2
| | | | | | Enable SNVS clock in clock_init function as default enabled clock. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10363-1 udc: Update i.MX udc driver to support MX7Ye.Li2015-03-04-24/+2
| | | | | | | Update driver codes and registers define for MX7. Implement udc callback function in MX7 arch. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10361 imx: mx7d arm2: Change to use WDOG_B resetYe.Li2015-03-04-3/+22
| | | | | | | | | | | | | | | | | | | The default u-boot reset is a internal WDOG reset (warm reset on i.MX6) which does not have power and DDR reset. So the peripherals and DDR may meet problem. When using the internal WDOG reset on i.MX7D ARM2 boards, we meets two DDR issues: 1. On 12x12 ARM2, sometimes the system may hang in DCD because the DDRC Operating Mode does not become to normal. 2. On 19x19 ARM2, the reset always brings system to USB download because the DDR3 turns to unstable. On the i.MX7D ARM2 board, the WDOG_B signal connects to POR_B or PMIC_PWRON. This gives a chance to use a stronger reset. So in this patch, we set the IOMUX for WDOG_B pin and enable WDOG_B signal output in WDOG WCR register. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10360 imx: iomux-v3: Fix the driver issue for MUX_CTL with offset 0Ye.Li2015-03-03-2/+1
| | | | | | | | | | | | | The IOMUX-v3 driver checks the MUX_CTL register offset. If the offset is zero, it will skip the MUX_CTL register setting. This behavior is correct for previous platforms like i.MX6, but on i.MX7, the IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00 is at offset 0. Thus, it causes the MUX setting to this pin always not working. This fix removes this condition checking since it is unnecessary. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10206-2 imx: mx7: Fix temperature checking issueYe.Li2015-02-06-14/+16
| | | | | | | | It is the same temperature checking problem as mx6 codes. The patch fixes this issue by blocking the booting until the temperature is lower than TEMPERATURE_HOT. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10206-1 imx: mx6: Fix temperature checking issueYe.Li2015-02-06-15/+17
| | | | | | | | | The current temperature checking will not stop booting when temperature is over TEMPERATURE_MAX value. This is a bug in the temperature polling. The patch fixes this issue by blocking the booting until the temperature is lower than TEMPERATURE_HOT. Signed-off-by: Ye.Li <B37916@freescale.com>
* ARM: Fix overflow in MMU setupMarek Vasut2015-02-05-1/+1
| | | | | | | | | | | | | | | | | | | The patch fixes a corner case where adding size to DRAM start resulted in a value (1 << 32), which in turn overflew the u32 computation, which resulted in 0 and it therefore prevented correct setup of the MMU tables. The addition of DRAM bank start and it's size can end up right at the end of the address space in the special case of a machine with enough memory. To prevent this overflow, shift the start and size separately and add them only after they were shifted. Hopefully, we only have systems in tree which have DRAM size aligned to 1MiB boundary. If not, this patch would break such systems. On the other hand, such system would be broken by design anyway. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> (cherry picked from commit 221a49d5bd4a512596c03bbc59fb28f4ef48bf6e)
* MLK-10200 imx: mx7: Add M4 booting supportYe.Li2015-02-05-2/+18
| | | | | | Implement the auxiliary core booting for Cortex M4 on i.MX7 Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10195 imx: mx7: Fix build warning related to mxs_lcd_initYe.Li2015-02-04-1/+1
| | | | | | | | | | | Fix the warning below by adding function declare: drivers/video/mxsfb.c: In function 'mxs_lcd_init': drivers/video/mxsfb.c:92:2: warning: implicit declaration of function 'mxs_set_lcdclk' [-Wimplicit-function-declaration] mxs_set_lcdclk(panel->isaBase, PS2KHZ(mode->pixclock)); Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10178-3 i2c:mxc Add i2c support for i.MX7DPeng Fan2015-02-04-0/+3
| | | | | | Add i2c support for i.MX7D. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10176-9 imx: mx7: add plugin boot supportYe.Li2015-02-04-0/+103
| | | | | | Add mx7_plugin.S to support building plugin boot image. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10176-8 imx: mx7: add HAB security supportYe.Li2015-02-04-0/+353
| | | | | | Add HAB files for secure boot and image athentication. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10176-7 imx: mx7: add system counter supportYe.Li2015-02-04-1/+156
| | | | | | | | Generic timer is added to mx7d, so add support for this. In uboot, only system counter is needed, the timer events are not needed. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10176-6 imx: mx7: Modify GPT timer driver for mx7Ye.Li2015-02-04-2/+8
| | | | | | | | | | Modify the GPT common platform driver for mx7 which only use 24Mhz OSC as clock source. Note: at default, the mx7d will use system counter as timer. The GPT is disabled. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10176-5 imx: mx7: Update IOMUX v3 driver for LPSRYe.Li2015-02-04-1/+16
| | | | | | | | Since mx7d introduces some LPSR IOMUX pins, add new base to IOMUX v3 driver for these LPSR pins. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10176-4 imx: mx7: Add arch level supportYe.Li2015-02-04-7/+590
| | | | | | | | | | Introduce a new cpu type MXC_CPU_MX7D and relevant functions for mx7d. Implement the soc.c for various system level functions like: temperature check, arch init, get mac fuse, boot mode get/apply, etc. Additional, enable building imx common platform files for mx7d. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10176-3 imx: mx7: Add clock supportYe.Li2015-02-04-0/+2270
| | | | | | | | | | | | | | | | | Since a new CCM with clock root slice is introduced in mx7. Provide several APIs for configuring root slice in clock_slice.c Implement clock/PLL relevant functions for modules in mx7d to enable/disable/set/get clocks or PLLs. From mx7d, the clocks are initialized in function "void clock_init(void)", such as UART, USDHC, ECSPI, USB, WDOG, WEIM. These module don't have clock setting functions in driver and BSP, and assume the clock is setup before entering into u-boot. Because default root clock is 24Mhz OSC, we have to setup these default clocks. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
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