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* arm/s5pxx: Fix get_timer_masked to get the time.Zhong Hongbo2012-09-01-5/+17
| | | | | | | | | | | In general, The get_timer_masked function get the system time, no the number of ticks. Such as the nand_wait_ready will use get_timer_masked to delay the operations. And change the system time to adopt to the CONFIG_SYS_HZ. Signed-off-by: Hongbo Zhong <bocui107@gmail.com> Tested-by: Jaehoon Chung<jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0Rajeshwari Shinde2012-09-01-11/+18
| | | | | | | | | | This patch modifies the pinmux settings of MMC and UART as per Exynos5250 Rev 1.0. It also corrects the gpio offset calculations. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: CLOCK: Add BPLL supportRajeshwari Shinde2012-09-01-7/+24
| | | | | | | | This patch adds support for BPLL clock. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0Rajeshwari Shinde2012-09-01-1/+14
| | | | | | | | | | | MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5: DDR3: Add DDR3 memory setup for Exynos5250 Rev 1.0Rajeshwari Shinde2012-09-01-0/+65
| | | | | | | | The patch adds the memory initialization sequence of DDR3. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0Rajeshwari Shinde2012-09-01-108/+126
| | | | | | | | | Define additional registers for clock control in Exynos5250 Rev 1.0 Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARCH: SPL: Add parametric board initializerRajeshwari Shinde2012-09-01-0/+97
| | | | | | | | | | | | | Add a structure for table-driven configuration mechanism such that no recompilation is needed to update the configuration parameters, rather than hard-coding board initialization parameters. Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0Tetsuyuki Kobayashi2012-09-01-7/+14
| | | | | | | | | save_boot_params_default() in cpu.c accesses uninitialized stack area when it compiled with -O0 (not optimized). This patch removes save_boot_params_default() and put the equivalent in start.S Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Tom Rini <trini@ti.com>
* tegra20: Remove armv4t build flagsAllen Martin2012-09-01-14/+0
| | | | | | | | | | | These flags were necessary when building tegra20 as a single binary that supported ARM7TDMI and Cortex A9. Now that the ARM7TDMI support is split into a separate SPL, this is no longer necessary. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* arm: enable libgcc build for SPLAllen Martin2012-09-01-1/+1
| | | | | | | | | Enable the building of private libgcc for SPL Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra20: enable SPL for tegra20 boardsAllen Martin2012-09-01-280/+5
| | | | | | | | | | | Add SPL options to tegra20 config files and enable SPL build for tegra20 boards. Also remove redundant code from u-boot that is not contained in SPL. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra20: move SDRAM param save to later in bootAllen Martin2012-09-01-5/+0
| | | | | | | | | | | | Move warmboot_save_sdram_params() to later in the boot sequence. This code relies on devicetree to get the address of the memory controller and with upcoming changes for SPL boot it gets called early in the boot process when devicetree is not initialized yet. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: add tegra20 support to arm720tAllen Martin2012-09-01-1/+637
| | | | | | | | | | | | | Add support for tegra20 arm7 boot processor. This processor is used to power on the Cortex A9 and transfer control to it. In tegra this processor is an ARM7TDMI not an ARM720T, but since we don't use cache it was easier to just reuse the ARM720T code as the processors are otherwise identical except for cache and MMU. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: Fix arm720t SPL buildAllen Martin2012-09-01-0/+13
| | | | | | | | | | | | Take a few SPL fixes from armv7 and apply them to arm720t: -Use dummy exception handlers for SPL build -Initialize relocation register r9 to 0 for the case of no relocation -ifdef out interrupt handler code Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra20: move tegra20 SoC code to arch/arm/cpu/tegra20-commonAllen Martin2012-09-01-13/+59
| | | | | | | | | | | In preparation for splitting out the armv4t code from tegra20, move the tegra20 SoC code to arch/arm/cpu/tegra20-common. This code will be compiled armv4t for the arm7tdmi and armv7 for the cortex A9. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra20: rename tegra2 -> tegra20Allen Martin2012-09-01-81/+81
| | | | | | | | | | This is make naming consistent with the kernel and devicetree and in preparation of pulling out the common tegra20 code. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: add basic support for the Broadcom BCM2835 SoCStephen Warren2012-09-01-0/+304
| | | | | | | | | | | | | | | | | This SoC is used in the Raspberry Pi, for example. For more details, see: http://www.broadcom.com/products/BCM2835 http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf. Initial support is enough to boot to a serial console, execute a minimal set of U-Boot commands, download data over a serial port, and boot a Linux kernel. No storage or network drivers are implemented. GPIO driver originally by Vikram Narayanan <vikram186@gmail.com> with many fixes from myself. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* ARM: arm1176: enable instruction cache in arch_cpu_init()Stephen Warren2012-09-01-0/+7
| | | | | | | | | Note that this affects all users of the ARM1176 CPU that enable CONFIG_ARCH_CPU_INIT, not just the BCM2835 SoC, potentially such as tnetv107x. Cc: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* snowball: Adding board specific cache cleanup routineMathieu J. Poirier2012-09-01-0/+26
| | | | | | | | Following ARM's reference manuel for initializing the cache - the kernel won't boot otherwise. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* armv7: Adding cpu specific cache managmenentMathieu J. Poirier2012-09-01-0/+8
| | | | | | | | Some CPU (i.e u8500) need more cache management before launching the Linux kernel. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* u8500: Enabling power to MMC device on AB8500 V2Mathieu J. Poirier2012-09-01-28/+89
| | | | | | | | | Register mapping has changed on power control chip between the first and second revision. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Tom Rini <trini@ti.com>
* u8500: Moving processor-specific functions to cpu area.Mathieu J. Poirier2012-09-01-0/+81
| | | | | | | | | | Functions such as providing power to the MMC device and reading the processor version register should be in the cpu area for access by multiple u8500-based boards. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Tom Rini <trini@ti.com>
* snowball: applying power to LAN and GBF controllersMathieu J. Poirier2012-09-01-3/+15
| | | | | | | | LAN and GBF need to be powered explicitely, doing so with interface to AB8500 companion chip. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* snowball: Moving to ux500.v2 addess scheme for PRCMU accessMathieu J. Poirier2012-09-01-32/+71
| | | | | | | | Addresses between ux500.v1 and ux500.v2 have changed slightly, hence mandating a review of the PRCMU access methods. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* snowball: Adding CPU clock initialisationMathieu J. Poirier2012-09-01-4/+37
| | | | | Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* snowball: Adding architecture dependent initialisationMathieu J. Poirier2012-09-01-6/+91
| | | | | | | Enabling timers and clocks in PRCMU and cleaning up mailbox. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* u8500: Moving prcmu to cpu directoryMathieu J. Poirier2012-09-01-1/+220
| | | | | | | | This is to allow the prcmu functions to be used by multiple u8500-based processors. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
* snowball: Add support for ux500 based snowball boardMathieu J. Poirier2012-09-01-0/+212
| | | | | | | | | | | Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> Acked-by: Tom Rini <trini@ti.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Conflicts: drivers/gpio/Makefile
* davinci, c6x: Always use C version of reset codeTom Rini2012-09-01-84/+34
| | | | | | | | | We can safely use the same reset code written in C for both Davinci and C6X platforms. In addition the C version of the code is marginally smaller on Davinci. Tested-by: Matt Porter <mporter@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* am33xx evm: Update secure_emif_sdram_config during ddr initSatyanarayana, Sandhya2012-09-01-1/+7
| | | | | | | | | | | | | | | This patch updates secure_emif_sdram_config with the same value written to sdram_config during ddr3 initialization. During suspend/resume, this value is copied into sdram_config. With this, a write to sdram_config at the end of resume sequence which triggers an init sequence can be avoided. Without this register write in place, the DDR_RESET line goes low for a few cycles during resume which is a violation of the JEDEC spec. Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
* da8xx/hawkboard: Add support for ohci host controllerSughosh Ganu2012-09-01-0/+111
| | | | | | | | | | Also enable the ohci port on hawkboard. These additions result in an increased u-boot size -- adjust the same accordingly in the board's config. Move the usb header for da8xx platforms under arch-davinci. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
* armv7: Make lowlevel_init.S's lowlevel_init do ABI compatible stackTom Rini2012-09-01-0/+1
| | | | | | | | Make sure that when we setup the stack before calling s_init() we have the stack have 8-byte alignment for ABI compliance. Tested-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Rini <trini@ti.com>
* omap4/5/am33xx: Make lowlevel_init available to all armv7 platformsTom Rini2012-09-01-24/+57
| | | | | | | | | | | | | | Make the lowlevel_init function that these platforms have which just sets up the stack and calls a C function available to all armv7 platforms. As part of this we change some of the macros that are used to be more clear. Previously (except for am335x evm) we had been setting CONFIG_SYS_INIT_SP_ADDR to a series of new defines that are equivalent to simply referencing NON_SECURE_SRAM_END. On am335x evm we should have been doing this initially and do now. Cc: Sricharan R <r.sricharan@ti.com> Tested-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Add support, update omap3 McSPI driverTom Rini2012-09-01-0/+5
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Correct MMC1, remove MMC2 supportTom Rini2012-09-01-4/+9
| | | | | | | | - Correct the MMC1 base offset - Remove MMC2 (that area is reserved and not MMC2). - Add the real BOOT_DEVICE_MMC2 value Signed-off-by: Tom Rini <trini@ti.com>
* i.MX28: bug fixes in PMU configuration codeStathis Voukelatos2012-09-01-6/+6
| | | | | | Signed-off-by: Stathis Voukelatos <stathis.voukelatos@linn.co.uk> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com>
* MX28: Move the u-boot.bd info CPUDIR/SOCDIRMarek Vasut2012-09-01-0/+14
| | | | | | | | This gets us rid of duplication of the same file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mxs: rename mx28.c to mxs.c as it is common to i.MX233 and i.MX28 SoCsOtavio Salvador2012-09-01-1/+1
| | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: Clarify why we poweroff in case of brownout in 5v conflictOtavio Salvador2012-09-01-0/+4
| | | | | | | | If VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes unreliable but this wasn't clear on code so a comment has been added to clarify it. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: Reowork SPL to use 'mxs' prefix for methodsOtavio Salvador2012-09-01-112/+112
| | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: prefix register structs with 'mxs' prefixOtavio Salvador2012-09-01-124/+124
| | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: prefix register acessor macros with 'mxs' prefixOtavio Salvador2012-09-01-517/+517
| | | | | | | As the register accessing mode is the same for all i.MXS SoCs we ought to use 'mxs' prefix intead of 'mx28'. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mxs: reorganize source directory for easy sharing of code in i.MXS SoCsOtavio Salvador2012-09-01-1/+1
| | | | | | | | | Most code can be shared between i.MX23 and i.MX28 as both are from i.MXS family; this source directory structure makes easy to share code among them. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
* MX28: use a clear name for DDR2 initializationOtavio Salvador2012-09-01-6/+6
| | | | | | | | | The mx28 prefix has been added to the initialization data and function so it is clear by which SoC it is used as i.MX233 will have a specific one. While on that, we also change it to static. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Marek Vasut <marex@denx.de>
* MX28: extend print_cpuinfo() to use chip informationOtavio Salvador2012-09-01-2/+40
| | | | | | | The information now is gathered from HW_DIGCTL_CHIPID register and includes the chip modem and revision on the output. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* imx: Use a clear identification of an unidentified CPU typeOtavio Salvador2012-09-01-2/+2
| | | | | | | | | | In case an unidentified CPU type is detected it now returns i.MX??, in a const char. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* Enable the EMAC clock in at91_macb_hw_init().Markus Hubig2012-09-01-0/+4
| | | | | | Signed-off-by: Markus Hubig <mhubig@imko.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm : Atmel : add at91sam9x5ek board supportBo Shen2012-09-01-2/+508
| | | | | | | | | | | | Add at91sam9x5ek board support, this board support the following SoCs AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35 Using at91sam9x5ek_nandflash to configure for the board Now only supports NAND with software ECC boot up Signed-off-by: Bo Shen <voice.shen@atmel.com> [move MAINTAINERS entry to right place] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* DaVinci DA8xx: fix set_cpu_clk_info()Laurence Withers2012-09-01-9/+14
| | | | | | | | | | | | | | | | | | | | | | For the DA8xx family of SoCs, the set_cpu_clk_info() function was not initialising the DSP frequency, leading to 'bdinfo' command output such as: [...snip...] ARM frequency = 300 MHz DSP frequency = -536870913 MHz DDR frequency = 300 MHz This commit provides a separate implementation of set_cpu_clk_info() for the DA8xx SoCs that initialises the DSP frequency to zero (since currently the DSP is not enabled by U-Boot on any DA8xx platform). The separate implementation is justified because there is no common code between DA8xx and the other SoC families. It is now much easier to understand the flow of the two separate functions. Signed-off-by: Laurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Hadli, Manjunath <manjunath.hadli@ti.com> Cc: Heiko Schocher <hs@denx.de>
* DaVinci DA8xx: replace magic number for DDR speedLaurence Withers2012-09-01-1/+4
| | | | | | | | | | Replace a magic number for the DDR2/mDDR PHY clock ID with a proper definition. In addition, don't request this clock ID on DA830 hardware, which does not have a DDR2/mDDR PHY (or associated PLL controller). Signed-off-by: Laurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
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