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| | * imx6: fix random hang when download by usbFrank Li2013-12-17-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | ROM did not invalidate L1 cache when download by usb Need invalidate L1 cache before enable cache Signed-off-by: Huang yongcai <b20788@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com>
| | * mx6: clock: Fix the calculation of PLL_ENET frequencyFabio Estevam2013-12-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the mx6 quad reference manual, the DIV_SELECT field of register CCM_ANALOG_PLL_ENETn has the following meaning: "Controls the frequency of the ethernet reference clock. - 00 - 25MHz - 01 - 50MHz - 10 - 100MHz - 11 - 125MHz" Current logic does not handle the 25MHz case correctly, so fix it. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * nitrogen6x: Move setup_sata to common partGiuseppe Pagano2013-12-17-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move setup_sata function definition from platform file nitrogen6x.c to arch/arm/imx-common/sata.c to avoid code duplication. Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Eric Nelson <eric.nelson@boundarydevices.com>
| | * i.MX6 (DQ/DLS): use macros for mux and pad declarationsEric Nelson2013-12-17-2106/+2118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows the use of either or both declarations from the files mx6q_pins.h and mx6dl_pins.h. All board files should include <asm/arch/mx6-pins.h> with one of the following defined in boards.cfg MX6Q - for boards targeting i.MX6Q or i.MX6D MX6DL - for boards targeting i.MX6DL MX6S - for boards targeting i.MX6S MX6QDL - for boards that support any of the above with run-time detection Pad declarations will be MX6_PAD_x for single-variant boards and MX6Q_PAD_x and MX6DL_PAD_x for boards supporting both processor classes. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
| | * imx-common: remove extraneous semicolon from macroEric Nelson2013-11-27-2/+2
| | | | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| | * i.MX6DQ/DLS: whitespace: Align IOMUX_PAD column in declarationsEric Nelson2013-11-13-490/+490
| | | | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| | * i.MX6DQ/DLS: remove unused pad declarationsEric Nelson2013-11-13-1043/+0
| | | | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| | * i.MX6DQ: Add Pinmux settings that are present in mainline and Dual-Lite/SoloEric Nelson2013-11-13-0/+24
| | | | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| | * i.MX6DQ/DLS: remove useless mux/pad declarationsEric Nelson2013-11-13-160/+0
| | | | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| | * i.MX6DQ/DLS: replace pad names with their Linux kernel equivalentsEric Nelson2013-11-13-1761/+1761
| | | | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * | ARM: AM43xx: GP_EVM: Add support for DDR3Lokesh Vutla2013-12-18-16/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | ARM: AM43xx: EPOS_EVM: Add support for LPDDR2Lokesh Vutla2013-12-18-3/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | ARM: AM33xx+: Update ioregs to pass different valuesLokesh Vutla2013-12-18-9/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently same value is programmed for all ioregs. This is not the case for all SoC's like AM4372. So adding a structure for ioregs and updating in all board files. And also return from config_cmd_ctrl() and config_ddr_data() functions if data is not passed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [trini: Fixup dxr2, cm_t335, adapt pcm051 rev3] Signed-off-by: Tom Rini <trini@ti.com>
| * | ARM: AM43xx: clocks: Update DPLL detailsLokesh Vutla2013-12-18-14/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating the Multiplier and Dividers value for all DPLLs. Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value returned the MPU DPLL is locked. At different OPPs follwoing are the MPU locked frequencies. OPP50 300MHz OPP100 600MHz OPP120 720MHz OPPTB 800MHz OPPNT 1000MHz According to the latest DM following is the OPP table dependencies: VDD_CORE VDD_MPU OPP50 OPP50 OPP50 OPP100 OPP100 OPP50 OPP100 OPP100 OPP100 OPP120 So at different OPPs of MPU it is safest to lock CORE at OPP_NOM. Following are the DPLL locking frequencies at OPP NOM: Core locks at 1000MHz Per locks at 960MHz LPDDR2 locks at 266MHz DDR3 locks at 400MHz Touching AM33xx files also to get DPLL values specific to board but no functionality difference. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | ARM: AM43xx: mux: Update mux dataLokesh Vutla2013-12-18-0/+45
| | | | | | | | | | | | | | | | | | | | | Updating the mux data for UART, adding data for i2c0 and mmc. And also updating pad_signals structure. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | ARM: AM43xx: Update Current Booting devices listLokesh Vutla2013-12-18-3/+10
| | | | | | | | | | | | | | | | | | | | | Current Booting devices list is different from that of AM33xx. Updating the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | ARM: AM43xx: Select clk source for Timer2Lokesh Vutla2013-12-18-0/+4
| | | | | | | | | | | | | | | | | | Selecting the Master osc clk as Timer2 clock source. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | ARM: AM43XX: board: add support for reading onboard EEPROMSekhar Nori2013-12-18-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Add support for reading onboard EEPROM to enable board detection. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | ARM: AM43xx: Adapt to ti_armv7_common.h config fileLokesh Vutla2013-12-18-1/+1
| | | | | | | | | | | | | | | | | | | | | Use ti_armv7_common.h config file to inclde the common configs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | ARM: AM43xx: Update the base addresses of modulesLokesh Vutla2013-12-18-13/+15
| | | | | | | | | | | | | | | | | | | | | PRCM, timer base addresses and offsets are different from AM33xx. Updating the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | Merge remote-tracking branch 'u-boot-pxa/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-18-0/+1
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| | * | ARM: pxa: prevent PXA270 occasional reboot freezesSergei Ianovich2013-12-18-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum 71 of PXA270M Processor Family Specification Update (April 19, 2010) explains that watchdog reset time is just 8us insead of 10ms in EMTS. If SDRAM is not reset, it causes memory bus congestion and the device hangs. We put SDRAM in selfresh mode before watchdog reset, removing potential freezes. Signed-off-by: Sergei Ianovich <ynvich@gmail.com> CC: Marek Vasut <marex@denx.de>
| * | | arm: tegra: Fix the CPU complex reset masksAlban Bedel2013-12-18-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPU complex reset masks are not matching with the datasheet for the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20 and T30 the register consist of groups of 4 bits, with one bit for each CPU core. On T20 the 2 high bits of each group are always stubbed as there is only 2 cores. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swrren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: support SKU b1 of Tegra30Alban Bedel2013-12-18-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the Tegra30 SKU b1 and treat it like other Tegra30 chips. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Reviewed-by: Julian Scheel <julian.scheel@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | Tegra114: Do not program CPCON field for PLLXThierry Reding2013-12-18-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PLLX no longer has the CPCON field on Tegra114, so do not attempt to program it. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | Tegra114: Fix PLLX M, N, P init settingsJimmy Zhang2013-12-18-24/+59
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The M, N and P width have been changed from Tegra30. The maximum value for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should be set accordingly. Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: OMAP5: clocks: Update MPU settings for OPP_NOMLokesh Vutla2013-12-12-12/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per the latest 0.6 version of DM for OMAP5430 ES2.0, MPU_GCLK is given as 1000MHz. In order to achieve this DPLL_MPU should be locked at 2000MHz. Fixing the same and cleaning the previously used dpll values. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | ARM: DRA7xx: Change clk divider settingLokesh Vutla2013-12-12-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Commit "armv7: hw_data: change clock divider setting" updates the setting for m6 divider for 20MHz sys_clk frequency. But missed to update for other sys_clk frequencies. Doing the same. Reported-by: Rajendran, Vinothkumar <vinothr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | arm: omap: abb: add missing includeNikita Kiryanov2013-12-12-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ABB code uses LDELAY but does not include the header that provides its definition. Include the header. Cc: Tom Rini <trini@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Nishanth Menon <nm@ti.com>
| * | arm: am437: Fix offset for USB registersDan Murphy2013-12-12-2/+2
| | | | | | | | | | | | | | | | | | Fix the offset for the USB clock registers Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | ARM: OMAP4: Move TEXT_BASE down to non-HS limitLokesh Vutla2013-12-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the current scenario SPL size is being overlapped with the public stack and not allowing any OMAP4 device to boot. So the suggestion came up was to move the TEXT_BASE down to non-HS limit. Fixing the same and also moving the SRAM_SCRATCH_SPACE_ADDR up to the end of image downloadable area. Discussion on this can be seen here: https://www.mail-archive.com/u-boot@lists.denx.de/msg127147.html Tested on OMAP4460 PANDA. Reported-by: Chao Xu <caesarxuchao@gmail.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFFTom Rini2013-12-12-0/+8
| | | | | | | | | | | | | | | | | | | | | Test on Beaglebone white over cpsw, usb ether and SD card (read and write), performance increased, crc32 of data matches. Signed-off-by: Tom Rini <trini@ti.com>
| * | Revert "ARM: move interrupt_init to before relocation"Albert ARIBAUD2013-12-11-1/+2
| | | | | | | | | | | | | | | | | | | | | Revert commit 0f5141e9 which causes boards starting in FLASH to try and write to a FLASH location. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mmcTom Rini2014-01-09-0/+77
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| * | | socfpga/dwmmc: Adding DesignWare MMC driver support for SOCFPGAChin Liang See2014-01-09-0/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To add the DesignWare MMC driver support for Altera SOCFPGA. It required information such as clocks and bus width from platform specific files (SOCFPGA handoff files) Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2014-01-09-19/+9
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| * | | | sh: sh2: Remove CONFIG_SH2A definition from asm/processor.hNobuhiro Iwamatsu2014-01-09-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SH2 and SH2A use a common header. Both checks are not necessary. This removes CONFIG_SH2A definition from asm/processor.h. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | sh: sh4: Remove CONFIG_SH4A definition from source codeNobuhiro Iwamatsu2014-01-09-13/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SH4 and SH4A are compatible. But some instructions are different from these. In Linux kernel, It is treated as a separate CPU, but for now, I think that there is no need to divide especially in the U-Boot. This removes CONFIG_SH4A definition from source code, SH4A is treated as SH4. And this fix white space. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | sh: sh2: Change CONFIG_SYS_HZ to CONFIG_SH_CMT_CLK_FREQNobuhiro Iwamatsu2014-01-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_HZ of SH2 is not used as frequency of base timer. This is the correct clock of CMT. This changes from CONFIG_SYS_HZ to CONFIG_SH_CMT_CLK_FREQ, in order to use CONFIG_SYS_HZ as clock of CMT. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | | | sh: sh4: Add CONFIG_SH4 definition to config.mk of SH4Nobuhiro Iwamatsu2014-01-08-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | sh: sh3: Add CONFIG_SH3 definition to config.mk of SH3Nobuhiro Iwamatsu2014-01-08-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | sh: sh2: Add CONFIG_SH2 definition to config.mk of SH2Nobuhiro Iwamatsu2014-01-08-1/+1
| |/ / / | | | | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | | sandbox: Add a prototype for cleanup_before_linux()Simon Glass2014-01-08-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This function is defined but has no prototype declaration. Add it. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | sandbox: Add facility to save/restore sandbox stateSimon Glass2014-01-08-4/+490
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is often useful to be able to save out the state from a sandbox test run, for analysis or to restore it later to continue a test. Add generic infrastructure for doing this using a device tree binary file. This is a flexible tagged file format which is already supported by U-Boot, and it supports hierarchy if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Hung-ying Tyan <tyanh@chromium.org>
* | | | sandbox: Allow reading/writing of RAM bufferSimon Glass2014-01-08-3/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is useful to be able to save and restore the RAM contents of sandbox U-Boot either for setting up tests, for later analysys, or for chaining together multiple tests which need to keep the same memory contents. Add a function to provide a memory file for U-Boot. This is read on start-up and written when shutting down. If the file does not exist on start-up, it will be created when shutting down. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | sandbox: Add -i option to enter interactive modeSimon Glass2014-01-08-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Normally when U-Boot starts with a command (-c option) it quits when the command completes. Normally this is what is requires, since the test is likely complete. Provide an option to jump into the console instead, so that debugging or other tasks may be performed before quitting. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | sandbox: Allow the console to work earlierSimon Glass2014-01-08-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With sandbox, errors and problems may be reported before console_init_f() is executed. For example, an argument may not parse correctly or U-Boot may panic(). At present this output is swallowed so there is no indication what is going wrong. Adjust the console to deal with a very early sandbox setup, by detecting that there is no global_data yet, and calling os functions in that case. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | sandbox: Implement the bootm command for sandboxSimon Glass2014-01-08-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When sandbox does a 'bootm' to run a kernel we cannot actually execute it. So just exit sandbox, which is essentially what U-Boot does on other archs. Also, allow sandbox to use bootm on any kernel, so that it can be used to test booting of kernels from any architecture. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | sandbox: Allow return from board_init_f()Simon Glass2014-01-08-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The execution flow becomes easier if we can return from board_init_f() as ARM does. We can control things from start.c instead of having to call back into that file from other places. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | sandbox: Correct help message <arg> garblingSimon Glass2014-01-08-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The <arg> is displayed for options with no argument, and omitted for those with an argument. Swap this around. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-10-31 09:33:53 +0000