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* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-11-07-41/+72
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| * ARM: mxs: Enable DCDC converter for battery bootMarek Vasut2013-10-31-0/+2
| | | | | | | | | | | | | | | | | | | | In case the board detected sufficient voltage for battery boot, make sure the DCDC converter is ON and the board is not running only from linregs, otherwise an instability will be observed. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6: Remove PAD_CTL_DSE_120ohm from i.MX6DL's IPU1_DI0_PIN4 pinOtavio Salvador2013-10-31-1/+1
| | | | | | | | | | | | | | | | This removes the PAD_CTL_DSE_120ohm as done for i.MX6Q's IPU1_DI0_PIN4 pin definition and makes it aligned with 3.0.35-4.1.0 and 3.12 mainline kernel. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| * mx5: lowlevel_init: Remove unused macroFabio Estevam2013-10-31-6/+0
| | | | | | | | | | | | | | setup_wdog macro is not used anywhere, so just remove it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * ARM: mx5: Enable L2 cacheFabio Estevam2013-10-31-0/+6
| | | | | | | | | | | | Enable L2 cache for improving the system performance. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * ARM: mxs: Setup stack in JTAG modeMarek Vasut2013-10-17-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case the MX23/MX28 is switched into JTAG mode via the BootMode select switches, the BootROM bypasses the CPU core registers initialization. This in turn means that the Stack Pointer (SP) register is not set as it is in every other mode of operation, but instead is only zeroed out. To prevent U-Boot SPL from crashing in this obscure JTAG mode, configure the SP to point at the CONFIG_SYS_INIT_SP_ADDR if the SP is zeroed out. Note that in case the SP is already configured, we must preserve that exact SP value and must not modify it. This is important since in every other mode but the JTAG mode, the SPL returns into the BootROM and BootROM in turn loads U-Boot itself. If the SP were to be corrupted, the BootROM won't be able to continue it's operation after returned from SPL and the system would crash. Finally, add the JTAG mode switch identifier, so it's not recognised as Unknown mode. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br>
| * ARM: mxs: tools: Use mkimage for BootStream generationMarek Vasut2013-10-17-9/+10
| | | | | | | | | | | | | | | | | | | | | | Now that mkimage can generate an BootStream for i.MX23 and i.MX28, use the mkimage as a default tool to generate the BootStreams instead of the elftosb tool. This cuts out another obscure dependency. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * mx6: compute PLL PFD frequencies rather than using definesPierre Aubert2013-10-17-25/+42
| | | | | | | | | | Signed-off-by: Pierre Aubert <p.aubert@staubli.com> CC: Stefano Babic <sbabic@denx.de>
* | Merge branch 'u-boot-atmel/master' into 'u-boot-arm/master'Albert ARIBAUD2013-11-05-0/+9
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| * | at91: add defines for reset typeRoger Meier2013-11-04-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Roger Meier <r.meier@siemens.com> Acked-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | arm: atmel: at91sam9n12ek: add usb host supportBo Shen2013-11-04-0/+2
| |/ | | | | | | | | | | | | Add usb host support for at91sam9n12ek board. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | ARM: OMAP5: DDR3: Change io settingsSRICHARAN R2013-11-01-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The change from 0x64656465 to 0x64646464 is to remove the weak pull enabled on DQS, nDQS lines. This pulls the differential signals in the same direction which is not intended. So disabling the weak pulls improves signal integrity. On the uEVM there are 4 DDR3 devices. The VREF for 2 of the devices is powered by the OMAP's VREF_CA_OUT pins. The VREF on the other 2 devices is powered by the OMAP's VREF_DQ_OUT pins. So the net effect here is that only half of the DDR3 devices were being supplied a VREF! This was clearly a mistake. The second change improves the robustness of the interface and was specifically seen to cure corruption observed at high temperatures on some boards. With the above two changes better memory stability was observed with extended temperature ranges around 100C. Signed-off-by: Sricharan R <r.sricharan@ti.com>
* | dra7xx_evm: Enabled UART-boot mode and add dra7xx_evm_uart3 buildMinal Shah2013-11-01-0/+1
| | | | | | | | | | | | | | | | | | | | | | UART booting is supported on this SoC, but via UART3 rather than UART1. Because of this we must change the board to use UART3 for all console access (only one UART is exposed on this board and a slight HW mod is required to switch UARTs). Signed-off-by: Minal Shah <minal.shah@ti.com> [trini: Make apply to mainline, reword commit] Signed-off-by: Tom Rini <trini@ti.com>
* | am335x: Enable CONFIG_OMAP_WATCHDOG supportTom Rini2013-11-01-0/+4
| | | | | | | | | | | | | | There is a board-specific portion for calling watchdog enable itself, in main U-Boot. Signed-off-by: Tom Rini <trini@ti.com>
* | am33xx, davinci: Create and use <asm/davinci_rtc.h>Tom Rini2013-11-01-50/+56
|/ | | | | | | Create a common header file for the RTC IP block that is shared between davinci and am33xx. Signed-off-by: Tom Rini <trini@ti.com>
* zynq: Use arch_cpu_init() instead of lowlevel_init()Michal Simek2013-10-17-0/+6
| | | | | | | | | | | Zynq lowlevel_init() was implemented in C but stack pointer is setup after function call in _main(). Move architecture setup to arch_cpu_init() which is call as the first function in board_init_f() which already have correct stack pointer. Reported-by: Sven Schwermer <sven.schwermer@tuhh.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* microblaze: Fix watchdog initializationMichal Simek2013-10-16-4/+3
| | | | | | | | | | | The patch: "blackfin: Move blackfin watchdog driver out of the blackfin arch folder." (sha1: e9a389a18477c1c57a0b30e9ea8f4d38c6e26e63) changed hw_watchdog_init() prototype which didn't match with Microblaze one. This patch fixes the driver and Microblaze initialization. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Coding Style cleanup: drop some excessive empty linesWolfgang Denk2013-10-14-2/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Coding Style cleanup: remove trailing empty linesWolfgang Denk2013-10-14-5/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Coding Style cleanup: replace leading SPACEs by TABsWolfgang Denk2013-10-14-42/+42
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Drop changes for PEP 4 following python tools] Signed-off-by: Tom Rini <trini@ti.com>
* Coding Style cleanup: remove trailing white spaceWolfgang Denk2013-10-14-88/+88
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* ARM: omap4-panda: Add MAC address creation for pandaDan Murphy2013-10-14-0/+4
| | | | | | | | Add a MAC address create based on the OMAP die ID registers. Then poplulate the ethaddr enviroment variable so that the device tree alias can be updated prior to boot. Signed-off-by: Dan Murphy <dmurphy@ti.com>
* ARM: omap4: Update sdram setting for panda rev A6Dan Murphy2013-10-14-0/+4
| | | | | | | | | | OMAP4 panda rev A6 is a 4430 es2.3 IC with an updated memory part. The panda rev A6 uses Elpida 2x4Gb memory and no longer uses Micron so the timings needs to be updated Signed-off-by: Dan Murphy <dmurphy@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-10-08-621/+69
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| * socfpga: Adding System Manager driverChin Liang See2013-10-07-1/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding System Manager driver which will configure the pin mux for real hardware Cyclone V development kit (not Virtual Platform) Signed-off-by: Chin Liang See <clsee@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
| * omap1510inn: arm925t: remove supportAlbert ARIBAUD2013-10-07-608/+0
| | | | | | | | | | | | | | | | | | omap1510inn is orphan and has been for years now. Reove it and, as it was the only arm925t target, also remove arm925t support. Update doc/README.scrapyard accordingly. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * ARM: IGEP0033: Update timing to run DDR at 400MHz.Enric Balletbo i Serra2013-10-07-12/+12
| | | | | | | | | | | | | | We can run the DDR at 400MHz, so update the timings for that purpose. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com> Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2013-10-08-2/+25
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| * | spi: exynos: Support word transfersRajeshwari Shinde2013-10-08-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since SPI register access is so expensive, it is worth transferring data a word at a time if we can. This complicates the driver unfortunately. Use the byte-swapping feature to avoid having to convert to/from big endian in software. This change increases speed from about 2MB/s to about 4.5MB/s. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | armv7: hw_data: change clock divider setting.Poddar, Sourav2013-10-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clock requirement for qspi clk is 192 Mhz. According to the below formulae, f dpll = f ref * 2 * m /(n + 1) clockoutx2_Hmn = f dpll / (hmn+ 1) fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz For clockoutx2_Hmn to be 768, hmn + 1 should be 4. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | omap5: add qspi supportMatt Porter2013-10-07-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | Add QSPI definitions and clock configuration support. Signed-off-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | | ARM: virtualization: replace verbose license with SPDX identifierAndre Przywara2013-10-07-35/+3
|/ / | | | | | | | | | | | | | | | | The original creation of arch/arm/cpu/armv7/{virt-v7.c,nonsec_virt.S} predates the SPDX conversion, so the original elaborate license statements sneaked in. Fix this by replacing them with the proper abbreviation. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-10-04-1/+455
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| * ARM: extend non-secure switch to also go into HYP modeAndre Przywara2013-10-03-9/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the KVM and XEN hypervisors to be usable, we need to enter the kernel in HYP mode. Now that we already are in non-secure state, HYP mode switching is within short reach. While doing the non-secure switch, we have to enable the HVC instruction and setup the HYP mode HVBAR (while still secure). The actual switch is done by dropping back from a HYP mode handler without actually leaving HYP mode, so we introduce a new handler routine in our new secure exception vector table. In the assembly switching routine we save and restore the banked LR and SP registers around the hypercall to do the actual HYP mode switch. The C routine first checks whether we are in HYP mode already and also whether the virtualization extensions are available. It also checks whether the HYP mode switch was finally successful. The bootm command part only calls the new function after the non-secure switch. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * ARM: add SMP support for non-secure switchAndre Przywara2013-10-03-1/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the non-secure switch is only done for the boot processor. To enable full SMP support, we have to switch all secondary cores into non-secure state also. So we add an entry point for secondary CPUs coming out of low-power state and make sure we put them into WFI again after having switched to non-secure state. For this we acknowledge and EOI the wake-up IPI, then go into WFI. Once being kicked out of it later, we sanity check that the start address has actually been changed (since another attempt to switch to non-secure would block the core) and jump to the new address. The actual CPU kick is done by sending an inter-processor interrupt via the GIC to all CPU interfaces except the requesting processor. The secondary cores will then setup their respective GIC CPU interface. While this approach is pretty universal across several ARMv7 boards, we make this function weak in case someone needs to tweak this for a specific board. The way of setting the secondary's start address is board specific, but mostly different only in the actual SMP pen address, so we also provide a weak default implementation and just depend on the proper address to be set in the config file. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * ARM: trigger non-secure state switch during bootm executionAndre Przywara2013-10-03-0/+13
| | | | | | | | | | | | | | | | | | To actually trigger the non-secure switch we just implemented, call the switching routine from within the bootm command implementation. This way we automatically enable this feature without further user intervention. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * ARM: add C function to switch to non-secure stateAndre Przywara2013-10-03-0/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core specific part of the work is done in the assembly routine in nonsec_virt.S, introduced with the previous patch, but for the full glory we need to setup the GIC distributor interface once for the whole system, which is done in C here. The routine is placed in arch/arm/cpu/armv7 to allow easy access from other ARMv7 boards. We check the availability of the security extensions first. Since we need a safe way to access the GIC, we use the PERIPHBASE registers on Cortex-A15 and A7 CPUs and do some sanity checks. Boards not implementing the CBAR can override this value via a configuration file variable. Then we actually do the GIC enablement: a) enable the GIC distributor, both for non-secure and secure state (GICD_CTLR[1:0] = 11b) b) allow all interrupts to be handled from non-secure state (GICD_IGROUPRn = 0xFFFFFFFF) The core specific GIC setup is then done in the assembly routine. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * ARM: add assembly routine to switch to non-secure stateAndre Przywara2013-10-03-0/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While actually switching to non-secure state is one thing, another part of this process is to make sure that we still have full access to the interrupt controller (GIC). The GIC is fully aware of secure vs. non-secure state, some registers are banked, others may be configured to be accessible from secure state only. To be as generic as possible, we get the GIC memory mapped address based on the PERIPHBASE value in the CBAR register. Since this register is not architecturally defined, we check the MIDR before to be from an A15 or A7. For CPUs not having the CBAR or boards with wrong information herein we allow providing the base address as a configuration variable. Now that we know the GIC address, we: a) allow private interrupts to be delivered to the core (GICD_IGROUPR0 = 0xFFFFFFFF) b) enable the CPU interface (GICC_CTLR[0] = 1) c) set the priority filter to allow non-secure interrupts (GICC_PMR = 0xFF) Also we allow access to all coprocessor interfaces from non-secure state by writing the appropriate bits in the NSACR register. The generic timer base frequency register is only accessible from secure state, so we have to program it now. Actually this should be done from primary firmware before, but some boards seems to omit this, so if needed we do this here with a board specific value. The Versatile Express board does not need this, so we remove the frequency from the configuration file here. After having switched to non-secure state, we also enable the non-secure GIC CPU interface, since this register is banked. Since we need to call this routine also directly from the smp_pen later (where we don't have any stack), we can only use caller saved registers r0-r3 and r12 to not mess with the compiler. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * ARM: add secure monitor handler to switch to non-secure stateAndre Przywara2013-10-03-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A prerequisite for using virtualization is to be in HYP mode, which requires the CPU to be in non-secure state first. Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine which switches the CPU to non-secure state by setting the NS and associated bits. According to the ARM architecture reference manual this should not be done in SVC mode, so we have to setup a SMC handler for this. We create a new vector table to avoid interference with other boards. The MVBAR register will be programmed later just before the smc call. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
| * ARM: prepare armv7.h to be included from assembly sourceAndre Przywara2013-10-03-1/+5
| | | | | | | | | | | | | | | | armv7.h contains some useful constants, but also C prototypes. To include it also in assembly files, protect the non-assembly part appropriately. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-10-02-900/+442
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| * Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-10-02-34/+313
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| | * i.MX6DQ/DLS: Add pad MX6_PAD_GPIO_1__USB_OTG_IDEric Nelson2013-09-27-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds the pad to i.MX6DQ and changes the i.MX6DLS declaration to match the Linux kernel declaration. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
| | * mx6: Fix use of improper value in enable_ipu_clockPierre Aubert2013-09-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The value MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET that was used to initialize the CCGR3 register caused an undefined value for CG0. Signed-off-by: Pierre Aubert <p.aubert@staubli.com> CC: Stefano Babic <sbabic@denx.de> Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
| | * i.MX6DL/S: add drive-strength back to pads DISP0_DAT2/DAT10Eric Nelson2013-09-20-2/+2
| | | | | | | | | | | | | | | | | | | | | This patch fixes a regression introduced by commit 87d720e0. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
| | * mx6slevk: Add Ethernet supportFabio Estevam2013-09-20-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | mx6slevk has a SMSC8720 connected in RMII mode. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| | * ARM: arch-mx6: fix PLL2_PFD2_FREQMarkus Niebel2013-09-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | according to the manual frequency of PLL2 PFD2 is 396.000.000 instead of 400.000.000 Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de> Acked-by: Stefano Babic <sbabic@denx.de>
| | * Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2013-09-13-7/+31
| | |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: MAINTAINERS boards.cfg Signed-off-by: Stefano Babic <sbabic@denx.de>
| | * | mx27: add missing constant for mx27trem2013-09-10-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add some missing constant (chip select, ...) Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr> Signed-off-by: Eric Jarrige <eric.jarrige@armadeus.org> Acked-by: Stefano Babic <sbabic@denx.de>
| | * | ARM: mxs: Receive r0 and r1 passed from BootROMMarek Vasut2013-09-10-24/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure value in register r0 and r1 is preserved and passed to the board_init_ll() and mxs_common_spl_init() where it can be processed further. The value in r0 can be configured during the BootStream generation to arbitary value, r1 contains pointer to return value from CALL'd function. This patch also clears the value in r0 before returning to BootROM to make sure the BootROM is not confused by this value. Finally, this patch cleans up some comments in the start.S file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
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