summaryrefslogtreecommitdiff
path: root/arch
Commit message (Collapse)AuthorAgeLines
* malloc_f: enable SYS_MALLOC_F by default if DM is onMasahiro Yamada2015-03-28-15/+0
| | | | | | | | | | | | | | This option has a bool type, not hex. Fix it and enable it if CONFIG_DM is on because Driver Model always requires malloc memory. Devices are scanned twice, before/after relocation. CONFIG_SYS_MALLOC_F should be enabled to use malloc memory before relocation. As it is board-independent, handle it globally. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Robert Baldyga <r.baldyga@samsung.com>
* malloc_f: remove redundant defalut values of CONFIG_SYS_MALLOC_F_LENMasahiro Yamada2015-03-28-9/+0
| | | | | | | | | | The default value of CONFIG_SYS_MALLOC_F_LEN is defined by ./Kconfig as 0x400. Each defconfig or Kconfig need not repeat the same value. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Robert Baldyga <r.baldyga@samsung.com>
* m68k: remove arch/m68k/lib/board.cMasahiro Yamada2015-03-28-645/+0
| | | | | | | | | | All the M68000 boards have switched to Generic Board. This file is no longer necessary. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Huan Wang <alison.wang@freescale.com> Cc: Angelo Dureghello <angelo@sysam.it> Reviewed-by: Simon Glass <sjg@chromium.org>
* generic-board: select SYS_GENERIC_BOARD for some architecturesMasahiro Yamada2015-03-28-7/+13
| | | | | | | | | | | | We have done with the generic board conversion for all the boards of ARC, Blackfin, M68000, MicroBlaze, MIPS, NIOS2, Sandbox, X86. Let's select SYS_GENERIC_BOARD for those architectures, so we can tell which architecture has finished the conversion at a glance. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
* generic-board: move __HAVE_ARCH_GENERIC_BOARD to KconfigMasahiro Yamada2015-03-28-29/+14
| | | | | | | | Move the option to Kconfig renaming it to CONFIG_HAVE_GENERIC_BOARD. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
* x86: quark: Enable on-chip ethernet controllersBin Meng2015-03-24-0/+19
| | | | | | | | | | Intel Quark SoC integrates two 10/100 ethernet controllers which can be connected to an external RMII PHY. The MAC IP is from Designware. Enable this support with the existing U-Boot Designware MAC driver so that the ethernet port on Intel Galileo board can be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* arch/x86/cpu/quark/mrc.c: Switch to U_BOOT_DATE / U_BOOT_TIMETom Rini2015-03-24-1/+2
| | | | | | | | | | | Using __DATE__ and __TIME__ results in an error due to -Werror=date-time with gcc-4.9 (__DATE__ / __TIME__ might prevent reproducible builds) so switch these over to U_BOOT_DATE / U_BOOT_TIME Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: MRC codes clean upBin Meng2015-03-24-1049/+955
| | | | | | | | | | | | This patch cleans up the quark MRC codes coding style by: - Remove BIT0/1../31 defines from mrc_util.h - Create names for the documented BITs and use them - For undocumented single BITs, use (1 << n) directly - For undocumented ORed BITs, use the hex number directly - Remove redundancy parenthesis all over the codes - Replace to use lower case hex numbers Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* remove unnecessary version.h includesRob Herring2015-03-24-37/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
* ARM: UniPhier: remove unnecessary ifdef conditionalMasahiro Yamada2015-03-24-2/+0
| | | | | | | | The callee (arch/arm/lib/cache-cp15.c) has a #ifdef CONFIG_SYS_DCACHE_OFF conditional. The same conditional in the caller (arch/arm/mach-uniphier/cache_uniphier.c) is redundant. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: UniPhier: disable L2 cache by lowlevel_init of U-Boot properMasahiro Yamada2015-03-24-17/+5
| | | | | | | | | | | | The L2 cache is used as a temporary SRAM on SPL. Now the secondary CPUs store the necessary code for jumping to Linux on their L1 I-caches. So, the L2 cache can be disabled much earlier, at the very entry of U-Boot proper (lowlevel_init). This makes the boot sequence clearer. Also, as the L1 cache has been disabled by the start.S, enable_caches() does not need to do it again. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: UniPhier: optimize kicking secondary CPUs codeMasahiro Yamada2015-03-24-72/+38
| | | | | | | | | | | | | | Currently, the secondary CPU(s) are kicked three times: Boot ROM ---(kick)--> SPL ---(kick)--> U-boot ---(kick)--> Linux. It makes the boot sequence very complicated. This commit merges the first and the second kicks, so the secondary CPU(s) can directly jump from SPL to Linux. arch/arm/mach-uniphier/smp.S is no longer necessary. Linux boot test passed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: UniPhier: fix typos in commentsMasahiro Yamada2015-03-24-12/+13
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: UniPhier: add empty lowlevel_init to U-boot properMasahiro Yamada2015-03-24-0/+13
| | | | | | | To remove the ifdef conditional of CONFIG_SKIP_LOWLEVEL_INIT, add late_lowlevel_init.S to U-Boot proper. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: UniPhier: use CONFIG_SPL_STACK to define SPL stack pointerMasahiro Yamada2015-03-24-4/+13
| | | | | | | Ifdef conditionals for CONFIG options are not Kconfig-friendly. Instead, define CONFIG_SPL_STACK to prepare for Kconfig moves. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: UniPhier: enable Driver Model and UART on SPLMasahiro Yamada2015-03-24-3/+10
| | | | | | | | | | | Enable CONFIG_SPL_DM and CONFIG_SPL_SERIAL_SUPPORT, which provide Driver Model UART support on SPL. CONFIG_SYS_SPL_MALLOC_{START,SIZE} should be dropped because simple malloc is preferred on SPL. Dlmalloc requires some static variables on .data section that is not available yet for NOR boot mode etc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: UniPhier: move UART pin settings to SPLMasahiro Yamada2015-03-24-49/+96
| | | | | | | | The UniPhier platform is going to enable Driver Model and UART support on SPL. Move UART pin settings to early_pin_init(), which is called from SPL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: UniPhier: move platform devices to SPLMasahiro Yamada2015-03-24-2/+2
| | | | | | | | | | Since we do not have OF_CONTROL support for SPL, platform devices are necessary to enable Driver Model on SPL. To prepare for that, move platdevice.o to SPL and enable it by CONFIG_SPL_DM. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: UniPhier: include PH1-LD4 Makefile from PH1-sLD8Masahiro Yamada2015-03-24-16/+1
| | | | | | | | The two Makefiles arch/arm/mach-uniphier/{ph1-ld4,ph1-sld8}/Makefile are completely the same. We can improve the maintainability by having one to include the other. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: UniPhier: remove unnecessary CONFIG_SYS_SOCMasahiro Yamada2015-03-24-3/+0
| | | | | | | | Since commit a86ac9540e20 (ARM: UniPhier: include <mach/*.h> instead of <asm/arch/*.h>), UniPhier platform does not need the symbolic link arch/arm/include/asm. This option is not necessary either. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-03-20-0/+26
|\
| * ARM: atmel: sama5d4: set non-secured for peripheralsBo Shen2015-03-18-0/+9
| | | | | | | | | | | | | | When access the programmable secure peripherals address space, it needs set them to non-secured. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * ARM: atmel: armv7: move spl lds to armv7 directoryBo Shen2015-03-18-0/+0
| | | | | | | | | | | | | | As the u-boot-spl.lds is used only for armv7 SoCs (includes sama5d3 and sama5d4), so move it to armv7 directory. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * ARM: at91: at91sam9rlek: add mci supportWu, Josh2015-03-18-0/+17
| | | | | | | | | | | | | | | | This patch enable the MCI support for at91sam9rlek board. Signed-off-by: Josh Wu <josh.wu@atmel.com> [rebase on ToT] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-03-18-1/+18
|\ \ | |/ |/|
| * mx6: soc: Switch to cold resetDirk Behme2015-03-13-0/+18
| | | | | | | | | | | | | | | | Disable the warm reset and enable the cold reset for a more reliable restart ('reset'). This is taken from the Linux kernel, see imx_src_init() in arch/arm/mach-imx/src.c. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
| * imx:mx6 remove duplicated includesPeng Fan2015-03-13-1/+0
| | | | | | | | | | | | There is no need to include asm/bootm.h twice, so remove one. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-03-05-604/+3463
| |\
* | | powerpc: ppc4xx: remove korat board supportMasahiro Yamada2015-03-17-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Larry Johnson <lrj@acm.org>
* | | powerpc: mpc5xxx: remove galaxy5200 board supportMasahiro Yamada2015-03-17-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Eric Millbrandt <emillbrandt@dekaresearch.com>
* | | powerpc: ppc4xx: remove W7OLMC/W7OLMG board supportMasahiro Yamada2015-03-17-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | They have not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Erik Theisen <etheisen@mindspring.com>
* | | powerpc: mpc5xxx: remove aev, TB5200 board supportMasahiro Yamada2015-03-17-6/+0
| | | | | | | | | | | | | | | | | | | | | They have not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | powerpc: ppc4xx: remove JSE board supportMasahiro Yamada2015-03-17-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Stephen Williams <steve@icarus.com>
* | | powerpc: mpc5xxx: remove BC3450 board supportMasahiro Yamada2015-03-17-4/+0
| | | | | | | | | | | | | | | | | | | | | This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2015-03-15-68/+77
|\ \ \
| * | | ARM: UniPhier: adjust device trees for business transferMasahiro Yamada2015-03-15-68/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Panasonic's System LSI products, UniPhier SoC family, have been transferred to Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | | ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973, 621766Nishanth Menon2015-03-13-25/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RX51 has a secure logic which uses different parameters compared to traditional implementation. So, make the generic secure acr write over-ride-able by board file and refactor rx51 code to use this. While at it, enable the OMAP3 specific errata code for 454179, 430973, 621766. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766Nishanth Menon2015-03-13-21/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the OMAP3 specific errata code for 454179, 430973, 621766 and while at it, remove legacy non-revision checked errata logic. Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configurationNishanth Menon2015-03-13-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update to existing recommendation for L2ACTLR configuration to prevent system instability and optimize performance. These apply to both OMAP5 and DRA7. Reported-by: Vivek Chengalvala <vchengalvala@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870Praveen Rao2015-03-13-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the workaround for ARM errata 798870 for OMAP5 / DRA7 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced here as well. Signed-off-by: Praveen Rao <prao@ti.com> Signed-off-by: Angela Stegmaier <angelabaker@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with omap_smc1Nishanth Menon2015-03-13-17/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | omap_smc1 is now generic enough to remove duplicate omap3_gp_romcode_call logic that omap3 introduced. As part of this change, move to using the generic lowlevel_init.S for omap3 as well. Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCsNishanth Menon2015-03-13-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is in preperation of using generic cross OMAP code. Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | ARM: OMAP: Change set_pl310_ctrl_reg to be genericNishanth Menon2015-03-13-10/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function. So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation. While at this, smc #0 is maintained as handcoded assembly thanks to various gcc version eccentricities, discussion thread: http://marc.info/?t=142542166800001&r=1&w=2 Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | ARM: Introduce erratum workaround for 621766Nishanth Menon2015-03-13-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 621766: Under a specific set of conditions, executing a sequence of NEON or vfp load instructions can cause processor deadlock Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set L1NEON to 1 Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | ARM: Introduce erratum workaround for 430973Nishanth Menon2015-03-13-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 430973: Stale prediction on replaced inter working branch causes Cortex-A8 to execute in the wrong ARM/Thumb state Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE to 1 Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | ARM: Introduce erratum workaround for 454179Nishanth Menon2015-03-13-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 454179: Stale prediction may inhibit target address misprediction on next predicted taken branch Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE and disable branch size mispredict to 1 Also provide a hook for SoC specific handling to take place if needed. Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | | ARM: Introduce erratum workaround for 798870Nishanth Menon2015-03-13-2/+51
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add workaround for Cortex-A15 ARM erratum 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." Implementations for SoC families such as Exynos, OMAP5/DRA7 etc will be widely different. Every SoC has slightly different manner of setting up access to L2ACLR and similar registers since the Secure Monitor handling of Secure Monitor Call(smc) is diverse. Hence an weak function is introduced which may be overriden to implement SoC specific accessor implementation. Based on ARM errata Document revision 18.0 (22 Nov 2013) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-03-10-88/+1158
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: README Signed-off-by: Tom Rini <trini@konsulko.com>
| * | | apalis/colibri_t30: fix MMC/SD card detect GPIOsMarcel Ziswiler2015-03-04-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the MMC/SD card detect GPIOs for Apalis T30 which got broken by the following commit: 2b2b50bc8748 "dm: tegra: dts: Use TEGRA_GPIO() macro for all GPIOs" While at it also re-add the comments describing which particular Apalis/Colibri pins those GPIOs are on. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Stefan Agner <stefan.agner@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | dm: tegra: dts: add aliases for spi on apalis_t30Marcel Ziswiler2015-03-04-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All boards with a SPI interface have a suitable spi alias except Apalis T30. Add these missing aliases just as the following commit did for the others: d2f60f93325a "dm: tegra: dts: Add aliases for spi on tegra30 boards" Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-12-29 10:31:43 +0000