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* am33xx: Fix warning with CONFIG_DISPLAY_CPUINFOTom Rini2013-05-10-5/+1
| | | | | | | | The arm_freq and ddr_freq variables are unused, so remove. Fixup whitespace slightly while in here. Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Tom Rini <trini@ti.com>
* davinci: handle CONFIG_SYS_CLE_MASK and CONFIG_SYS_ALE_MASKEric Benard2013-05-10-0/+9
| | | | | | | | | | | | | these variables are curently defined in several config files but the driver doesn't use them and defaults to hardcoded values in nand_defs.h It's interesting to be able to change this hardcoded valude when the hardware is not using the default adress signals to drive ALE and CLE and two configuration defines already exist for this purpose so use them. Signed-off-by: Eric Bénard <eric@eukrea.com>
* da850: provide davinci_enable_uart0Eric Benard2013-05-10-0/+10
| | | | | | | | this is needed to bring UART0 out of reset but this function currently only exists for dm644x/355/365/646x when da850 (at least am1808 also need it). Signed-off-by: Eric Bénard <eric@eukrea.com>
* ARM: OMAP5: Fix warm reset with USB cable connectedLokesh Vutla2013-05-10-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Warm reset on OMAP5 freezes when USB cable is connected. Fix requires PRM_RSTTIME.RSTTIME1 to be programmed with the time for which reset should be held low for the voltages and the oscillator to reach stable state. There are 3 parameters to be considered for calculating the time, which are mostly board and PMIC dependent. -1- Time taken by the Oscillator to shut + restart -2- PMIC OTP times -3- Voltage rail ramp times, which inturn depends on the PMIC slew rate and value of the voltage ramp needed. In order to keep the code in u-boot simple, have a way for boards to specify a pre computed time directly using the 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' option. If boards fail to specify the time, use a default as specified by 'CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC' instead. Using the default value translates into some ~22ms and should work in all cases. However in order to avoid this large delay hiding other bugs, its recommended that all boards look at their respective data sheets and specify a pre computed and optimal value using 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC' In order to help future board additions to compute this config option value, add a README at doc/README.omap-reset-time which explains how to compute the value. Also update the toplevel README with the additional option and pointers to doc/README.omap-reset-time. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [rnayak@ti.com: Updated changelog and added the README] Signed-off-by: Rajendra Nayak <rnayak@ti.com>
* OMAP5: USB: hsusbtll_clkctrl has to be in hw_auto for USB to workLubomir Popov2013-05-10-1/+1
| | | | | | | | | | | | USB TLL clocks do not support 'explicit_en', only 'hw_auto' control (R. Sricharan). cm_l3init_hsusbtll_clkctrl has to be moved to the clk_modules_hw_auto_essential[] array in order to make the clock work. This fix is needed (but not sufficient) for USB EHCI operation in U-Boot. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
* Add DDR3 support for IGEP COM AQUILA/CYGNUS.Enric Balletbo i Serra2013-05-10-0/+17
| | | | | | These boards uses Samsung K4B2G1646E-BIH9 a 2Gb E-die DDR3 SDRAM. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
* arm: omap: emif: Fix DDR3 init after warm resetLokesh Vutla2013-05-10-3/+8
| | | | | | | | | | | | | | | | EMIF supports a global warm reset mode, during which the EMIF keeps the SDRAM content. But if leveling is enabled at the time of warm reset for DDR3, the following steps needs to be done after warm reset: 1) Keep EMIF in self refresh mode. 2) Reset PHY to bring back the PHY to a known state. 3) Start Levelling procedure. Doing the same. And also enabling DLL lock and code output after warm reset. Tested on OMAP5432 ES2.0 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* OMAP5: I2C: Set I2C_BUS_MAX to 5 to enable I2C4 and I2C5Lubomir Popov2013-05-10-1/+1
| | | | | | | | | | | I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. In order to be able to select one of these buses however, I2C_BUS_MAX has to be set to 5; do this here. Please note that for working bus selection, a fix to the i2c driver is required as well (subject of a separate patch). Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
* OMAP5: I2C: Add I2C4 and I2C5 basesLubomir Popov2013-05-10-0/+2
| | | | | | | | I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. The I2C4 and I2C5 base addresses were however not defined; do this here. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
* OMAP5: I2C: Enable i2c5 clocksLubomir Popov2013-05-10-0/+1
| | | | | | | I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms. The i2c5 clock was however not enabled; do this here. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
* am33xx: add pll and clock support for TI814x CPSWMatt Porter2013-05-10-2/+102
| | | | | | | Enables required PLLs and clocks for CPSW on TI814x. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* i2c: zynq: Add support for Xilinx ZynqMichal Simek2013-04-30-0/+2
| | | | | | | | | Support Xilinx Zynq i2c controller. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@ti.com>
* mmc: Add support for Xilinx Zynq sdhci controllerMichal Simek2013-04-30-0/+5
| | | | | | | Add support for SD, MMC and eMMC card on Xilinx Zynq. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* zynq: Move macros to hardware.hMichal Simek2013-04-30-0/+2
| | | | | | | | Add all fixed addresses to hardware.h and change petalinux configuration to support this. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* net: gem: Fix gem driver on 1Gbps LANMichal Simek2013-04-30-1/+33
| | | | | | | | | | The whole driver used 100Mbps because of zc702 rev B. Fix problem with not setup proper clock for gem1. This is generic approach for clk setup. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* zynq: Move scutimer baseaddr to hardware.hMichal Simek2013-04-30-1/+3
| | | | | | | | Move baseaddr to hardware.h to be shared between configurations. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: zynq: Rename XPSS_ prefix to ZYNQ_ for hardcoded SoC addressesMichal Simek2013-04-30-6/+6
| | | | | | | | XPSS prefix was used in past and it is obsolete for quite some time. Let's use correct SoC name which is Zynq. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* arm: zynq: U-Boot udelay < 1000 FIXDavid Andrey2013-04-30-9/+37
| | | | | | | | | Rework the __udelay function of U-Boot Zynq Arch to handle delay < 1000 usec Signed-off-by: David Andrey <david.andrey@netmodule.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-arm into HEADTom Rini2013-04-18-55/+221
|\ | | | | | | | | | | | | | | | | | | Quick manual fixup to merge the USB boot related defines and TPM related defines. Conflicts: include/configs/exynos5250-dt.h Signed-off-by: Tom Rini <trini@ti.com>
| * exynos: Correct use of 64-bit divisionSimon Glass2013-04-17-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | The current code is causing errors like this on my toolchains: /usr/x86_64-pc-linux-gnu/armv7a-cros-linux-gnueabi/binutils-bin/2.22/ ld.bfd.real: failed to merge target specific data of file /usr/lib/gcc/ armv7a-cros-linux-gnueabi/4.7.x-google/libgcc.a(_divdi3.o) Use do_div() to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Tegra: Split tegra_get_chip_type() into soc & sku funcsTom Warren2013-04-15-36/+83
| | | | | | | | | | | | | | | | | | | | | | As suggested by Stephen Warren, use tegra_get_chip() to return the pure CHIPID for a Tegra SoC (i.e. 0x20 for Tegra20, 0x30 for Tegra30, etc.) and rename tegra_get_chip_type() to reflect its true function, i.e. tegra_get_chip_sku(), which returns an ID like TEGRA_SOC_T25, TEGRA_SOC_T33, etc. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * Tegra: Fix MSELECT clock divisors for T30/T114.Tom Warren2013-04-15-8/+6
| | | | | | | | | | | | | | | | | | A comparison of registers between our internal NV U-Boot and u-boot-tegra/next showed some discrepancies in the MSELECT clock divisor programming. T20 doesn't have a MSELECT clk src reg. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * Tegra114: Initialize System Counter (TSC) with osc frequencyTom Warren2013-04-15-0/+72
| | | | | | | | | | | | | | | | | | T114 needs the SYSCTR0 counter initialized so the TSC can be read by the kernel. Do it in the bootloader since it's a write-once deal (secure/non-secure mode dependent). Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * Tegra: Configure L2 cache control reg properly.Tom Warren2013-04-15-8/+52
| | | | | | | | | | | | | | | | | | | | Without this change, kernel fails at calling function cache_clean_flush during kernel early boot. Aprocryphally, intended for T114 only, so I check for a T114 SoC. Works (i.e. dalmore 3.8 kernel now starts printing to console). Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Tegra: Restore cp15 VBAR _start vector write for ARMv7Tom Warren2013-04-15-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | A start vector fix was added by AneeshV for OMAP4 (commit 0d479b53), and caused the old monilithic Tegra builds to hang due to an undefined instruction trap. Previously, the code needed to run on both the AVP (ARM7TDI) and A9, and the AVP doesn't have a CP15 register. I corrected this in commit 6d6c0bae w/#ifndef CONFIG_TEGRA, but now that we use SPL, and boot the AVP w/o any ARMv7 code, I can revert my change, and make Aneesh's change apply to Tegra. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: support T33 SKU of Tegra30Stephen Warren2013-04-15-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make U-Boot aware of the T33 SKU of Tegra30, and treat it identically to any other Tegra30. An alternative would be to simply remove the SKU checking from tegra_get_chip_type(); most use of the value most likely simply wants to know the current chip, not the specific SKU. Or, the function could be split into separate tegra_get_chip() and tegra_get_sku() for the cases where differentiation really is required. I wonder whether tegra_get_chip_type() should printf() whenever any unkown chip/SKU is found, although perhaps the function is called so early that the printf() wouldn't actually make it to the UART anyway. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2013-04-16-1/+6
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| * x86: Fix DRAM bank size init with generic boardSimon Glass2013-04-15-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | The intention of the memory init code is that it should work the same with CONFIG_SYS_GENERIC_BOARD and without. This is tricky because dram_init() is called prior to relocation with generic board (matching other archs) and after relocation without generic board. Adjust the init sequence so that dram_init() is not called in the generic board case, which seems like the easiest fix for now. Also ensure that relocation addresses are still calculated. Signed-off-by: Simon Glass <sjg@chromium.org>
* | ARMv7: start.S: stay in HYP mode if u-boot is entered in itAndre Przywara2013-04-15-3/+7
|/ | | | | | | | | | The KVM and Xen hypervisors for the Cortex-A15 virtualization implementation need to be entered in HYP mode. Should the primary board firmware already enter HYP mode (Calxeda firmware does that), we should not deliberately drop back to SVC mode. Since U-boot does not use the MMU, running in HYP mode is just fine. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
* ARM: fix CONFIG_SPL_MAX_SIZE semanticsAlbert ARIBAUD2013-04-14-15/+13
| | | | | | | | | | | | | | | | | | | | Remove SPL-related ASSERT() in arch/arm/cpu/u-boot.lds as this file is never used for SPL builds. Rewrite the ASSERT() in arch/arm/cpu/u-boot-spl.lds to separately test image (text,data,rodata...) size, BSS size, and full footprint each against its own max, and make Tegra boards check full footprint. Also, output section mmutable is not used in SPL builds. Remove it. Finally, update README regarding the (now homogeneous) semantics of CONFIG_SPL_[BSS_]MAX_SIZE and add the new CONFIG_SPL_MAX_FOOTPRINT macro. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reported-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-14-0/+2
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| * spi: mxc_spi: Set master mode for all channelsFabio Estevam2013-04-13-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | ARM: Fix __bss_start and __bss_end in linker scriptsAlbert ARIBAUD2013-04-13-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 3ebd1cbc introduced compiler-generated __bss_start and __bss_end__ and commit c23561e7 rewrote all __bss_end__ as __bss_end. Their merge caused silent and harmless but potentially bug-inducing clashes between compiler- and linker- generated __bss_end symbols. Make __bss_end and __bss_start compiler-only, and create __bss_base and __bss_limit for linker-only use. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reported-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* | BUGFIX: arm: data abort in get_bad_stack_swiTetsuyuki Kobayashi2013-04-13-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | When swi instruction is executed, it is expected to get message "software interrupt" in console and dump registers and reboot, as do_software_interrupt() in arch/arm/lib/interrupts.c. But, actually it causes data abort accessing wrong address in get_bad_stack_swi macro in arch/arm/cpu/v7/start.S. This patch fixes this problem. The same mistake in arch/arm/cpu/{arm1136,arm1176,pxa}/start.S. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
* | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-13-9/+9
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| * | omap3: Display MHz instead of mHz on the consoleman.huber@arcor.de2013-04-12-2/+2
| | | | | | | | | | | | | | | | | | The processor is hopefully running with M(ega)Hz and not with m(illi)Hz. Signed-off-by: Manfred Huber <man.huber@arcor.de>
| * | am335x: Really correct DDR timings on new BeagleBone partTom Rini2013-04-12-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | The previous timings were done on the internal-only A1 board which has different DDR part than all later revs. The timings need a slight adjustment to be correct in all cases with later revs. Signed-off-by: Tom Rini <trini@ti.com>
* | | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-12-1458/+174
|\ \ \ | |/ / |/| | | | | | | | Conflicts: drivers/video/exynos_fb.c
| * | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2013-04-11-0/+5
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| | * | powerpc/usb: Fix usb device-tree fix-upramneek mehresh2013-04-10-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix USB device-tree fixup to properly handle device-tree fixup and print appropriate message when wrong/junk "dr_mode" or "phy_type" are mentioned in hwconfig string Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
| * | | powerpc/lib: fix unsafe register handling in wait_ticksMats Kärrman2013-04-10-6/+11
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If watchdog is enabled, the arch/powerpc/lib/ticks.S::wait_ticks() function calls the function specified by the WATCHDOG_RESET macro. The wait_ticks function depends on the registers r0, r6 and r7 being preserved however that is not guaranteed, e.g. if the reset function is a C function this will probably overwrite r0 and cause an endless loop. The following patch changes to using r14+r15 instead of r6+r7 (to resemble what would have been generated by a C compiler) and saves all necessary registers on the stack. The patch has been tested on a custom MPC5125 based machine using the 512x powerpc architecture. Signed-off-by: Mats Karrman <mats.karrman@tritech.se> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Joakim Tjernlund <joakim.tjernlund@transmode.se> Tested-by: Stefan Roese <sr@denx.de>
| * | Consolidate bool typeYork Sun2013-04-01-177/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'bool' is defined in random places. This patch consolidates them into a single header file include/linux/types.h, using stdbool.h introduced in C99. All other #define, typedef and enum are removed. They are all consistent with true = 1, false = 0. Replace FALSE, False with false. Replace TRUE, True with true. Skip *.py, *.php, lib/* files. Signed-off-by: York Sun <yorksun@freescale.com>
| * | Merge branch 'for-v2013.04'Anatolij Gustschin2013-03-29-1275/+0
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/video/Makefile Signed-off-by: Anatolij Gustschin <agust@denx.de>
| | * | lcd, pxafb: move the pxafb to drivers/videoJeroen Hofstee2013-03-21-651/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the lcd code was compiled unconditionally for pxa also add CONFIG_PXA_LCD to the boards using this framebuffer. Since driver/video contains video and lcd drivers, add lcd to the name to make clear it belongs to common/lcd.c. cc: Anatolij Gustschin <agust@denx.de> cc: Cliff Brake <cliff.brake@gmail.com> cc: Marek Vasut <marek.vasut@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
| | * | lcd, mpc8xx: move the mpc8xx driver to drivers/videoJeroen Hofstee2013-03-21-619/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the lcd code was compiled unconditionally in arch also add CONFIG_MPC8XX_LCD to the boards using this driver. cc: Anatolij Gustschin <agust@denx.de> cc: Wolfgang Denk <wd@denx.de> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
| | * | common/lcd.c: cleanup use of global variablesWolfgang Denk2013-03-21-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | lcd_color_fg and lcd_color_bg had to be declared in board specific code, but were not actually used there; in addition, we have getter / setter functions for these, which were not used either. Get rid of the global variables, and use the getter function where needed (so far no setter calls are needed). Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Alessandro Rubini <rubini@unipv.it> Cc: Anatolij Gustschin <agust@denx.de> Cc: Bo Shen <voice.shen@atmel.com> Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Simon Glass <sjg@chromium.org> Cc: Stelian Pop <stelian@popies.net> Cc: Tom Warren <twarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Jeroen Hofstee <jeroen@myspectrum.nl> [agust: also fixed cm_t35 board while rebasing] Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | | | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-12-21/+27
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| * | | | omap5912-osk: Fix get_timer() and CONFIG_SYS_HZJon Hunter2013-04-10-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function get_timer() should return time in ms and CONFIG_SYS_HZ should be set to 1000 by default. Fix both of these items. Signed-off-by: Jon Hunter <jon-hunter@ti.com>
| * | | | OMAP4: Fix bug in omap4460_volts structLubomir Popov2013-04-10-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The omap4460_volts struct was incorrectly referencing tps62361 instead of twl6030 as PMIC for the core and mm voltages (the tps is used for mpu supply only). This shall lead to bad OPP settings while booting kernel. Fixing it. Fix some comments as well. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
| * | | | am335x: Update timings for the beaglebone againTom Rini2013-04-10-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After further testing we can run DDR at 400MHz so update the timings again. Tested-by: Koen Kooi <koen@dominion.thruhere.net> Signed-off-by: Tom Rini <trini@ti.com>
generated by cgit v1.1 at 2024-11-20 16:05:05 +0000