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| * | | omap3/sys_info: fix printout of OMAP36XX L3 freqencyAndreas Bießmann2013-07-26-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OMAP36xx/OMAP37xx family uses L3 frequency of 200MHz instead of 165MHz used by OMAP34xx/OMAP35xx. Also fix checkpatch warning about alignment. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | arm: omap3: spl: Fix problem with 8bit NAND devicesStefan Roese2013-07-26-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently in OMAP3 SPL, the GPMC for NAND is configured for 16bit access. This patch adds support for 8bit NAND devices as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@ti.com>
| * | | Merge branch 'u-boot/master' into u-boot-arm/masterAlbert ARIBAUD2013-07-25-25573/+2238
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| * | | | ARM: highbank: avoid bss write in timer_initRob Herring2013-07-25-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timer_init function is called before relocation and writes to bss data were corrupting relocation data. Fix this by removing the call to reset_timer_masked. The initial timer count should be 0 or near 0 anyway, so initializing the variables are not needed. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * | | | ARM: highbank: set timer prescaler to 256Rob Herring2013-07-25-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 150MHz clock rate gives u-boot time functions problems and there's no benefit to a fast clock, so lower the rate. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * | | | ARM: highbank: fix get_tbclk value to timer rateRob Herring2013-07-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | get_tbclk should return the timer's frequency, not CONFIG_SYS_HZ. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * | | | ARM: move interrupt_init to before relocationRob Herring2013-07-25-2/+1
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interrupt_init also sets up the abort stack, but is not setup before relocation. So any aborts during relocation will hang and not print out any useful information. Fix this by moving the interrupt_init to after the stack setup in board_init_f. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* | | | powerpc/usb: Depricate usb_phy_type and usb_dr_mode uboot env variablesramneek mehresh2013-08-14-22/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove getting values of usb mode and phy_type from "usb_dr_mode" and "usb_phy_type" uboot env variables. Now, these are determined only from hwconfig string Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | | | fsl/usb: Move USB internal phy definitions to fsl_usb.hramneek mehresh2013-08-14-51/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fsl_usb.h file created to share data bewteen usb platform code and usb ip driver. Internal phy structure definitions moved to this file Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | | | powerpc/mpc85xx:Avoid hardcoded init for serdes block 1 & 2Prabhakar Kushwaha2013-08-14-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is not necessary for all processor to have serdes block 1 & 2. They may have only one serdes block. So, put serdes block 1 & 2 related code under defines Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-08-13-40/+396
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| * | | | powerpc/mpc85xx: Cleanup license header in source filesYork Sun2013-08-12-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the license header introduced by the following patches Add TWR-P10xx board support Add T4240EMU target IDT8T49N222A configuration code Add C29x SoC support Add support for C29XPCIE board Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | 83xx/pcie: fix build error for 83xx pcieRoy Zang2013-08-09-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following build error caused by patch "powerpc/pcie: add PCIe version 3.x support": pcie.c:302:34: error: 'PCI_LTSSM' undeclared (first use in this function) pcie.c:303:15: error: 'PCI_LTSSM_L0' undeclared (first use in this function) Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/mpc8xxx: Fix TIMING_CFG_3[EXT_ACTTOPRE]James Yang2013-08-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TIMING_CFG_3[EXT_ACTTOPRE] register field is 2 bits wide, but the mask omitted the LSB. This patch provides a 2-bit wide mask. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/85xx: Add C29x SoC supportMingkai Hu2013-08-09-0/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features: - 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com>
| * | | | powerpc/pcie: remove PCIe version 3.x define for B4860 and B4420Zang Roy-R619112013-08-09-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | B4860 and B4420 has PCIe version 2.4 IP instead of 3.x Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
| * | | | powerpc/pcie: add PCIe version 3.x supportZang Roy-R619112013-08-09-2/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/rman: fix RMan support for t4240 and b4860Minghuan Lian2013-08-09-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add CONFIG_SYS_DPAA_RMAN macro to t4240 and b4860. 2. Decrease RMan liodn offset number. SET_RMAN_LIODN() is used to set liodn offset of RMan blocks 0-3. For t4240 and b4860, RMan liodn base is assigned to 922, the original offset number is too large that the liodn (base+offset 922+678 = 1600) is greater than 0x500 the maximum liodn number. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/asm: Move function declaration of 'serdes_get_prtcl' to fsl_serdes.hShaveta Leekha2013-08-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It allows files not in the same path to use this function as required by B4 board file Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
| * | | | powerpc/mpc85xx: Add defines for serdes RSTCTL registerShaveta Leekha2013-08-09-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also change the define name SRDS_RSTCTL_SDPD to SRDS_RSTCTL_SDEN, which stands for SerDes enable as mentioned in SerDes module guide Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
| * | | | board/bsc9132qds: Configure DSP DDR controllerPriyanka Jain2013-08-09-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side DDR. They are mapped to PowerPC and DSP CCSR space respectively. BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC and other to DSP side controller. Configure DSP DDR controller similar to PowerPC side DDR controller as memories are exactly similar. Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * | | | board/bsc9132qds: Add DSP side tlb and lawsPriyanka Jain2013-08-09-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a integrated device that contains two powerpc e500v2 cores and two DSP starcores. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 and M3 memory -Creating LAW for 1GB DDR which is connected exclusively to DSP-cores Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/srio-pcie-boot: Avoid the NOR_BOOT macro when boot from SRIO/PCIELiu Gang2013-08-09-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a board (slave) boots from SRIO/PCIE, it would get the instructions from a remote board (master) by SRIO/PCIE interface, and the slave's u-boot image should be built with the SYS_TEXT_BASE=0xFFF80000; So the u-boot of the slave should avoid the NOR_BOOT branch at the booting stage. For example, when a P2041RDB boots from SRIO/PCIE, it will set TLB entry 15 from base address "CONFIG_SYS_MONITOR_BASE & 0xffc00000", and with the 4M size as the boot window in NOR_BOOT branch. Because the CONFIG_SYS_MONITOR_BASE = CONFIG_SYS_TEXT_BASE = 0xFFF80000, so the TLB entry will be from base address 0xffc00000 and with 4M size. Then the u-boot will set TLB entry 14 from base address "CONFIG_SYS_INIT_RAM_ADDR", and with the 16K size as the initial stack window. For the P2041RDB platform, the CONFIG_SYS_INIT_RAM_ADDR = 0xffd00000. So the TLB entry 14 and 15 will be in confliction. There will be right TLB entries configurations when avoid the NOR_BOOT branch and set the boot window from 0xfff00000 with 1M size space. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
| * | | | powerpc/mpc85xx: Workaround for A-005812York Sun2013-08-09-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can result in invalid atomic operations. For u-boot, this erratum only impacts SoCs running in write shadow mode. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/mpc8xxx: Add memory reset controlYork Sun2013-08-09-13/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | JEDEC spec requires the clocks to be stable before deasserting reset signal for RDIMMs. Clocks start when any chip select is enabled and clock control register is set. This patch also adds the interface to toggle memory reset signal if needed by the boards. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/mpc8xxx: Add x4 DDR device supportYork Sun2013-08-09-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On selected platforms, x4 DDR devices can be supported. Using x4 devices may lower the performance, but generally they are available for higher density. Tested on MT36JSF2G72PZ-1G9E1 RDIMM. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/mpc8xxx: Set inactive csn_bnds to 0xffffffffYork Sun2013-08-09-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When chip select interleaving is enabled, cs0_bnds is used for address binding. Other csn_bnds are not used. When two controllers interleaving is enabled, cs0_bnds of both controllers are used, other csn_bnds are not. However, the unused csn_bnds may be used internally for calculating addresses for calibration. Setting those registers to 0 may confuse controllers in some cases. Instead, setting them to 0xffffffff together with normal LAWs will guarantee the address is not mapped to DDR. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/corenet: Move RCW print to cpu.cYork Sun2013-08-09-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RCW print is common for all corenet platforms. Not necessary to ducplicate in each board file. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | mpc85xx: Base emulator supportYork Sun2013-08-09-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prepare for emulator support for mpc85xx parts. Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers. These two registers improve stability but not supported by emulator. Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/corenet: Move CONFIG_FSL_CORENET out of board header fileYork Sun2013-08-09-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board specific feature and belongs to SoC header. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/t4: Correct LIODN assignment for SRIOLiu Gang2013-08-09-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For T4 platform, the SRIO LIODN registers are in SRIO address space and not in GUTs. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
| * | | | powerpc/b4860: Correct LIODN assignment for SRIOLiu Gang2013-08-09-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For B4, the SRIO LIODN registers are in SRIO address space and not in GUTs. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
| * | | | powerpc/srio: Update the SRIO LIODN registers and ID table macroLiu Gang2013-08-09-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some PowerPC platforms, LIODN registers for SRIO ports are in SRIO register address space. So the ccsr_rio structure should be updated for those LIODN registers. In addition, add a new macro "SET_SRIO_LIODN_BASE" to create the SRIO LIODN ID table based on the SRIO LIODN register address. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | | | | Merge branch 'master' of git://www.denx.de/git/u-boot-mipsTom Rini2013-08-13-150/+160
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| * | | | | MIPS: bootm: drop obsolete Qemu specific bootm implementationDaniel Schwierzeck2013-08-13-66/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Qemu specific bootm implementation was intended for a special Qemu target in Linux kernel. But this target has been dropped in v2.6.25-rc1 by commit 302922e5f6901eb6f29c58539631f71b3d9746b8 Author: Ralf Baechle <ralf@linux-mips.org> Date: Tue Jan 29 10:15:02 2008 +0000 [MIPS] Qemu: Remove platform. The Qemu platform was originally implemented to have an easily supportable platform until Qemu reaches a state where it emulates a real world system. Since the latest release Qemu is capable of emulating the MIPSsim and Malta platforms, so this goal has been reached. The Qemu plaform is also rather underfeatured so less useful than a Malta emulation. Thus the special bootm implementation is obsolete by now and can be dropped. The Qemu support in U-Boot is going to be replaced by MIPS Malta board support. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | | MIPS: bootm: add YAMON style Linux preparation/jump code for Qemu MaltaDaniel Schwierzeck2013-08-13-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | | MIPS: bootm: add support for generic relocation of init ramdisksDaniel Schwierzeck2013-08-13-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All linux kernels after v2.6 require a page-aligned location of an external init ramdisk. Enable CONFIG_SYS_BOOT_RAMDISK_HIGH to support this with the generic U-Boot relocation code. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | | MIPS: bootm: refactor initialisation of kernel environmentDaniel Schwierzeck2013-08-13-33/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move initialisation of Linux environment to separate functions. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | | MIPS: bootm: refactor initialisation of kernel cmdlineDaniel Schwierzeck2013-08-13-47/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move initialisation of Linux command line to separate functions. Also add support for bootm subcommand 'cmdline'. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | | MIPS: bootm: add support for LMBDaniel Schwierzeck2013-08-13-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is required for init ramdisk relocation and device tree support. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | | MIPS: bootm: optimize kernel entry callDaniel Schwierzeck2013-08-13-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix signature of kernel entry function. Mark the kernel entry with __noreturn for better code optimisation. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | | | MIPS: bootm: fix checkpatch.pl warningsDaniel Schwierzeck2013-08-13-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | | | | Merge branch 'master' of git://www.denx.de/git/u-boot-videoTom Rini2013-08-12-115/+4
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| * | | | | exynos: video: change mipi dsi write function parameters correctlyDonghwa Lee2013-08-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch have changed mipi dsi write functions' parameters correctly so that type cast operations were removed. And mipi dsi payload is composed with array of panel commands to improve readability. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
| * | | | | video: Encapsulate font in video_font_data.hMarek Vasut2013-08-12-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves all the font configuration values into video_font_data.h so they are all in the right place with the font. The video_font.h now only includes video_font_data.h and will allow us to select and include different font once more fonts are added. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Anatolij Gustschin <agust@denx.de> [agust: fixed build warning for mcc200] Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * | | | | arm, am33xx: add clk_get prototypeHeiko Schocher2013-08-10-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the clk_get() function is needed for the da8xx-fb video driver, which is used on the am3xx based siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * | | | | video, da8xx: move da8xx-fb.h to drivers/videoHeiko Schocher2013-08-10-113/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the da8xx-fb driver works also on am335x boards. So move the da8xx-fb.h file from arch/arm/include/asm/arch-davinci to drivers/video, so this driver can used from am335x based boards. Also add WVGA panel_type. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Tom Rini <trini@ti.com>
| * | | | | dma: apbh: Add special circular mode for LCDMarek Vasut2013-08-09-0/+2
| | |_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add special function that executes a specially crafted circular DMA descriptor. The function doesn't wait for the descriptor to finish the transfer, since the descritor never finishes. This is useful when operating a SmartLCD through the LCDIF interface, as the LCDIF does not give us any means to have continuous refresh of the SmartLCD. Instead, the RUN bit in the LCDIF CTRL register must be triggered manually. This can be worked around by starting an DMA transfer which continuously sets the RUN bit. This function allows starting exactly such transfer. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* | | | | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2013-08-12-0/+7
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| * | | | microblaze: Call spi_init functionMichal Simek2013-08-08-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialization spi. Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Stephan Linz <linz@li-pro.net> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
generated by cgit v1.1 at 2024-11-01 07:24:14 +0000