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| * ARM: OMAP5: Add functions to enable and disable EDMA3 clocksVignesh R2015-08-17-0/+52
| | | | | | | | | | | | | | | | | | Adds functions to enable and disable edma3 clocks which can be invoked by drivers using edma3 to control the clocks. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * ARM: OMAP5: Add support for disabling clocks in ubootKishon Vijay Abraham I2015-08-17-0/+57
| | | | | | | | | | | | | | | | | | Add do_disable_clocks() to disable clock domains and module clocks. These clocks are enabled using do_enable_clocks(). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * ARM: AM43xx: Add support for disabling clocks in ubootKishon Vijay Abraham I2015-08-17-0/+53
| | | | | | | | | | | | | | | | | | Add do_disable_clocks() to disable clock domains and module clocks. These clocks are enabled using do_enable_clocks(). Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2015-08-18-7/+5
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| * | ARM: exynos: fix regression for Origen4210Thomas Abraham2015-08-17-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The do_lowlevel_init() function includes certian CA15 specific L2 cache configuration which is only applicable on Exynos5420 and members of its family. Fix the regression on Origen4210 by skipping the Exynos5420 specific portions of the code. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | ARM: exynos: move SoC sources to mach-exynosThomas Abraham2015-08-17-3/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Move arch/arm/cpu/armv7/exynos/* to arch/arm/mach-exynos/* to allow reuse of existing code for ARMv8 based Exynos platforms. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | pci: mvebu: Add PCIe driverAnton Schubert2015-08-17-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a PCI driver for the controllers found on Marvell MVEBU SoCs. Besides the driver, this patch also removes the statically defined PCI MBUS windows. As they are not needed anymore, since this PCIe driver now creates the windows dynamically. Tested on Armada XP db-mv784mp-gp eval board using an Intel E1000 PCIe card in all 3 PCIe slots. And on the Armada 38x db-88f6820-gp eval board using this Intel E1000 PCIe card in the PCIe 0 slot. This port was done in cooperation with Anton Schubert. Signed-off-by: Anton Schubert <anton.schubert@gmx.de> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <eibach@gdsys.de>
* | arm: mvebu: Add complete SDRAM ECC scrubbingStefan Roese2015-08-17-6/+139
| | | | | | | | | | | | | | | | | | | | | | | | This patch introduces the SDRAM scrubbing for ECC enabled board to fill/initialize the ECC bytes. This is done via the XOR engine to speed up the process. The scrubbing is a 2-stage process: 1) SPL scrubs the area 0 - 0x100.0000 (16MiB) for the main U-Boot 2) U-Boot scrubs the remaining SDRAM area(s) Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | arm: mvebu: dram.c: Rework dram_init() and dram_init_banksize()Stefan Roese2015-08-17-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | Rework these functions so that dram_init_banksize() does not call dram_init() again. It only needs to set the banksize values in the bdinfo struct. Make sure to also clip the size of the last bank if it exceeds the maximum allowed value of 3 GiB (0xc000.0000). Otherwise other address windows (e.g. PCIe) will overlap with this memory window. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | arm: mvebu: Display ECC enabled / disabled upon bootupStefan Roese2015-08-17-0/+19
| | | | | | | | | | | | | | | | | | This patch adds "(ECC enabled)" or "(ECC disabled)" to the DRAM bootup text. Making it easier for board with SPD DIMM's to see, if ECC is enabled or not. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | arm: mvebu: Enable USB EHCI support on Armada XPStefan Roese2015-08-17-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the USB EHCI support for the Marvell Armada XP (AXP) SoCs. In compatism to the Armada 38x (A38x), the AXP needs to configure the USB PLL and the USB PHY's specifically in U-Boot. The A38x has done this already in the bin_hdr (SPL U-Boot). Without this, accessing the controller registers in U-Boot or Linux will hang the CPU. Additionally, the AXP uses a different USB EHCI base address. This patch also takes care of this by runtime SoC detection in the Marvell EHCI driver. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Anton Schubert <anton.schubert@gmx.de> Cc: Marek Vasut <marex@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | arm: mvebu: Enable NAND controller on MVEBU SoC'sStefan Roese2015-08-17-2/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the NAND controller on the Armada XP/38x and provides a new function that returns the NAND controller input clock. This function will be used by the MVEBU NAND driver. As part of this patch, the multiple BIT macro definitions are moved to a common place in soc.h. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peter Morrow <peter@senient.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | arm: mvebu: Disable MBUS error propagationStefan Roese2015-08-17-0/+6
| | | | | | | | | | | | | | | | | | Accessing MBUS windows not backed-up by e.g. PCIe devices will hang the SoC. Disable MBUS error propagation back to CPU allows to read 0xffffffff instead of hanging the SoC. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | arm: mvebu: Flush caches and disable MMU only on A38xStefan Roese2015-08-17-7/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only with disabled MMU its possible to switch the base register address on Armada 38x. Without this the SDRAM located at >= 0x4000.0000 is also not accessible, as its still locked to cache. So to fully release / unlock this area from cache, we need to first flush all caches, then disable the MMU and disable the L2 cache. On Armada XP this does not seem to be needed. Even worse, with this code added, I sometimes see strange input charactes loss from the console. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | arm: mvebu: Setup the MBUS bridge registersStefan Roese2015-08-17-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With this patch, the MBUS bridge registers (base and size) are configured upon each call to mbus_dt_setup_win(). This is needed, since the board code can also call this function in later boot stages. As done in the maxbcm board. This is needed to fix a problem with the secondary CPU's not booting in Linux on AXP. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peter Morrow <peter@senient.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | arm: mvebu: Change MBUS base addresses and sizesStefan Roese2015-08-17-10/+16
| | | | | | | | | | | | | | | | | | This patch changes the MBUS base addresses and sizes to use more generic names and also adds defines for the sizes. It also moves the base address to higher addresses. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | arm: mvebu/armada100: dram.c: Remove CONFIG_SYS_BOARD_DRAM_INITStefan Roese2015-08-17-4/+0
| | | | | | | | | | | | | | | | CONFIG_SYS_BOARD_DRAM_INIT is not defined anywhere. So lets get rid of all references here. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | arm: lpc32xx: gpio macro for pin mappingSylvain Lemieux2015-08-17-0/+40
| | | | | | | | | | | | Add LPC32xx GPIO interface macro for pin mapping. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* | lpc32xx: cpu: add support for soft resetSylvain Lemieux2015-08-17-6/+17
| | | | | | | | | | | | | | | | Add support for optional soft reset (i.e. "RESOUT_N" not asserted during reset). To be compatible with the original U-Boot code, when the "addr" parameter is 0, a hard is performed; for any other values, a soft reset is done. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* | arm: lpc32xx: mux: add missing registersSylvain Lemieux2015-08-17-1/+18
|/ | | | | | | Add missing registers in struct definition. Update GPIO MUX base register to match GPIO base (refer to "LPC32x0 User manual" Rev. 3 - 22 July 2011). Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-08-14-189/+386
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| * x86: minnowmax: Define and enable interrupt setupSimon Glass2015-08-14-3/+66
| | | | | | | | | | | | | | | | Set up interrupts correctly so that Linux can use all devices. Use savedefconfig to regenerate the defconfig file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Return -1 when reading a PCI config register failsSimon Glass2015-08-14-3/+6
| | | | | | | | | | | | | | | | This can fail for internal reasons, so return a sensible value rather than a random one. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Drop FSP error defines and use EFI insteadSimon Glass2015-08-14-12/+1
| | | | | | | | | | | | | | | | Now that we have an efi.h header we can use that for FSP error defines. Drop the FSP ones. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Set APs' req_seq to the reg number from device treeBin Meng2015-08-14-0/+7
| | | | | | | | | | | | | | | | | | Multiple APs are brought up simultaneously and they may get the same seq num in the uclass_resolve_seq() during device_probe(). To avoid this, set req_seq to the reg number in the device tree in advance. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Show the un-relocated IP address in exceptionsSimon Glass2015-08-14-0/+2
| | | | | | | | | | | | | | | | | | | | When trying to figure out where an exception has occured, the relocated address is not a lot of help. Its value depends on various factors. Show the un-relocated IP as well. This can be looked up in System.map directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Switch to using generic global_data setupSimon Glass2015-08-14-83/+16
| | | | | | | | | | | | | | | | | | | | | | There is quite a bit of assembler code that can be removed if we use the generic global_data setup. Less arch-specific code makes it easier to add new features and maintain the start-up code. Drop the unneeded code and adjust the hooks in board_f.c to cope. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Move the GDT into global_dataSimon Glass2015-08-14-5/+8
| | | | | | | | | | | | | | | | | | Rather than keeping track of the Global Descriptor Table in its own memory we may as well put it in global_data with everything else. As a first step, stop using the separately allocated GDT. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Remove init_gd() functionSimon Glass2015-08-14-1/+0
| | | | | | | | | | | | | | This is declared but no-longer exists. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: baytrail: Support running as an EFI payloadSimon Glass2015-08-14-0/+2
| | | | | | | | | | | | | | | | We should not fiddle with interrupts or the FSP when running as an EFI payload. Detect this and skip this code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: baytrail: Tidy up interrupt and FSP initSimon Glass2015-08-14-1/+8
| | | | | | | | | | | | | | | | We should signal to the FSP that PCI enumeration is complete. Perform this task in a suitable place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Allow pirq_init() to return an errorSimon Glass2015-08-14-19/+18
| | | | | | | | | | | | | | | | This function can fail. In this case we should return the error rather than swallowing it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Split out fsp_init_phase_pci() code into a new functionSimon Glass2015-08-14-3/+15
| | | | | | | | | | | | | | | | | | | | | | This code may be useful for boards that use driver model for PCI. Note: It would be better to have driver model automatically call this function somehow. However for now it is probably safer to have it under board control. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Tidy up the PIRQ routing code a littleSimon Glass2015-08-14-28/+13
| | | | | | | | | | | | | | | | | | This code could use a little tightening up. There is some repetition and an odd use of fdtdec_get_int_array(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: fsp: Do not assert VPD_IMAGE_REV when DEBUGBin Meng2015-08-14-4/+1
| | | | | | | | | | | | | | | | | | | | When using different release version of Intel FSP, the VPD_IMAGE_REV is different (ie: BayTrail Gold 3 is 0x0303 while Gold 4 is 0x0304). Remove the asserting of this so that U-Boot does not hang in a debug build. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: baytrail: Configure FSP UPD from device treeAndrew Bradford2015-08-14-30/+226
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow for configuration of FSP UPD from the device tree which will override any settings which the FSP was built with itself. Modify the MinnowMax and BayleyBay boards to transfer sensible UPD settings from the Intel FSPv4 Gold release to the respective dts files, with the condition that the memory-down parameters for MinnowMax are also used. Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Removed fsp,mrc-debug-msg and fsp,enable-xhci for minnowmax, bayleybay Fixed lines >80col Signed-off-by: Simon Glass <sjg@chromium.org>
* | sun6i: clock: Add support for the mipi pllHans de Goede2015-08-14-0/+70
| | | | | | | | | | | | | | | | Add support for the mipi pll, this is necessary for getting higher dotclocks with lcd panels. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: clock: Add clock_get_pll3() helper functionHans de Goede2015-08-14-0/+29
| | | | | | | | | | | | | | Add a helper function to get the pll3 clock rate. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Fix gmac not working on the Colombus boardHans de Goede2015-08-14-0/+12
| | | | | | | | | | | | | | | | | | The phy is using a RGMII interface, which we need to specify in our board-config, and the dts needs a gmac section (the dts changes have also been submitted to the kernel). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Add support for the Auxtek-T003 HDMI stickHans de Goede2015-08-14-0/+160
| | | | | | | | | | | | | | | | The Auxtek-T003 HDMI stick is an A10s based HDMI stick with USB wifi, and composite video out support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: dts: Sync with kernelHans de Goede2015-08-14-39/+910
| | | | | | | | | | | | | | | | Sync the sunxi dts files with the changes queued up for kernel-4.3 in mripard's sunxi/dt-for-4.3 branch. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: display: Fix composite video out on sun5iHans de Goede2015-08-14-1/+16
|/ | | | | | | | The tv-encoder on sun5i is slightly different compared to the one on sun4i/sun7i. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: tegra: represent RAM in 1 or 2 banksStephen Warren2015-08-13-14/+106
| | | | | | | | | | | | | | | | | | | | | Represent all available RAM in either one or two banks. The first bank describes any RAM below 4GB. The second bank describes any RAM above 4GB. This split is driven by the following requirements: - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg property for memory below and above the 4GB boundary. The layout of that DT property is directly driven by the entries in the U-Boot bank array. - On systems with RAM beyond a physical address of 4GB, the potential existence of a carve-out at the end of RAM below 4GB can only be represented using multiple banks, since usable RAM is not contiguous. While making this change, add a lot more comments re: how and why RAM is represented in banks, and implement a few more "semantic" functions that define (and perhaps later detect at run-time) the size of any carve-out. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: query_sdram_size() cleanupStephen Warren2015-08-13-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The return value of query_sdram_size() is assigned directly to gd->ram_size in dram_init(). Adjust the return type to match the field it's assigned to. This has the beneficial effect that on 64-bit systems, the return value can correctly represent large RAM sizes over 4GB. For similar reasons, change the type of variable size_bytes in the same way. query_sdram_size() would previously clip the detected RAM size to at most just under 4GB in all cases, since on 32-bit systems, larger values could not be represented. Disable this feature on 64-bit systems since the representation restriction does not exist. On 64-bit systems, never call get_ram_size() to validate the detected/ calculated RAM size. On any system with a secure OS/... carve-out, RAM may not have a single contiguous usable area, and this can confuse get_ram_size(). Ideally, we'd make this call conditional upon some other flag that indicates specifically that a carve-out is actually in use. At present, building for a 64-bit system is the best indication we have of this fact. In fact, the call to get_ram_size() is not useful by the time U-Boot runs on any system, since U-Boot (and potentially much other early boot software) always runs from RAM on Tegra, so any mistakes in memory controller register programming will already have manifested themselves and prevented U-Boot from running to this point. In the future, we may simply delete the call to get_ram_size() in all cases. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Correct logic for reading pll_misc in clock_start_pll()Simon Glass2015-08-13-13/+31
| | | | | | | | | | | | The logic for simple PLLs on T124 was broken by this commit: 722e000c Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. Correct it by reading from the same pll_misc register that it writes to and adding an entry for the DP PLL in the pllinfo table. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: tegra: Make pinmux.h standalone includibleThierry Reding2015-08-13-0/+2
| | | | | | | | | | | This header file uses type definitions (u8, u32) from linux/types.h but doesn't include it. If includes aren't carefully ordered this can cause build failures. Cc: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* apalis/colibri_t30: fix usb dm regressionMarcel Ziswiler2015-08-13-2/+2
| | | | | | | | | | | | | | | | Unfortunately currently both Apalis T30 as well as Colibri T30 crash upon starting USB host support. This is due to the following patch not having taken into account that our T30 device trees were defaulting to peripheral only mode instead of otg: commit ddb9a502d18008e845d5a8fa03ec48630fa77fb7 dm: usb: tegra: Move most of init/uninit into a function This patch fixes this by defaulting to otg now. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* apalis/colibri_t20/30: clean-upMarcel Ziswiler2015-08-13-2/+4
| | | | | | | | | | | | | | | Various clean-ups either in comments, order or spacing without any functional impact: - Add some comments in the device trees resp. reorder some parameters for consistency across all our modules. - Sort some include files alphabetically (while leaving common.h on top of course). - Streamline some comments in the configuration files and fix the spacing from using spaces to tabs. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* colibri_t20: add i2c supportMarcel Ziswiler2015-08-13-0/+28
| | | | | | | | | | Add I2C support in order to subsequently allow disabling the PMIC sleep mode on low supply voltage. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* colibri_t20: add lcd display supportMarcel Ziswiler2015-08-13-0/+29
| | | | | | | | | | Add LCD display support defaulting to VESA VGA resolution. Different resolutions configurable via device tree. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-11-15 08:52:48 +0000