summaryrefslogtreecommitdiff
path: root/arch
Commit message (Collapse)AuthorAgeLines
* x86: ivybridge: Provide a dummy SDRAM init for 64-bitSimon Glass2017-02-06-0/+31
| | | | | | | | | | We don't support SDRAM init in 64-bit mode since it is essentially impossible to get into that mode before SDRAM set up. Provide dummy functions for now. At some point we will need to pass the SDRAM parameters through from SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Skip SATA init in SPLSimon Glass2017-02-06-0/+2
| | | | | | | This doesn't work at present. Disable it for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Fix up type sizes for 64-bitSimon Glass2017-02-06-0/+10
| | | | | | | Adjust types as needed to support 64-bit compilation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Drop flag_is_changable() on x86_64Simon Glass2017-02-06-0/+3
| | | | | | | | This doesn't build at present and is not used in a 64-bit build. Disable it for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Fix up byteorder.h for x86_64Simon Glass2017-02-06-8/+9
| | | | | | | Remove the very old x86 code and add support for 64-bit. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a link script for SPLSimon Glass2017-02-06-0/+74
| | | | | | | | If SPL is used it is always build in 32-bit mode. Add a link script to handle the correct placement of the sections. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add a link script for 64-bit x86Simon Glass2017-02-06-0/+82
| | | | | | | | This needs a different image format from 32-bit x86, so add a new link script. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Fix up CONFIG_X86_64 checkSimon Glass2017-02-06-1/+1
| | | | | | | | When SPL and U-Boot proper have different settings for this flag, we need to use the correct one. Fix this up in the interrupt code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Support global_data on x86_64Simon Glass2017-02-06-1/+33
| | | | | | | | At present this is just an ordinary variable. We may consider making it a fixed register in the future. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add cpu code for x86_64Simon Glass2017-02-06-1/+72
| | | | | | | | There is not much needed at present, but set up a separate directory to put this code as it grows. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Move the i386 code into its own directorySimon Glass2017-02-06-509/+549
| | | | | | | | Much of the cpu and interrupt code cannot be compiled on 64-bit x86. Move it into its own directory and build it only in 32-bit mode. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add an SPL implementationSimon Glass2017-02-06-0/+163
| | | | | | | | SPL needs to set up the machine ready for loading 64-bit U-Boot and jumping to it. Call the existing init routines in order to accomplish this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Tidy up use of size_t in relocationSimon Glass2017-02-06-2/+2
| | | | | | | Addresses should not be cast to size_t. Use uintptr_t instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add support for 64-bit relocationSimon Glass2017-02-06-0/+45
| | | | | | | | | Add a 64-bit relocation function. SPL loads U-Boot into RAM at a fixed address and runs it. U-Boot then relocates itself to the top of RAM using this relocation function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Refactor relocation to prepare for 64-bitSimon Glass2017-02-06-24/+31
| | | | | | | | Move the core relocation code into a separate function so that the checking code can be used for 64-bit relocation also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add 64-bit start-up codeSimon Glass2017-02-06-0/+37
| | | | | | | | Add code to start up U-Boot in 64-bit mode. It is fairly simple since we are running from RAM and SPL has done the low-level init. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Allow 32-bit init to move to SPLSimon Glass2017-02-06-2/+2
| | | | | | | | Update the Makefile so that some 32-bit init can be built into SPL rather than U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Use X86_32BIT_INIT instead of X86_RESET_VECTORSimon Glass2017-02-06-5/+7
| | | | | | | | Use this new option to control the location of 32-bit init. This will allow us to place this in SPL if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Use X86_16BIT_INIT instead of X86_RESET_VECTORSimon Glass2017-02-06-6/+4
| | | | | | | | Use this new option to control the location of 16-bit init. This will allow us to place this in SPL if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Kconfig: Add location options for 16/32-bit initSimon Glass2017-02-06-0/+40
| | | | | | | | | | | | | | | | | | At present all 16/32-bit init is controlled by CONFIG_X86_RESET_VECTOR. If this is enabled, then U-Boot is the 'first' boot loader and handles execution from the reset vector through to U-Boot's command prompt. If it is not enabled then U-Boot starts at the 32-bit entry and skips most of its init, assuming that the previous boot loader has done this already. With the move to suport 64-bit operation, we have more cases to consider. The 16-bit and 32-bit init may be in SPL rather than in U-Boot proper. Add Kconfig options which control the location of the 16-bit and the 32-bit init. These are not intended to be user-setting except for experimentation. Their values should be determined by whether 64-bit U-Boot is used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Add Kconfig options to build 64-bit U-BootSimon Glass2017-02-06-0/+46
| | | | | | | | Add a new CONFIG_X86_64 option which will eventually cause U-Boot to be built as a 64-bit application, with SPL doing the 16/32-bit init. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: lib: Fix types and casts for 64-bit compilationSimon Glass2017-02-06-5/+5
| | | | | | | Fix various compiler warnings in the x86 library code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: fsp: Fix cast for 64-bit compilationSimon Glass2017-02-06-2/+2
| | | | | | | Fix a cast in get_next_hob() that causes warnings on 64-bit machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: dts: Mark serial as needed before relocationSimon Glass2017-02-06-0/+1
| | | | | | | | We almost always need the serial port before relocation, so mark it as such. This will ensure that it appears in the device tree for SPL, if used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Fix types for 64-bit compilationSimon Glass2017-02-06-2/+2
| | | | | | | Fix a few types that causes warnings on 64-bit machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Add more debugging for failuresSimon Glass2017-02-06-10/+31
| | | | | | | | Add various debug() messages in places where errors occur. This aids with debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ivybridge: Declare global data where it is usedSimon Glass2017-02-06-0/+8
| | | | | | | | Some files are missing this declaration. Add it to avoid build errors when we actually need the declaration. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Update mpspec to build on 64-bit machinesSimon Glass2017-02-06-10/+10
| | | | | | | | | At present this uses u32 to store an address. We should use unsigned long and avoid special types in function return values and parameters unless necessary. This makes the code more portable. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Use unsigned long for address in table generationSimon Glass2017-02-06-21/+14
| | | | | | | | We should use unsigned long rather than u32 for addresses. Update this so that the table-generation code builds correctly on 64-bit machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Synchronize list of x86 subarchitectures (update bootparam.h)Andy Shevchenko2017-02-06-1/+2
| | | | | | | | Basically rename X86_SUBARCH_MRST to X86_SUBARCH_INTEL_MID to be more specific. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2017-02-03-72/+106
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: configs/ls1046aqds_defconfig configs/ls1046aqds_nand_defconfig configs/ls1046aqds_qspi_defconfig configs/ls1046aqds_sdcard_ifc_defconfig configs/ls1046aqds_sdcard_qspi_defconfig configs/ls1046ardb_emmc_defconfig configs/ls1046ardb_qspi_defconfig configs/ls1046ardb_sdcard_defconfig
| * arch: powerpc: update the eLBC IP input clockPrabhakar Kushwaha2017-02-03-40/+21
| | | | | | | | | | | | | | | | | | | | | | | | eLBC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock ratio register (LCRR) used in current implementation governs eLBC IP output cloc. Update sys_info->freq_localbus to represent eLBC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arch: powerpc: Move CONFIG_FSL_ELBC to KconfigPrabhakar Kushwaha2017-02-03-0/+20
| | | | | | | | | | | | | | Enable ELBC from Kconfig. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arch: arm: update the IFC IP input clockPrabhakar Kushwaha2017-02-03-24/+5
| | | | | | | | | | | | | | | | | | | | | | | | IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arch: powerpc: update the IFC IP input clockPrabhakar Kushwaha2017-02-03-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | IFC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock control register (CCR) used in current implementation governs IFC IP output clock. Update sys_info->freq_localbus to represent IFC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * arch: powerpc: Move CONFIG_FSL_IFC to KconfigPrabhakar Kushwaha2017-02-03-0/+17
| | | | | | | | | | | | | | Enable IFC from Kconfig. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * board: freescale: ls1012a: Enable secure DDR on LS1012A platformsPrabhakar Kushwaha2017-02-03-0/+3
| | | | | | | | | | | | | | | | | | | | | | PPA binary needs to be relocated on secure DDR, hence marking out a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag is set Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * armv8: ls1046a: Enable workaround for erratum A-008336York Sun2017-01-31-0/+1
| | | | | | | | | | | | | | Erratum A-008336 applies to LS1046A per latest SoC document. Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
| * armv8: ls1046a: added usb nodes in dtsTang Yuantian2017-01-27-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | The LS1046A processor has three integrated USB 3.0 controllers (USB1, USB2, and USB3) that allow direct connection to the USB ports with appropriate protection circuitry and power supplies. USB1 and USB2 ports are powered by a NX5P2190UK device, which supplies 5v power at up to 1.2 A. The power enable and power-fault-detect pins are connected to the LS1046A processor via CPLD for individual port management. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge git://git.denx.de/u-boot-mpc85xxTom Rini2017-02-01-17/+38
|\ \
| * | powerpc: mpc5200: Correct return value of memcpy functionMark Marshall2017-02-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The memcpy() function returns a pointer to trg. Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at> Reviewed-by: Thomas Graziadei <thomas.graziadei@omicronenergy.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: York Sun <york.sun@nxp.com>
| * | powerpc: mpc85xx: Use symbolic names for cache control bitsMark Marshall2017-01-31-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | We should use the symbolic names for the cache control bits. Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at> Reviewed-by: Thomas Graziadei <thomas.graziadei@omicronenergy.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | powerpc: mpc83xx: Enable pre-relocation mallocmario.six@gdsys.cc2017-01-31-7/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | To enable DM on MPC83xx, we need pre-relocation malloc, which is implemented in this patch. Signed-off-by: Mario Six <mario.six@gdsys.cc> [York S: Fixed compiling warning for unused variable 'i'] Reviewed-by: York Sun <york.sun@nxp.com>
| * | powerpc: mpc83xx: Minimize r1 modificationmario.six@gdsys.cc2017-01-31-5/+8
| |/ | | | | | | | | | | | | | | | | | | | | | | | | The r1 register is modified several times during the cache-ram setup of the MPC83xx SoCs. Since this SP modification confuses debuggers, we use a general purpose register to compute the new stack pointer value, and only set the SP once after all computations are done. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Joakim Tjernlund <Joakim.Tjernlund@infinera.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2017-02-01-30/+3075
|\ \
| * | BOARD: MCCMON6: Provide support for iMX6q based mccmon6 boardLukasz Majewski2017-01-30-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | This patch provides u-boot support for Liebherr (LWN) mccmon6 board. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | arm: dts: imx53-cx9020: fix packetloss on fec_mxcPatrick Bruenn2017-01-30-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinmuxing for i.MX53 FEC ethernet copied from <kernel>/arch/arm/boot/dts/imx53-qsb-common.dtsi (at least until v4.9) was bad. It is different from the manual pinmuxing in <u-boot>/board/freescale/mx53loco/mx53loco.c which was used in cx9020 implementation previously before mainlining into u-boot. It seems the bug in imx53-qsb kernel device tree is hidden for so long, because it was never used, by the kernel driver. Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
| * | imx: dts: mx6sxsabreauto: enable i2c2/3Peng Fan2017-01-27-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | Enable i2c2/3, add pinctrl settings. Add max7310 for i2c3. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | imx: mx6sx: add dts for mx6sxsabreauto boardPeng Fan2017-01-27-0/+3003
| | | | | | | | | | | | | | | | | | | | | | | | Add dts for mx6sxsabreauto board. dts related files imported fro Linux (commit e5517c2a5a4). Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
| * | ARM: imx6ul: Move liteSOM source to SoC directoryMarcin Niestroj2017-01-27-18/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moving arch/arm/mach-litesom/ to arch/arm/cpu/armv7/mx6/ was requested in [1] during discussion of chiliSOM support patches. [1] http://lists.denx.de/pipermail/u-boot/2017-January/279137.html Suggested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
generated by cgit v1.1 at 2024-11-09 15:29:17 +0000