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* Merge git://git.denx.de/u-boot-mpc85xxTom Rini2016-12-04-90/+189
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| * powerpc: mpc86xx: Convert CONFIG_SYS_FSL_NUM_LAWS to Kconfig optionYork Sun2016-12-04-12/+6
| | | | | | | | | | | | Use Kconfig instead of defining this macro in header file. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: mpc85xx: Convert CONFIG_SYS_FSL_NUM_LAWS to Kconfig optionYork Sun2016-12-02-32/+48
| | | | | | | | | | | | Move the macro to Kconfig SYS_FSL_NUM_LAWS. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: mpc86xx: Move CONFIG_FSL_LAW to KconfigYork Sun2016-12-02-0/+7
| | | | | | | | | | | | Clean up existing definitions and drop from white list. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: mpc85xx: Move CONFIG_FSL_LAW to KconfigYork Sun2016-12-02-0/+42
| | | | | | | | | | | | | | Some header files have this macro defined conditionally and redefined unconditionally. Remove all existing definitions. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: mpc85xx: Move SECURE_BOOT to KconfigYork Sun2016-12-02-0/+6
| | | | | | | | | | | | Move from CONFIG_SYS_EXTRA_OPTIONS to Kconfig option. Signed-off-by: York Sun <york.sun@nxp.com>
| * armv8: fsl-layerscape: Move SECURE_BOOT to KconfigYork Sun2016-12-02-0/+5
| | | | | | | | | | | | Move from CONFIG_SYS_EXTRA_OPTIONS to Kconfig option. Signed-off-by: York Sun <york.sun@nxp.com>
| * armv7: ls1021a: Move SECURE_BOOT option to KconfigYork Sun2016-12-02-0/+6
| | | | | | | | | | | | Move from CONFIG_SYS_EXTRA_OPTIONS to Kconfig option. Signed-off-by: York Sun <york.sun@nxp.com>
| * script: remove CONFIG_SYS_CCSRBAR_DEFAULT from white listYork Sun2016-12-02-3/+2
| | | | | | | | | | | | | | Now all mpc85xx and mpc86xx have converted to use SYS_CCSRBAR_DEFAULT in Kconfig. Drop this macro for LSCH2 and remove from white list. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: mpc86xx: Convert CONFIG_SYS_CCSRBAR_DEFAULT to Kconfig optionYork Sun2016-12-02-0/+9
| | | | | | | | | | | | Move default value definitions to Kconfig SYS_CCSRBAR_DEFAULT. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: mpc85xx: Convert CONFIG_SYS_CCSRBAR_DEFAULT to Kconfig optionYork Sun2016-12-02-41/+50
| | | | | | | | | | | | Move default value definitions to to Kconfig SYS_CCSRBAR_DEFAULT. Signed-off-by: York Sun <york.sun@nxp.com>
| * powerpc: cyrus: Separate P5020/P5040 config optionsYork Sun2016-12-02-2/+8
| | | | | | | | | | | | | | Instead of using EXTRA options in defconfig, use two targets in Kconfig to select correct SoC. Signed-off-by: York Sun <york.sun@nxp.com>
* | arm: Remove VCMA9 boardSimon Glass2016-12-04-5/+0
| | | | | | | | | | | | | | | | | | This board has not been converted to DM_SERIAL by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: David Müller <d.mueller@elsoft.ch> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | arm: Remove smdk2410 boardSimon Glass2016-12-04-5/+0
| | | | | | | | | | | | | | | | This board has not been converted to DM_SERIAL by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: David Müller <d.mueller@elsoft.ch>
* | ARM: dts: AM571x-IDK Initial SupportSchuyler Patton2016-12-04-1/+83
| | | | | | | | | | | | | | | | | | Add initial DTS support for AM571-IDK evm. Signed-off-by: Schuyler Patton <spatton@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | board: ti: am572x: Add pinmux for X15/GPEVM SR2.0 using latest PMTNishanth Menon2016-12-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Update the board pinmux for AM572x-IDK board using latest PMT[1] and the board files named am572x_gp_evm_A3a_sr2p0 that were autogenerated on 19th October, 2016 by "Ahmad Rashed<a-rashed@ti.com>". [1] https://dev.ti.com/pinmux/app.html#/default/ Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: dts: am57xx: sync DT with latest LinuxLokesh Vutla2016-12-04-703/+703
| | | | | | | | | | | | | | Sync all am57xx based dts files with latest Linux Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: dts: dra71x-evm: Add DT supportLokesh Vutla2016-12-04-1/+231
| | | | | | | | | | | | | | Add DT support for dra71-evm and built it as part of FIT image. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: dts: dra7xx: sync DT with latest LinuxLokesh Vutla2016-12-04-640/+1617
| | | | | | | | | | | | | | Sync all dra7xx based dts files with latest Linux Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: OMAP4+: Add support for getting pbias info from boardLokesh Vutla2016-12-04-1/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | Palmas driver assumes it is always TPS659xx regulator on all DRA7xx based boards to enable mmc regulator. This is not true always like in case of DRA71x-evm. So get this information based on the board. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Delete omap4_vmmc_pbias_config from omap_hsmmc.c] Signed-off-by: Tom Rini <trini@konsulko.com>
* | board: ti: dra71x-evm: Add PMIC supportKeerthy2016-12-04-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the pmic_data for LP873x PMIC which is used to power up dra71x-evm. Note: As per the DM[1] DRA71x supports only OP_NOM. So, updating the efuse registers only to use OPP_NOM irrespective of any CONFIG_DRA7_<VOLT>_OPP_{NOM,od,high} is defined. [1] http://www.ti.com/product/DRA718/technicaldocuments Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7: Fixup DSPEVE, IVA and GPU clock frequencies based on OPPSuman Anna2016-12-04-0/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to update the device-tree blob to adjust the DSP and IVA DPLL clocks pertinent to the selected OPP choice, with the default being OPP_NOM. The voltage settings are done in u-boot, but the actual clock configuration itself is done in kernel because of the following reasons: 1. SoC definition constraints us to NOT to do dynamic voltage scaling ever after the initial avs0 setting in bootloader - so the voltage must be set in bootloader. 2. The voltage level must be set even if the IP blocks like GPU/DSP are unused. 3. The IVA, GPU and DSP DPLLs are not essential for u-boot functionality, and similar DPLL clock configuration code has been cleaned up in v2014.10 u-boot release. See commit, 02c41535b6a4 ("ARM: OMAP4/5: Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALL"). The non-essential DPLLs are configured within the kernel during the clock init step when parsing the device tree and creating the clock devices. This approach meets both the u-boot and kernel needs. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Subhajit Paul <subhajit_paul@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7: Redefine voltage and efuse macros per OPP using KconfigSuman Anna2016-12-04-13/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Redefine the macros used to define the voltage values and the efuse register offsets based on OPP for all the voltage domains. This is done using Kconfig macros that can be set in a defconfig or selected during a config step. This allows a voltage domain to be configured/set to a corresponding voltage value depending on the OPP selection choice. The Kconfig choices have been added for MPU, DSPEVE, IVA and GPU voltage domains, with the MPU domain restricted to OPP_NOM. The OPP_OD and OPP_HIGH options will be added when the support for configuring the MPU clock frequency is added. The clock configuration for other voltage domains is out of scope in u-boot code. The CORE voltage domain does not have separate voltage values and efuse register offset at different OPPs, while the MPU voltage domain only has different efuse register offsets for different OPPs, but uses the same voltage value. Any different choices of OPPs for voltage domains on common ganged-rails is automatically taken care to select the corresponding highest OPP voltage value. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: OMAP4+: Add support for dynamically selecting OPPsLokesh Vutla2016-12-04-64/+111
| | | | | | | | | | | | | | | | | | | | | | It can be expected that different paper spins of a SoC can have different definitions for OPP and can have their own constraints on the boot up OPP for each voltage rail. In order to have this flexibility, add support for dynamically selecting the OPP voltage based on the board to handle any such exceptions. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-dmTom Rini2016-12-03-18/+48
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| * | drivers: usb: musb: adopt musb backend driver to driver modelMugunthan V N2016-12-02-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently all backend driver ops uses hard coded physical address, so to adopt the driver to DM, add device pointer to ops call backs so that drivers can get physical addresses from the usb driver priv/plat data. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | am33xx: board: probe misc drivers to register musb devicesMugunthan V N2016-12-02-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | MUSB wrapper driver is bound as MISC device and underlying usb devices are bind to usb drivers based on dr_mode, so probing the MISC wrapper driver to register musb devices. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | am33xx: board: do not register usb devices when CONFIG_DM_USB is definedMugunthan V N2016-12-02-1/+4
| | | | | | | | | | | | | | | | | | | | | Do not register usb devices when CONFIG_DM_USB is define. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | libfdt: replace ARCH_FIXUP_FDT with ARCH_FIXUP_FDT_MEMORYMasahiro Yamada2016-12-02-6/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e2f88dfd2d96 ("libfdt: Introduce new ARCH_FIXUP_FDT option") allows us to skip memory setup of DTB, but a problem for ARM is that spin_table_update_dt() and psci_update_dt() are skipped as well if CONFIG_ARCH_FIXUP_FDT is disabled. This commit allows us to skip only fdt_fixup_memory_banks() instead of the whole of arch_fixup_fdt(). It will be useful when we want to use a memory node from a kernel DTB as is, but need some fixups for Spin-Table/PSCI. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for x86: Signed-off-by: Simon Glass <sjg@chromium.org>
* | | arm: omap5: Add OPTEE node to fdtAndrew F. Davis2016-12-03-1/+34
| | | | | | | | | | | | | | | | | | | | | | | | Add an OPTEE node to the FDT when TEE installation has completed successfully. This informs the kernel of the presence of OPTEE. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | arm: omap5: Add TEE loading supportHarinarayan Bhatta2016-12-03-0/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | secure_tee_install is used to install and initialize a secure TEE OS such as Linaro OP-TEE into the secure world. This function takes in the address where the signed TEE image is loaded as an argument. The signed TEE image consists of a header (struct tee_header), TEE code+data followed by the signature generated using image signing tool from TI security development package (SECDEV). Refer to README.ti-secure for more information. This function uses 2 new secure APIs. 1. PPA_SERV_HAL_TEE_LOAD_MASTER - Must be called on CPU Core 0. Protected memory for TEE must be reserved before calling this function. This API needs arguments filled into struct ppa_tee_load_info. The TEE image is authenticated and if there are no errors, the control passes to the TEE entry point. 2. PPA_SERV_HAL_TEE_LOAD_SLAVE - Called on other CPU cores only after a TEE_LOAD_MASTER call. Takes no arguments. Checks if TEE was successfully loaded (on core 0) and transfers control to the same TEE entry point. The code at TEE entry point is expected perform OS initialization steps and return back to non-secure world (U-Boot). Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | arm: omap5: Add function to make an SMC call on cpu1Harinarayan Bhatta2016-12-03-0/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On DRA7xx platform, CPU Core 1 is not used in u-boot. However, in some cases it is need to make secure API calls from Core 1. This patch adds an assembly function to make a secure (SMC) call from CPU Core #1. Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | davinci: omapl138_lcdk: configure ddr2Fabien Parent2016-12-03-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The SPL is unable to load u-boot because the DDR2 is not configured. Configure the DDR2. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | davinci: omapl138_lcdk: configure pll0Fabien Parent2016-12-03-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The SPL is not able to boot properly because the PLL0 is not configured. Configure it. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: davinci: Move CONFIG_SYS_DA850_DDR_INIT to KconfigFabien Parent2016-12-03-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Clean config headers by moving CONFIG_SYS_DA850_DDR_INIT away to a Kconfig file. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: davinci: Move CONFIG_SYS_DA850_PLL_INIT to KconfigFabien Parent2016-12-03-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Clean config headers by moving CONFIG_SYS_DA850_PLL_INIT away to a Kconfig file. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA7x/AM57xx: Get rid of CONFIG_AM57XXNishanth Menon2016-12-03-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_AM57XX is just an unnecessary macro that is redundant given So, remove the same instead of spreading through out the u-boot source code and getting in the way to maintain common code for DRA7x family. Acked-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: K2G: DDR3: Fix up priv ID for MPUNishanth Menon2016-12-03-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For ECC enabled DDR, we use EDMA to reset all memory values to 0. For K2E/L/H/K the priv ID of 8 was indicative of ARM, but that is not the case for K2G, where it is 1. Unfortunately, ddr3 code had hard coded the privID and had missed identification previously. Fix the same, else unforeseen behavior can be expected in our reset of DDR contents to 0 for ECC enablement. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | sh: generate position independent code for all platformsVladimir Zapolskiy2016-12-02-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Finally add fpic compilation option to produce relocatable code. Note that this requires to define CONFIG_NEEDS_MANUAL_RELOC for all board files, also relocation support still has some limitations (e.g. a developer should care not to overwrite the executing code or memset() with zeroes not yet relocated data on malloc init etc.), which may be fixed while switching to PIE. Due to short investigation the architecture code is not ready for PIE linking, this will require some manipulations with .dyn* sections. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* | | sh: share the correct version of start.S among all cpusVladimir Zapolskiy2016-12-02-135/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is easy to note that SH2/SH3/SH4 start.S code is practically the same with a minor difference for SH2 where a short data header is present. To avoid unwanted code duplication and to automatically convert SH2 and SH3 platforms to generic board support move fixed SH4 start.S into arch/sh/lib/start.S and share it among all platforms. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | sh4: fix start.S by calling board_init_f() after first code relocationVladimir Zapolskiy2016-12-02-12/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Like on ARM platform keep the first code relocation from a U-boot image storage to RAM at CONFIG_SYS_TEXT_BASE, then pass execution to a generic board_init_f() with empty GD flags. If CONFIG_SYS_TEXT_BASE is equal to a calculated by board_init_f() relocation address there will be no more code and data copy, however it's worth to mention that the first copy happens even if $pc on _start is the same as CONFIG_SYS_TEXT_BASE, on practice this works without a problem. Also note that _sh_start is renamed back to _start to correct gd->mon_len calculation by setup_mon_len(), the opposite rename was done in pre-generic board commit 2024b968ee9 ("sh: Fix build in start.S"). Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | sh: add shared relocate_code() function and call board_init_r()Vladimir Zapolskiy2016-12-02-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commits b61e90e6fd83 ("sh: Drop the arch-specific board init") and f41e6088eb1a ("sh: Fix build errors for generic board") left code and data relocation done in start.S, however further actual U-boot configuration is not started anymore. Practically SH boards with the code relocated into the expected position by start.S still can be booted, so the change adds this option and provides an option how to relocate code for board_init_r() execution. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | sh: add common dram_init() function for all boardsVladimir Zapolskiy2016-12-02-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Generic board support assumes a different method of specifying DRAM size on board, also it can be shared among all boards, notably only sh7763rdp board has a custom legacy dram_init(), however the difference is only in printing some additional information, this feature can be removed. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | sh: add MEMORY command to a shared linker scriptVladimir Zapolskiy2016-12-02-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment in runtime all defined sections are copied into or created in RAM, specify this explicitly to assert potential out of RAM placements of the sections. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | sh: define entry point and reloc_dst inside a linker scriptVladimir Zapolskiy2016-12-02-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No functional change, concentrate linker script commands in one place for convenience. Entry point is set to CONFIG_SYS_TEXT_BASE by default on build, so this option can be omitted from being added to the linker script. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | sh: place board lowlevel_init code in the beginning of .textVladimir Zapolskiy2016-12-02-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Reference lowlevel_init of all supported SH2A/SH3/SH4/SH4A boards from a shared linker script, the lowlevel_init function will be called by a relative address. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | sh4: use single u-boot linker script for all boardsVladimir Zapolskiy2016-12-02-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Three supported SH4/SH4A boards with the bootloader image stored on SPI flash have own flavour of a linker script, in turn they are equal among each other. The only difference is that the text from lowlevel_init.o is placed right after start.o, which makes sense. Note that .bss section is not marked as NOLOAD, because for about 10 years this is a default option of a GNU linker, either the attribute is found or not the resulting image file is the same. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | sh4: remove __io config options from r2dplus and r7780mp boardsVladimir Zapolskiy2016-12-02-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | Defined __io is no-op for the SH architecture and it can be removed from board files without any functional change. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | sh4: cache: move exported cache manipulation functions into cache.cVladimir Zapolskiy2016-12-02-39/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | No functional change, moving cache manipulation functions into cache.c allows to collect all of them in a single location and as a pleasant side effect cache_control() function can be unexported now. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | sh: cache: don't modify CCR from P1 areaVladimir Zapolskiy2016-12-02-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cache_wback_all() is a local function and it is called from cache_control() only, which is in turn jumps to P2 area. The change fixes an issue when cache_wback_all() returns from P2 to P1, however cache_control() continues to manipulate with CCR register, according to the User's Manual this is restricted. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
generated by cgit v1.1 at 2024-11-20 10:05:29 +0000