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| | * Add e6500 processor detectionKumar Gala2012-08-23-0/+4
| | | | | | | | | | | | | | | Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc8xxx: use topology registers to calculate number of coresYork Sun2012-08-23-9/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | We have actual topology infomation to find out exactly which core is present. Calculate the number of cores if not specified. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc8xxx: Add immap for topology and rcpm registersYork Sun2012-08-23-1/+87
| | | | | | | | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx: Add IFC LAW target ID for FSL High-End SoCPrabhakar Kushwaha2012-08-23-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's High-End SoC are going to have Integrated Flash controller (IFC)'s support. So add IFC LAW target ID support for High-End SoC or corenet SoC. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx:Enable debugger support to missed e500v2 SoCPrabhakar Kushwaha2012-08-23-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some restrictions on external debugging (JTAG). Need to define define CONFIG_SYS_PPC_E500_DEBUG_TLB to enable a temporary TLB entry to be used during boot to work around the limitations. Enable missed e500v2 SoC i.e. MPC8536, MPC8544, MPC8548 and MPC8572 for debug support. Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Cc: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/fsl-corenet: work around erratum A004510Scott Wood2012-08-23-0/+330
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum A004510 says that under certain load conditions, modified cache lines can be discarded, causing data corruption. To work around this, several CCSR and DCSR register updates need to be made in a careful manner, so that there is no other transaction in corenet when the update is made. The update is made from a locked cacheline, with a delay before to flush any previous activity, and a delay after to flush the CCSR/DCSR update. We can't use a readback because that would be another corenet transaction, which is not allowed. We lock the subsequent cacheline to prevent it from being fetched while we're executing the previous cacheline. It is filled with nops so that a branch doesn't cause us to fetch another cacheline. Ordinarily we are running in a cache-inhibited mapping at this point, so we temporarily change that. We make it guarded so that we should never see a speculative load, and we never do an explicit load. Thus, only the I-cache should ever fill from this mapping, and we flush/unlock it afterward. Thus we should avoid problems from any potential cache aliasing between inhibited and non-inhibited mappings. NOTE that if PAMU is used with this patch, it will need to use a dedicated LAW as described in the erratum. This is the responsibility of the OS that sets up PAMU. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/fsl-corenet: remove dead variant symbolsScott Wood2012-08-23-69/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/85xx: remove support for the Freescale P3060Timur Tabi2012-08-23-261/+2
| | | | | | | | | | | | | | | | | | | | | | | | The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/85xx: add support for FM2 DTSEC5Timur Tabi2012-08-23-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * p1014rdb: set ddr bus width properly depending on SVRMatthew McClintock2012-08-23-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, for NAND boot for the P1010/4RDB we hard code the DDR configuration. We can still dynamically set the DDR bus width in the nand spl so the P1010/4RDB boards can boot from the same u-boot image Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc8xxx: Remove P1015 and P1016 from CPU listYork Sun2012-08-23-39/+2
| | | | | | | | | | | | | | | | | | | | | | | | P1015 is the same as P1011 and P1016 is the same as P1012 from software point of view. They have different packages but share SVRs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/corenet_ds: Master module for boot from PCIELiu Gang2012-08-23-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the powerpc processors with PCIE interface, boot location can be configured from one PCIE interface by RCW. The processor booting from PCIE can do without flash for u-boot image. The image can be fetched from another processor's memory space by PCIE link connected between them. The processor booting from PCIE is slave, the processor booting from normal flash memory space is master, and it can help slave to boot from master's memory space. When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the master module, need to finish these processes: 1. Initialize the PCIE port and address space. 2. Set inbound PCIE windows covered slave's u-boot image stored in master's NOR flash. 3. Set outbound windows in order to configure slave's registers for the core's releasing. 4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2" or "PCIE3" using the following command: setenv bootmaster PCIE1 saveenv Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macroLiu Gang2012-08-23-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. The code will get this information from RCW and then finishes corresponding configurations. This has the following advantages: 1. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just rewrite the new RCW with selected port, then the code will get the port information by reading new RCW. 2. It will be easier to support other boot location options, for example, boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build targetLiu Gang2012-08-23-99/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Get rid of the SRIOBOOT_MASTER build target, and to support for serving as a SRIO boot master via environment variable. Set the environment variable "bootmaster" to "SRIO1" or "SRIO2" using the following command: setenv bootmaster SRIO1 saveenv The "bootmaster" will enable the function of the SRIO boot master, and this has the following advantages compared with SRIOBOOT_MASTER build configuration: 1. Reduce a build configuration item in boards.cfg file. No longer need to build a special image for master, just use a normal target image and set the "bootmaster" variable. 2. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just set the corresponding value to "bootmaster" based on the using SRIO port. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx: Make NMG_CPU_A011 workaround conditionalYork Sun2012-08-23-3/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This erratum applies to the following SoCs: P4080 rev 1.0, 2.0, fixed in rev 3.0 P2041 rev 1.0, 1.1, fixed in rev 2.0 P3041 rev 1.0, 1.1, fixed in rev 2.0. Workaround for erratum NMG_CPU_A011 is enabled by default. This workaround may degrade performance. P4080 erratum CPU22 shares the same workaround. So it is always enabled for P4080. For other SoCs, it can be disabled by hwconfig with syntax: fsl_cpu_a011:disable Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc: Stack Pointer not properly alignedJoakim Tjernlund2012-08-22-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The code first aligns the SP to 16 then subtract 8, making it 8 bytes aligned. Furthermore the initial stack frame not quite correct either. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * mpc85xx: Initial SP alignment is wrong.Joakim Tjernlund2012-08-22-11/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PowerPC mandates SP to be 16 bytes aligned. Furthermore, a stack frame is added, pointing to the reset vector which may in the way when gdb is walking the stack because the reset vector may not accessible depending on emulator settings. Also use a temp register so gdb doesn't pick up intermediate values. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2012-09-21-269/+448
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| * | | Flex bus definition update for Coldfire 5253.Jason Jin2012-09-20-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | originally work by Jate Sujjavanich <jsujjavanich@syntech-fuelmaster.com> ---- The defines in arch/m68k/include/coldfire/flexbus.h are not compatible with the 5235 processor. The registers in struct fbcs are different sizes from those in the 5235. Also, the defines are a little different. This is what I have so far. Comments? ---- Reformat the patch manually by Jason Jin Signed-off-by: Jate Sujjavanich <jsujjavanich@syntech-fuelmaster.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
| * | | ColdFire: Queued SPI driverRichard Retanubun2012-09-20-2/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a driver for Freescale Colfire Queued SPI bus. Coded to work with 8 bits per transfer to use with SPI flash. CPOL, CPHA, and CS_ACTIVE_HIGH can be configured. Tested with MCF5270 which have 4 chip selects. Activate by #define CONFIG_CF_QSPI in board config. Signed-off-by: Richard Retanubun <richardretanubun@ruggedcom.com>
| * | | ColdFire: Clean up checkpatch warnings for MCF54451 and MCF54455Alison Wang2012-09-20-187/+201
| | | | | | | | | | | | | | | | Signed-off-by: Alison Wang <b18965@freescale.com>
| * | | ColdFire: Clean up checkpatch warnings for MCF547x and MCF548xAlison Wang2012-09-20-112/+122
| | | | | | | | | | | | | | | | Signed-off-by: Alison Wang <b18965@freescale.com>
| * | | ColdFire: Clean up checkpatch warnings for MCF523xAlison Wang2012-09-20-84/+96
| | | | | | | | | | | | | | | | Signed-off-by: Alison Wang <b18965@freescale.com>
| * | | ColdFire: Clean up checkpatch warnings for MCF532x/MCF537x/MCF5301xAlison Wang2012-09-20-203/+226
| | | | | | | | | | | | | | | | Signed-off-by: Alison Wang <b18965@freescale.com>
| * | | ColdFire: Clean up checkpatch warnings for MCF52x2Alison Wang2012-09-20-197/+229
| | | | | | | | | | | | | | | | Signed-off-by: Alison Wang <b18965@freescale.com>
| * | | ColdFire: Clean up checkpatch warnings for MCF5227xAlison Wang2012-09-20-101/+107
| | | | | | | | | | | | | | | | Signed-off-by: Alison Wang <b18965@freescale.com>
| * | | ColdFire: Add clear and set bits macros for ColdFire platformAlison Wang2012-09-20-1/+37
| | | | | | | | | | | | | | | | Signed-off-by: Alison Wang <b18965@freescale.com>
| * | | ColdFire: Update the bitops for ColdFire platformAlison Wang2012-09-20-32/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch uses the general ffs definition to replace the platform ffs definition. This patch also fixes the build error by adding hweightN definition for m5329evb and m5373evb. Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Alison Wang <b18965@freescale.com>
| * | | ARM: Remove apollon boardMarek Vasut2012-09-18-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board is the only board that still sticks to OneNAND IPL. Remove this board, since we have SPL around for a while and OneNAND is well supported in the SPL framework. The board can be revived if necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Tom Rini <trini@ti.com>
| * | | dm: sparc: Fixup the compile warnings in sparc codeMarek Vasut2012-09-18-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Hellstrom <daniel@gaisler.com> Cc: u-boot-dm@lists.denx.de
| * | | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2012-09-17-1/+2
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| | * | | omap4 i2c: add support for i2c bus 4Koen Kooi2012-09-06-1/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
| * | | | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2012-09-14-29/+151
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| | * | | | MIPS: move CONFIG_STANDALONE_LOAD_ADDR to CPU config makefilesDaniel Schwierzeck2012-08-24-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prepare for upcoming MIPS64 CPU support. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| | * | | | MIPS: factor out endianess flag handling to arch config.mkDaniel Schwierzeck2012-08-24-22/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is CPU independent and should be configured architecture-wide. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| | * | | | dm: mips: Import libgcc components from LinuxMarek Vasut2012-08-17-0/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Import ashldr3, ashrdi3 and lshrdi3 to squash possible libgcc fp mismatch, resulting in the following warning: mips-linux-gnu-ld: Warning: /usr/lib/gcc/mips-linux-gnu/4.7/libgcc.a(_lshrdi3.o) uses hard float, u-boot uses soft float mips-linux-gnu-ld: Warning: /usr/lib/gcc/mips-linux-gnu/4.7/libgcc.a(_ashldi3.o) uses hard float, u-boot uses soft float Imported from Linux (linux-next 20120723) as of commit: commit 72fbfb260197a52c2bc2583f3e8f15d261d0f924 Author: Ralf Baechle <ralf@linux-mips.org> Date: Wed Jun 7 13:25:37 2006 +0100 [MIPS] Fix optimization for size build. It took a while longer than on other architectures but gcc has finally started to strike us as well ... This also fixes the damage by 6edfba1b33c701108717f4e036320fc39abe1912. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> [<daniel.schwierzeck@gmail.com>: removed USE_PRIVATE_LIBGCC = yes] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| | * | | | dm: mips: Fix lb60 timer codeMarek Vasut2012-08-17-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timer code contains more halfword writes which trigger gcc errors. The registers are again 32bit, yet written by 16bit writes, fix this: timer.c: In function ‘reset_timer_masked’: timer.c:37:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c: In function ‘get_timer_masked’: timer.c:43:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c: In function ‘timer_init’: timer.c:86:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c:88:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c:89:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] timer.c:90:2: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel <zpxu@ingenic.cn> Cc: Shinya Kuribayashi <skuribay@pobox.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
| | * | | | dm: mips: Fix lb60 WDT controlMarek Vasut2012-08-17-1/+1
| | | |_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Write the TSCR register via 32bit write instead of 16bit one. The register is 32bit wide and bit 16 is being set, triggering gcc overflow error and making the code broken. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel <zpxu@ingenic.cn> Cc: Shinya Kuribayashi <skuribay@pobox.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
| * | | | Merge branch 'master' of git://www.denx.de/git/u-boot-mmcTom Rini2012-09-12-4/+4
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| | * | | | mmc: s5p_sdhci: fixed wrong function argumentJaehoon Chung2012-09-05-4/+4
| | | |/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Useless code is removed, and get buswidth value. buswidth value will be used to choice the 4bit or 8bit. (Now used 4bit mode in sdhci.c by default) Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungin.park@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | | microblaze: board: Use bi_flashstart instead of CONFIG_SYS_FLASH_BASEMichal Simek2012-09-11-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prepare for device-tree driven configuration. Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Stephan Linz <linz@li-pro.net>
| * | | | microblaze: Clean microblaze initializationMichal Simek2012-09-11-15/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move board specific function to board_init function in board/ folder Remove externs from generic board.c Use board_init_f function in board.c file. Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Stephan Linz <linz@li-pro.net>
| * | | | microblaze: timer: Prepare for device-tree initializationMichal Simek2012-09-11-38/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix CONFIG_SYS_HZ usage in board config. Do not use hardcoded value. Use CONFIG_SYS_HZ instead. Separate static configuration to single block. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | | | microblaze: intc: Coding style cleanupMichal Simek2012-09-11-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just coding style cleanup. Remove unneeded externs. Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Stephan Linz <linz@li-pro.net>
| * | | | microblaze: intc: Registering interrupt should return valueMichal Simek2012-09-11-8/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Return value to find out if un/registration was succesful. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | | | microblaze: board: Remove compilation warningMichal Simek2012-09-11-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Variable is used when CONFIG_SYS_FLASH_CHECKSUM is used. Warning log: board.c: In function 'board_init': board.c:101: warning: unused variable 's' Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Stephan Linz <linz@li-pro.net>
| * | | | microblaze: Add support for device tree driven board configurationMichal Simek2012-09-11-0/+28
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is minimum code required to be able to use device-tree for u-boot initialization. Currently only for device driver initialization. Linker script change ensures DTB to be aligned for both options CONFIG_OF_EMBED and CONFIG_OF_SEPARATE. Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Stephan Linz <linz@li-pro.net> CC: Simon Glass <sjg@chromium.org>
| * | | Merge branch 'master' of git://git.denx.de/u-boot-avr32Wolfgang Denk2012-09-04-3/+1
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-avr32: net:macb: add line break avr32:portmux: fix setup for macb1 avr32: Remove redundant LDSCRIPT definition Signed-off-by: Wolfgang Denk <wd@denx.de>
| | * | | avr32:portmux: fix setup for macb1Andreas Bießmann2012-09-03-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use portd_mask instead of portc_mask to setup the pins for port D. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| | * | | avr32: Remove redundant LDSCRIPT definitionBenoît Thébaudeau2012-09-02-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AVR32's LD script uses a standard location that is now automatically detected by the main Makefile, so its definition in AVR32's config.mk is now obsolete and redundant. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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