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* | Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc.Tom Warren2015-08-05-174/+285
| | | | | | | | | | | | | | | | | | | | | | | | | | Added PLL variables (dividers mask/shift, lock enable/detect, etc.) to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X. Used pllinfo struct in all clock functions, validated on T210. Should be equivalent to prior code on T124/114/30/20. Thanks to Marcel Ziswiler for corrections to the T20/T30 values. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Tegra: clocks: Add 38.4MHz OSC support for T210 useTom Warren2015-08-05-6/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added 38.4MHz/48MHz entries to pll_x_table for CPU PLL. Needs to be measured - should be close to 700MHz (1.4G/2). Note that some freqs aren't in the PLLU table in T210 TRM (13, 26MHz), so I used the 12MHz table entry for them. They shouldn't be selected since they're not viable T210 OSC freqs. Since there are now 2 new OSC defines, all tables (pll_x_table, PLLU) had to increase by two entries, but since 38.4/48MHz are not viable osc freqs on T20/30/114, etc, they're just set to 0. Signed-off-by: Tom Warren <twarren@nvidia.com>
* | T210: P2571: Turn CPU fan onTom Warren2015-08-05-0/+3
|/ | | | | | | | CPU board (E2530) has a fan - turn it on via GPIO to keep the SoC cool. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-08-05-136/+5552
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| * x86: qemu: Support operation as an EFI payloadSimon Glass2015-08-05-1/+6
| | | | | | | | | | | | | | | | | | Disable a few things which interfere with the EFI init. This allows QEMU to to boot into EFI, load a U-Boot payload then boot to the U-Boot prompt. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: baytrail: Support operation as an EFI payloadSimon Glass2015-08-05-1/+5
| | | | | | | | | | | | | | | | | | Disable a few things which interfere with the EFI init. This allows the Minnowboard MAX to boot into EFI, load a U-Boot payload then boot to the U-Boot prompt. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add helper code for running from EFISimon Glass2015-08-05-0/+165
| | | | | | | | | | | | | | | | | | | | When U-Boot is running from EFI some of the x86 init is replaced with EFI-specific init. For example, since DRAM has already been set up, we only need to find it, not init it. Add these functions so that boards can easily allow booting from EFI if required. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Handle running as EFI payloadSimon Glass2015-08-05-10/+43
| | | | | | | | | | | | | | | | | | When U-Boot runs as an EFI payload it needs to avoid setting up the CPU again. Also U-Boot currently does not handle interrupts for many devices, so run with interrupts disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add support for passing tables into U-BootSimon Glass2015-08-05-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | The EFI stub provides information to U-Boot in a table. This includes the memory map which is needed to decide where to relocate U-Boot. Collect this information in the early init code and store it in global_data. Fix up the BIST code at the same time since we don't have it when booting from EFI and can assume it is 0. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * efi: Add 64-bit payload supportSimon Glass2015-08-05-1/+65
| | | | | | | | | | | | | | | | | | | | | | | | Most EFI implementations use 64-bit. Add a way to build U-Boot as a 64-bit EFI payload. The payload unpacks a (32-bit) U-Boot and starts it. This can be enabled for x86 boards at present. Signed-off-by: Simon Glass <sjg@chromium.org> Improvements to how the payload is built: Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add a way to call 32-bit code from 64-bit modeSimon Glass2015-08-05-0/+79
| | | | | | | | | | | | | | | | | | The procedure to drop from 64-bit mode to 32-bit is a bit messy. Add a function to take care of it. It requires identity-mapped pages and that the calling code is running below 4GB. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add an enum for some commonly-used GDT bitsSimon Glass2015-08-05-0/+18
| | | | | | | | | | | | | | | | Rather than add these as open-coded values, create an enum with the commonly used flags. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Support building the EFI stubSimon Glass2015-08-05-1/+25
| | | | | | | | | | | | | | | | Add support for building a 32/64-bit EFI stub for x86. This involves building the startup and relocation code for either i386 or x86_64. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * efi: Add support for loading U-Boot through an EFI stubSimon Glass2015-08-05-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is useful to be able to load U-Boot onto a board even if is it already running EFI. This can allow access to the U-Boot command interface, flexible booting options and easier development. The easiest way to do this is to build U-Boot as a binary blob and have an EFI stub copy it into RAM. Add support for this feature, targeting 32-bit initially. Also add a way to detect when U-Boot has been loaded via a stub. This goes in common.h since it needs to be widely available so that we avoid redoing initialisation that should be skipped. Signed-off-by: Simon Glass <sjg@chromium.org> Improvements to how the payload is built: Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add relocation and link script for a 64-bit EFI applicationSimon Glass2015-08-05-0/+149
| | | | | | | | | | | | | | | | | | | | Add a linker script and relocation code for building 64-bit EFI applications. This can be used for the EFI stub. Signed-off-by: Simon Glass <sjg@chromium.org> Improvements to how the payload is built: Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Allow relocation code to build without text baseSimon Glass2015-08-05-6/+11
| | | | | | | | | | | | | | | | | | This code currently requires CONFIG_SYS_TEXT_BASE but this should be unnecessary. As a first step, remove the build-time limitation and report an error instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: dts: Add a device tree file for EFISimon Glass2015-08-05-0/+23
| | | | | | | | | | | | | | | | This contains just enough to bring up the serial UART. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add EFI board codeBen Stoltz2015-08-05-0/+1
| | | | | | | | | | | | | | | | | | | | Add support for the efi-x86 board, which supports running U-Boot as an EFI 32-bit application. Signed-off-by: Ben Stoltz <stoltz@google.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add support for U-Boot as an EFI applicationBen Stoltz2015-08-05-0/+319
| | | | | | | | | | | | | | | | | | | | Add the required x86 glue code. This includes the initial start-up, relocation and jumping to efi_main(). We also need to avoid fiddling with interrupts. Signed-off-by: Ben Stoltz <stoltz@google.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add asm/elf.h for x86-specific ELF definitionsSimon Glass2015-08-05-0/+46
| | | | | | | | | | | | | | | | Bring in this file from Linux 4.1. It supports relocation features specific to x86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Support skipping relocation for EFISimon Glass2015-08-05-0/+6
| | | | | | | | | | | | | | | | When running as an EFI application we must skip relocation. Add support for this in the x86 relocation code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Set up toolchain flags for running as EFI applicationBen Stoltz2015-08-05-3/+27
| | | | | | | | | | | | | | | | | | | | Adjust the toolchain flags to build U-Boot as a relocatable shared library, as required by EFI. Signed-off-by: Ben Stoltz <stoltz@google.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * efi: Add start-up library codeSimon Glass2015-08-05-57/+2
| | | | | | | | | | | | | | | | | | | | | | When running as an EFI application, U-Boot must request memory from EFI, and provide access to the boot services U-Boot needs. Add library code to perform these tasks. This includes efi_main() which is the entry point from EFI. U-Boot is built as a shared library. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Allow use of global_data with EFISimon Glass2015-08-05-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On x86 the global_data pointer is provided through a somewhat-bizarre and x86-specific mechanism: the F segment register is set to a pointer to the start of global_data, so that accesses can use this build-in register. When running as an EFI application we don't want to mess with the Global Descriptor Table (GDT) and there is little advantage (in terms of code size) to doing so. Allow global_data to be a simple variable in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Tidy up a few minor issues with interruptsSimon Glass2015-08-05-5/+4
| | | | | | | | | | | | | | | | Fix a typo, remove an unused field and make sure to use existing #define constants instead of open-coded values. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add some missing global_data declarations in files that use gdSimon Glass2015-08-05-0/+10
| | | | | | | | | | | | | | Some files use global_data but don't declare it. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Tidy up the 64-bit calling codeSimon Glass2015-08-05-2/+2
| | | | | | | | | | | | | | | | The GDT works but technically the length is incorrect. Fix this and add a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Drop unused copy_fdt_to_ram()Simon Glass2015-08-05-19/+0
| | | | | | | | | | | | | | | | This is now handled by generic U-Boot code so we do not need an x86 version. It is no-longer called, so remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Tidy up global_data flagsSimon Glass2015-08-05-7/+11
| | | | | | | | | | | | | | | | | | | | These flags now overlap some global ones. Adjust the x86-specific flags to avoid this. Since this requires a change to the start.S code, add a way for tools to find the 32-bit cold reset entry point. Previously this was at a fixed offset. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Use CR0 constants in CPU initSimon Glass2015-08-05-1/+1
| | | | | | | | | | | | | | We should use these constants where possible. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add various minor tidy-ups to the 32-bit startup codeSimon Glass2015-08-05-20/+26
| | | | | | | | | | | | | | | | Fix a typo, improve some comments and add a little more detail in some cases. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: bayleybay: Configure PCI IRQBin Meng2015-08-05-0/+71
| | | | | | | | | | | | | | | | Add PCI IRQ routing information in the board device tree and enable writing PIRQ routing table and MP table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add Intel Bayley Bay board supportBin Meng2015-08-05-1/+136
| | | | | | | | | | | | | | | | Intel Bayley Bay board is a BayTrail based board. Add this board with existing baytrail fsp support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add microcode for BayTrail-I B0 steppingBin Meng2015-08-05-0/+4244
| | | | | | | | | | | | | | | | This commit adds the microcode blob for BayTrail-I B0 stepping, CPUID signature 30671h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: baytrail: Update UPD setting for FSP Gold4 releaseBin Meng2015-08-05-1/+2
| | | | | | | | | | | | | | | | BayTrail FSP Gold4 release adds one UPD parameter to control IGD enable/disable. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: qemu: Add MP initializationBin Meng2015-08-05-0/+14
| | | | | | | | | | | | | | | | | | Add a cpu1 node to the device tree and enable the MP initialization on QEMU targets (i440fx and q35). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * x86: Add a 'pause' instruction in __udelay() for QEMU targetMiao Yan2015-08-05-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When running SMP configuration on QEMU (tcg mode, no kvm), there is a busy loop in start_aps(), calling udelay(), that waits for APs to show up online. However, there is a chance that VCPU1 will be timeout waiting, IOW the secondary VCPUs haven't started their execution yet. This patch adds a 'pause' instruction in __udelay() only for QEMU target, to give other VCPUs a chance to run. When QEMU sees the 'pause' instruction, it will yeild the execution to other CPUs. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | sunxi: Drop our own copy of the USB_KEYBOARD optionsHans de Goede2015-08-05-0/+1
| | | | | | | | | | | | | | USB_KEYBOARD is now defined in drivers/usb/Kconfig, drop our own duplicate definition. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | usb: musb-new: CONFIG_MUSB prefix replacement with CONFIG_USB_MUSBPaul Kocialkowski2015-08-05-2/+2
|/ | | | | | | | | USB-related options are usually prefixed with CONFIG_USB and platform-specific adaptation for the MUSB controller already have a CONFIG_USB_MUSB prefix, so this switches all MUSB-related options to a CONFIG_USB_MUSB prefix, for consistency. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* armv8/lsch3/config: Define USB XHCI controller base address for LS2085ANikhil Badola2015-08-03-0/+3
| | | | | | | | Define base address of both usb xhci controllers in lsch3 config in the format (IMMR + offset) for LS2085A Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/lsch3/config: Define CONFIG_SYS_CACHELINE_SIZE for LS2085ANikhil Badola2015-08-03-0/+1
| | | | | | | | Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by USB XHCI stack for alignment Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv7/ls102xa: Fix non-boot cpus cannot correctly fall in spin tableWang Dongsheng2015-08-03-0/+8
| | | | | | | | | | | Bootrom will put cpus into WFE state when boot cpu release cpus, so target cpu cannot correctly go to spin state. Add 'sev' to wakeup non-boot cpu that hold on bootrom space, let target cpu can fall into u-boot spin table. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-08-02-218/+1776
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| * imx: mx6ul_14x14_evk add basic board supportPeng Fan2015-08-02-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add USDHC, I2C, UART, 74LV, USB, QSPI support. 2. Support SPL 3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default supports sd for usdhc2, but can do hardware rework to make usdhc2 support emmc. Boot Log: U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59) reading u-boot.img reading u-boot.img U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800) CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0 - invalid sensor device Reset cause: POR Board: MX6UL 14x14 EVK I2C: ready DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx:mx6ul add dram spl configuration and header filePeng Fan2015-08-02-10/+141
| | | | | | | | | | | | | | | | | | | | | | | | 1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs. 2. Add a new function mx6ul_dram_iocfg to configure dram io. 3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support runtime check, but not hardcoding #ifdef macros. 4. Introduce mx6ul-ddr.h, which includes the register address for DRAM IO configuration. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/ULPeng Fan2015-08-02-0/+4
| | | | | | | | | | | | | | PAD_CTL_SPEED_LOW for i.MX6SX/UL is (0 << 6) Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: mx6ul update soc related settingsPeng Fan2015-08-02-5/+4
| | | | | | | | | | | | | | | | 1.Update WDOG settings. 2.No need to gate/ungate all PFDs for i.MX6UL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
| * imx: mx6ul select SYS_L2CACHE_OFFPeng Fan2015-08-02-0/+4
| | | | | | | | | | | | | | | | | | i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6 chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled. There is on specific switch for on/off L2 Cache, so default select SYS_L2CACHE_OFF. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx:mx6ul add clock supportPeng Fan2015-08-02-90/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add enet, uart, i2c, ipg clock support for i.MX6UL. 2. Correct get_periph_clk, it should account for MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK. 3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function, but not use 'ifdef'. 4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX. 5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q) || defined....", only need one CONFIG_PCIE_IMX in header file. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx-common: timer: add i.MX6UL supportPeng Fan2015-08-02-3/+5
| | | | | | | | | | | | Add i.MX6UL GPT timer support. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
generated by cgit v1.1 at 2024-09-23 10:36:45 +0000