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* dt: socfpga: Import and enable Arria V DK DTSMarek Vasut2015-03-04-0/+109
| | | | | | | | | | | | | Import DTS for Arria V development kit and enable support for DT. The DT is imported from Linux 3.19-rc1 as of commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* dt: socfpga: Import and enable Cyclone V DK DTSMarek Vasut2015-03-04-1/+82
| | | | | | | | | | | | | Import DTS for Cyclone V development kit and enable support for DT. The DT is imported from Linux 3.19-rc1 as of commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* arm: socfpga: Add Altera Arria V DK supportMarek Vasut2015-03-04-0/+5
| | | | | | | | | | | Add support for the Altera Arria V development kit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* Merge branch 'xnext/zynqmp' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-03-02-0/+172
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| * arm64: Add Xilinx ZynqMP supportMichal Simek2015-03-02-0/+172
| | | | | | | | | | | | | | | | | | Add basic Xilinx ZynqMP arm64 support. Serial and SD is supported. It supports emulation platfrom ep108 and QEMU. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | armv7.h: Add <asm/io.h>Tom Rini2015-03-02-0/+1
| | | | | | | | | | | | | | With a389531 we now call readl() from this file so add <asm/io.h> so that we have a prototype for the function. Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2015-03-01-35/+479
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| * | Exynos: Fix L2 cache timings on Exynos5420 and Exynos5800Doug Anderson2015-02-28-95/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It was found that the L2 cache timings that we had before could cause freezes and hangs. We should make things more robust with better timings. Currently the production ChromeOS kernel applies these timings, but it's nice to fixup firmware too (and upstream probably won't take our kernel hacks). This also provides a big cleanup of the L2 cache init code avoiding some duplication. The way things used to work: * low_power_start() was installed by the SPL (both at boot and resume time) and left resident in iRAM for the kernel to use when bringing up additional CPUs. It used configure_l2_ctlr() and configure_l2_actlr() when it detected it was on an A15. This was needed (despite the L2 cache registers being shared among all A15s) because we might have been the first man in after the whole A15 cluster was shutdown. * secondary_cores_configure() was called on at boot time and at resume time. Strangely this called configure_l2_ctlr() but not configure_l2_actlr() which was almost certainly wrong. Given that we'll call both (see next bullet) later in the boot process it didn't matter for normal boot, but I guess this is how L2 cache settings got set on 5420/5800 (but not 5250?) at resume time. * exynos5_set_l2cache_params() was called as part of cache enablement. This should happen at boot time (normally in the SPL except for USB boot where it happens in main U-Boot). Note that the old code wasn't setting ECC/parity in the cache enablement code but we happened to get it anyway because we'd call secondary_cores_configure() at boot time. For resume time we'd get it anyway when the 2nd A15 core came up. Let's make this a whole lot simpler. Now we always set these parameters in the same place for all boots and use the same code for setting up secondary CPUs. Intended net effects of this change (other than cleanup): * Timings go from before: data: 0 cycle setup, 3 cycles (0x2) latency tag: 0 cycle setup, 3 cycles (0x2) latency after: data: 1 cycle setup, 4 cycles (0x3) latency tag: 1 cycle setup, 4 cycles (0x3) latency * L2ACTLR is properly initted on 5420/5800 in all cases. One note is that we're still relying on luck to keep low_power_start() working. The compiler is being nice and not storing anything on the stack. Another note is that on its own this patch won't help to fix cache settings in an RW U-Boot update where we still have the RO SPL. The plan for that is: * Have RW U-Boot re-init the cache right before calling the kernel (after it has turned the L2 cache off). This is why the functions are in a header file instead of lowlevel_init.c. * Have the kernel save the L2 cache settings of the boot CPU and apply them to all other CPUs. We get a little lucky here because the old code was using "|=" to modify the registers and all of the bits that it's setting are also present in the new settings (!). That means that when the 2nd CPU in the A15 cluster comes up it doesn't actually mess up the settings of the 1st CPU in the A15 cluster. An alternative option is to have the kernel write its own low_power_start() code. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos542x: Make A7s boot with thumb-mode U-Boot on warm resetAkshay Saraswat2015-02-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On warm reset, all cores jump to the low_power_start function because iRAM data is retained and because while executing iROM code all cores find the jump flag 0x02020028 set. In low_power_start, cores check the reset status and if true they clear the jump flag and jump back to 0x0. The A7 cores do jump to 0x0 but consider following instructions as a Thumb instructions which in turn makes them loop inside the iROM code instead of jumping to power_down_core. This issue is fixed by replacing the "mov pc" instruction with a "bx" instruction which switches state along with the jump to make the execution unit consider the branch target as an ARM instruction. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos542x: Fix secondary core booting for thumbAkshay Saraswat2015-02-28-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When compiled SPL for Thumb secondary cores failed to boot at the kernel boot up. Only one core came up out of 4. This was happening because the code relocated to the address 0x02073000 by the primary core was an ARM asm code which was executed by the secondary cores as if it was a thumb code. This patch fixes the issue of secondary cores considering relocated code as Thumb instructions and not ARM instructions by jumping to the relocated with the help of "bx" ARM instruction. "bx" instruction changes the 5th bit of CPSR which allows execution unit to consider the following instructions as ARM instructions. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos542x: add L2 control register configurationAkshay Saraswat2015-02-28-13/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does 3 things: 1. Enables ECC by setting 21st bit of L2CTLR. 2. Restore data and tag RAM latencies to 3 cycles because iROM sets 0x3000400 L2CTLR value during switching. 3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR. We need to restore this here due to switching. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos542x: cache: Disable clean/evict push to externalAkshay Saraswat2015-02-28-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | L2 Auxiliary Control Register provides configuration and control options for the L2 memory system. Bit 3 of L2ACTLR stands for clean/evict push to external. Setting bit 3 disables clean/evict which is what this patch intends to do. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos542x: Add workaround for exynos iROM errataAkshay Saraswat2015-02-28-16/+200
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | iROM logic provides undesired jump address for CPU2. This patch adds a programmable susbstitute for a part of iROM logic which wakes up cores and provides jump addresses. This patch creates a logic to make all secondary cores jump to a particular address which evades the possibility of CPU2 jumping to wrong address and create undesired results. Logic of the workaround: Step-1: iROM code checks value at address 0x2020028. Step-2: If value is 0xc9cfcfcf, it jumps to the address (0x202000+CPUid*4), else, it continues executing normally. Step-3: Primary core puts secondary cores in WFE and store 0xc9cfcfcf in 0x2020028 and jump address (pointer to function low_power_start) in (0x202000+CPUid*4). Step-4: When secondary cores recieve event signal they jump to this address and continue execution. Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos542x: Add workaround for ARM errata 799270Akshay Saraswat2015-02-28-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds workaround for the ARM errata 799270 which says "If the L2 cache logic clock is stopped because of L2 inactivity, setting or clearing the ACTLR.SMP bit might not be effective. The bit is modified in the ACTLR, meaning a read of the register returns the updated value. However the logic that uses that bit retains the previous value." Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos542x: Add workaround for ARM errata 798870Akshay Saraswat2015-02-28-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds workaround for ARM errata 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos542x: CPU: Power down all secondary coresAkshay Saraswat2015-02-28-0/+164
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds code to shutdown secondary cores. When U-boot comes up, all secondary cores appear powered on, which is undesirable and causes side effects while initializing these cores in kernel. Secondary core power down happens in following steps: Step-1: After Exynos power-on, primary core starts executing first. Step-2: In iROM code every core has to check 2 flags i.e. addresses 0x02020028 & 0x02020004. Step-3: Initially 0x02020028 is 0 for all cores and 0x02020004 has a jump address for primary core and 0 for all secondary cores. Step-4: Therefore, primary core follows normal iROM execution and jumps to BL1 eventually, whereas all secondary cores enter WFE. Step-5: When primary core comes into function secondary_cores_configure, it puts pointer to function power_down_core into 0x02020004 and provides DSB and SEV for all cores so that they may come out of WFE and jump to power_down_core function. Step-6: And ultimately because of power_down_core all secondary cores shut-down. Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2015-03-01-532/+565
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| * | ARM: UniPhier: remove SSC_WAY_SIZE and SSC_NUM_ENTRIES macrosMasahiro Yamada2015-03-01-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each way of the system cache has 256 entries for PH1-Pro4 and older SoCs, whereas 512 entries for PH1-Pro5 and newer SoCs. The line size is still 128 byte. Thus, the way size is 32KB/64KB for old/new SoCs. To keep lowlevel_init SoC-independent, set BOOT_RAM_SIZE to the constant value 32KB. It is large enough for temporary RAM and should work for all the SoCs of UniPhier family. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | ARM: UniPhier: remove stop_mpll() from PH1-Pro4 PLL initializationMasahiro Yamada2015-03-01-21/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function was intended for MN2WS0235 (what we call PH1-Pro4TV). On that SoC, MPLL is already running on the power-on reset and it makes sense to stop the PLL at early boot-up. On the other hand, PH1-Pro4(R) does not have SC_MPLLOSCCTL register, so this function has no point. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | ARM: UniPhier: consolidate MEMCONF setting codeMasahiro Yamada2015-03-01-141/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code is duplicated in ph1-ld4/sg_init.c and ph1-pro4/sg_init.c. Merge the same code into a new file, memconf.c. The helper functions no longer have to be placed in the header file. Also, move them into memconf.c. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | ARM: UniPhier: support 1CS support card for all the UniPhier SoCsMasahiro Yamada2015-03-01-121/+189
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Two support card variants are used with UniPhier reference boards: - 1 chip select support card (original CPLD) - 3 chip selects support card (ARIMA-compatible CPLD) Currently, the former is only supported on PH1-Pro4, but it can be expanded to PH1-LD4, PH1-sLD8 with a little code change. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | ARM: UniPhier: add xHCI device nodes to PH1-Pro4 device treeMasahiro Yamada2015-03-01-6/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each USB port corresponds to the following IP core: port0: xHCI (0x65a00000) SS+HS port1: xHCI (0x65c00000) HS (SS PHY is not implemented) port2: EHCI (0x5a800100) HS port3: EHCI (0x5a810100) HS Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | ARM: UniPhier: enable xHCI and GIO cores for PH1-Pro4Masahiro Yamada2015-03-01-1/+25
| | | | | | | | | | | | | | | | | | This is necessary to use the USB 3.0 host controllers on PH1-Pro4. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | ARM: UniPhier: add I/O pin settings for xHCI on PH1-Pro4Masahiro Yamada2015-03-01-0/+7
| | | | | | | | | | | | | | | | | | This is necessary to use the xHCI cores for PH1-Pro4. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | ARM: UniPhier: replace "usb-ehci" with "generic-ehci"Masahiro Yamada2015-03-01-16/+16
| | | | | | | | | | | | | | | | | | | | | EHCI host controllers have a common register interface. We may wish to implement a generic EHCI driver someday. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | ARM: UniPhier: move uniphier_ehci_reset() functionMasahiro Yamada2015-03-01-27/+0
| | | | | | | | | | | | | | | | | | | | | | | | Because uniphier_ehci_reset() is only called from ehci-uniphier.c, it can be a static function there. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de>
| * | ARM: UniPhier: remove EHCI platform devicesMasahiro Yamada2015-03-01-45/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now UniPhier platform highly depends on Device Tree configuration (CONFIG_OF_CONTROL is select'ed by Kconfig). Since the EHCI is only used on main U-Boot, we can drop platform devices of the EHCI controllers. We still keep UART platform devices because they might be useful for SPL. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de>
| * | ARM: UniPhier: enable STDMAC for EHCIMasahiro Yamada2015-03-01-2/+10
| | | | | | | | | | | | | | | | | | | | | Deassert the reset signal and provide the clock for STDMAC core. This is necessary for the USB 2.0 host controllers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | ARM: UniPhier: reset NAND core in SPL for non-NAND boot modeMasahiro Yamada2015-03-01-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For all the UniPhier SoCs so far, the reset signal of the NAND core is automatically deasserted after the PLL gets stabled. (The bit 2 of SC_RSTCTRL is default to one.) This causes a fatal problem on the NAND controller of PH1-LD4. For that SoC, the NAND I/O pins are not set up yet at the power-on reset except the NAND boot mode. As a result, the NAND controller begins automatic device scanning with wrong I/O pins and finally hangs up. Actually, U-Boot dies after printing "NAND:" on the console unless the boot mode latch detected the NAND boot mode. To work around this problem, reset the NAND core in SPL for non-NAND boot modes. If CONFIG_NAND_DENALI is enabled, the reset signal is deasserted again in U-Boot proper. At this time, I/O pins have been correctly set up, the device scanning should succeed. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | ARM: UniPhier: split clkrst_init() into two functionsMasahiro Yamada2015-03-01-49/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split the current clkrst_init() into two functions: - early_clkrst_init(): called from SPL Deassert the reset signals of the memory controller and some other basic cores. - clkrst_init(): called from main U-boot Deassert the reset signals that are necessary for the access to peripherals etc. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | ARM: UniPhier: rename SC_CLKCTRL_CLK_* to SC_SCLKCTRL_CEN_*Masahiro Yamada2015-03-01-13/+13
| | | | | | | | | | | | | | | | | | Follow the register macros in the LSI specification book. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | ARM: UniPhier: fix SBC init codeMasahiro Yamada2015-03-01-25/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now UniPhier SoCs only work with CONFIG_SPL and the function sbc_init() is called from SPL. The conditional #if !defined(CONFIG_SPL_BUILD) has no point any more. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | ARM: UniPhier: fix comments in PH1-Pro4 SBC codeMasahiro Yamada2015-03-01-3/+3
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | ARM: UniPhier: include <mach/*.h> instead of <asm/arch/*.h>Masahiro Yamada2015-03-01-68/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 0e7368c6c426 (kbuild: prepare for moving headers into mach-*/include/mach), we can replace #include <asm/arch/*.h> with <mach/*.h> so we do not need to create the symbolic link during the build. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | ARM: UniPhier: move SoC headers to mach-uniphier/include/machMasahiro Yamada2015-03-01-0/+0
| | | | | | | | | | | | | | | | | | | | | Move arch/arm/include/asm/arch-uniphier/* -> arch/arm/mach-uniphier/include/mach/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | ARM: UniPhier: move SoC sources to mach-uniphierMasahiro Yamada2015-03-01-2/+2
| |/ | | | | | | | | | | | | Move arch/arm/cpu/armv7/uniphier/* -> arch/arm/mach-uniphier/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2015-03-01-21/+1248
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| * | arm: rmobile: Add Porter board supportVladimir Barinov2015-02-25-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Porter is an entry level development board based on R-Car M2 SoC (R8A7791) This commit supports the following peripherals: - SCIF, I2C, Ethernet, QSPI, SD, USB Host Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: lager: Add support SDHINobuhiro Iwamatsu2015-02-25-8/+993
| | | | | | | | | | | | | | | | | | | | | | | | | | | Lager board has two SDHI port as SDHI0 and SDHI2. This adds GPIO configuration and initialization function of SDHI, and enables MMC command. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | arm: rmobile: alt: Add support SDHINobuhiro Iwamatsu2015-02-25-12/+250
| | | | | | | | | | | | | | | | | | | | | | | | | | | Alt board has two SDHI port. This adds GPIO configuration and initialization function of SDHI, and enables MMC command. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini2015-03-01-2/+939
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| * | sh: enable CONFIG_USE_PRIVATE_LIBGCC by defaultMasahiro Yamada2015-02-25-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Now this feature works. Let's turn it on by default so we do not depend on specific tool-chains. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: import missing private libraries from Linux 3.19Masahiro Yamada2015-02-25-2/+936
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SuperH is supposed to support the Private Library feature, but it is actually not working. If CONFIG_USE_PRIVATE_LIBGCC is enabled, the build fails for the undefined references to '__sdivsi3_i4i' and '__udivsi3_i4i'. To fix this error, import missing libraries from Linux 3.19 and adjust them for U-Boot: - Remove "#include <linux/module.h>" and "EXPORT_SYMBOL(...)" - Use SPDX-License-Identifier - Remove white space Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | sh: rename some private librariesMasahiro Yamada2015-02-25-2/+2
| |/ | | | | | | | | | | | | | | Rename two files to the corresponding file names in Linux. This helps us find missing libraries in the next commit. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-02-25-89/+575
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| * | arm: ls1021x: Add support for initializing CAAM's stream idAlison Wang2015-02-24-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | There 4 JRs, 4 RTICs and 8 DECOs, and set them the same stream id for using the same SMMU3 on LS1021A. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: workaround for cache coherency problemchenhui zhao2015-02-24-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RCPM FSM may not be reset after power-on, for example, in the cases of cold boot and wakeup from deep sleep. It causes cache coherency problem and may block deep sleep. Therefore, reset them if they are not be reset. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm/ls102xa: use a array to define pexmscportsrMinghuan Lian2015-02-24-2/+1
| | | | | | | | | | | | | | | Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm/ls102xa: create TLB to map PCIe regionMinghuan Lian2015-02-24-10/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1021A's PCIe1 region begins 0x40_00000000; PCIe2 begins 0x48_00000000. In order to access PCIe device, we must create TLB to map the 40bit physical address to 32bit virtual address. This patch will enable MMU after DDR is available and creates MMU table in DRAM to map all 4G space; then, re-use the reserved space to map PCIe region. The following the mapping layout. VA mapping: ------- <---- 0GB | | | | |-------| <---- 0x24000000 |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000 |-------| <---- 0x300000000 | | |-------| <---- 0x34000000 |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000 |-------| <---- 0x40000000 | | |-------| <---- 0x80000000 DDR0 space start |\\\\\\\| |\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space |\\\\\\\| ------- <---- 4GB DDR0 space end Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Define default values for some CCSR macrosAlison Wang2015-02-24-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | This patch is to define default values for some CCSR macros to make header files cleaner. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-14 17:04:52 +0000