summaryrefslogtreecommitdiff
path: root/arch
Commit message (Collapse)AuthorAgeLines
* Add copy command to FSL DDR interactiveJames Yang2013-01-30-0/+127
| | | | | | | | | Add copy command which allows copying of DIMM/controller settings. This saves tedious retyping of parameters for each identical DIMM or controller. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Fix data stage name matching issueJames Yang2013-01-30-1/+2
| | | | | | | | | | This fix allows the name of the stage to be specifed after the controler and DIMM is specified. Prior to this fix, if the data stage name is not the first entry on the command line, the operation is applied to all controller and DIMMs. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Move DDR command parsing to separate functionJames Yang2013-01-30-79/+74
| | | | | | | | Move the FSL DDR prompt command parsing to a separate function so that it can be reused. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc8xxx: Enable entering DDR debugging by key pressYork Sun2013-01-30-2/+4
| | | | | | | | | | | | | | | Using environmental variable "ddr_interactive" to activate interactive DDR debugging seomtiems is not enough. For example, after updating SPD with a valid but wrong image, u-boot won't come up due to wrong DDR configuration. By enabling key press method, we can enter debug mode to have a chance to boot without using other tools to recover the board. CONFIG_FSL_DDR_INTERACTIVE needs to be defined in header file. To enter the debug mode by key press, press key 'd' shortly after reset, like one would do to abort auto booting. It is fixed to lower case 'd' at this moment. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx:Fix Core cluster configuration loopPrabhakar Kushwaha2013-01-30-8/+22
| | | | | | | | | | | | | | Different personalities/derivatives of SoC may have reduced cluster. But it is not necessary for last valid DCFG_CCSR_TP_CLUSTER register to have DCFG_CCSR_TP_CLUSTER[EOC] bit set to represent "End of Clusters". EOC bit can still be set in last DCFG_CCSR_TP_CLUSTER register of orignal SoC which may not be valid for the personality. So add initiator type check to find valid cluster. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx:Add support of B4420 SoCPoonam Aggrwal2013-01-30-1/+76
| | | | | | | | | | | | | | | | | | | | | B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Few updates for B4860 cpu changesPoonam Aggrwal2013-01-30-1/+16
| | | | | | | | | | | | | | | - Added some more serdes1 and serdes2 combinations serdes1= 0x2c, 0x2d, 0x2e serdes2= 0x7a, 0x8d, 0x98 - Updated Number of DDR controllers to 2. - Added FMAN file for B4860, drivers/net/fm/b4860.c Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Reserve default boot pageYork Sun2013-01-30-0/+16
| | | | | | | | | The boot page in memory is already reserved so OS won't overwrite. As long as the boot page translation is active, the default boot page also needs to be reserved in case the memory is 4GB or more. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxTom Rini2013-01-29-13/+92
|\
| * Merge remote-tracking branch 'mpc83xx/next'Kim Phillips2013-01-16-13/+92
| |\
| | * powerpc/mpc83xx: add support for new SPLScott Wood2012-12-19-13/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds arch support for PPC mpc83xx to boot "minimal" (4K) SPLs using the new infrastructure. Existing nand_spl targets are updated to deal with the name change from nand_init.c to spl_minimal.c (as in theory this isn't limited to NAND anymore). Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | | MIPS: bootm.c: add support for 'prep' and 'go' subcommandsGabor Juhos2013-01-16-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The bootm command supports subcommands since long time however those subcommands are not yet usable on MIPS. The patch is based on the ARM implementation, and it adds support for the 'prep' and 'go' subcommands only. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* | | MIPS: bootm.c: separate environment initializationGabor Juhos2013-01-16-23/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the environment initialization code into a separate function. This make the code reusable for bootm subcommands. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* | | MIPS: bootm.c: separate linux jump codeGabor Juhos2013-01-16-13/+19
| | | | | | | | | | | | | | | | | | | | | | | | Move the actual jump code into a separate function. This make the code reusable for bootm subcommands. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* | | MIPS: bootm.c: use debug macro to print debug messageGabor Juhos2013-01-16-3/+1
|/ / | | | | | | | | | | | | | | The '## Transferring control ...' message is printed only if DEBUG is enabled. Get rid of the 'ifdef DEBUG' statement and use the debug macro instead. Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
* | pxa: Save lr register in relocate_code functionŁukasz Dałek2013-01-14-0/+2
| | | | | | | | | | | | | | | | | | | | | | When u-boot is compiled for PXA25x processor, pxa/start.S is calling cpu_init_crit by BL instruction. BL is overwriting lr register so relocate_code is going into infinite loop. This patch preservs lr register in r12 before calling cpu_init_crit and after function returns restores it. Signed-off-by: Lukasz Dalek <luk0104@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-01-14-84/+12
|\ \
| * | mx31/mx35/mx51/mx53/mx6: add watchdogTroy Kisky2013-01-13-84/+2
| | | | | | | | | | | | | | | | | | | | | Use a common watchdog driver for all these cpus. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * | mx6: Add workaround for ARM errataFabio Estevam2013-01-09-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add workaround for the following ARM errata: 743622 and 751472. The motivation for this change is the following kernel commit 62e4d357a (ARM: 7609/1: disable errata work-arounds which access secure registers), which removes the errata from multiplatform kernel. Since imx has been converted to multiplatform in the kernel, we need to apply such workarounds into the bootloader. Workaround code has been taken from arch/arm/mm/proc-v7.S from 3.7.1 kernel. Explanation of each erratum is provided at "Chip Errata for the i.MX 6Dual/6Quad" document available at: cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-01-14-25/+953
|\ \ \
| * | | Exynos: clock: add CLK_DIV_FSYS3 at set_mmc_clkJaehoon Chung2013-01-11-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mobile storage is used the CLK_DIV_FSYS3 value. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | Exynos: clock: support get_mmc_clk for exynosJaehoon Chung2013-01-11-0/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To get exactly clock value for mmc, support the get_mmc_clk() like set_mmc_clk(). Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | EXYNOS: Add dummy definition to fix compilation dependency on ↵Ajay Kumar2013-01-10-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_EXYNOS_MIPI_DSIM When only DP is used, we need not enable CONFIG_EXYNOS_MIPI_DSIM. But if we do not select CONFIG_EXYNOS_MIPI_DSIM, exynos_fb.c throws error saying exynos_mipi_dsi_init() not defined. So, we add dummy definition for exynos_mipi_dsi_init when CONFIG_EXYNOS_MIPI_DSIM is not defined. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | EXYNOS5: Change parent clock of FIMD to MPLLAjay Kumar2013-01-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With VPLL as source clock to FIMD, Exynos DP Initializaton was failing sometimes with unstable clock. Changing FIMD source to MPLL resolves this issue. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | EXYNOS5: Add support for FIMD and DPAjay Kumar2013-01-10-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add panel_info structure required by LCD driver and DP panel platdata for SMDK5250. Add GPIO configuration for LCD. Enable FIMD and DP support on SMDK5250. DP Panel size: 2560x1600. We use 16BPP resolution to get LCD console. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chomium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | EXYNOS5: Add device node for USB.Rajeshwari Shinde2013-01-08-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the device node required for USB Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | EXYNOS5: FDT: Add SPI device node dataRajeshwari Shinde2013-01-08-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SPI device node data for exynos. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | EXYNOS5: FDT: Add sound device node dataRajeshwari Shinde2013-01-08-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add sound device node data for exynos Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | EXYNOS5: FDT : Decode peripheral idRajeshwari Shinde2013-01-08-13/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Api is added to decode peripheral id based on the interrupt number of the peripheral. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | EXYNOS5: FDT: Add I2C device node dataRajeshwari Shinde2013-01-08-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C device node data for exynos Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | arm:exynos4:pinmux: Modify the gpio function for mmcPiotr Wilczek2013-01-08-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add pinmux settings for Exynos4 for mmc0 and mmc2 Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | EXYNOS: EXYNOS4X12: extract Exynos4x12 IPs clock frequencyChander Kashyap2012-12-26-5/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds functions to extract clock frequency of Exynos4x12 IPs. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | exynos5: Add DT based driver for SMC911X ethernetHatim RV2012-12-26-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device tree based ethernet driver for SMC911X controller on SMDK5250 boards. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | EXYNOS5: FDT: add initial dts file for EXYNOS5250, SMDK5250Hatim RV2012-12-26-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds initial dts file for EXYNOS5250 SoC. This dts file currently include only ethernet devices and properties. More devices to be added in subsequent patches. Also add the dts file for SMDK5250 board which uses the EXYNOS5250 dts file. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12Chander Kashyap2012-12-26-0/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds gpio structure for Exynos4x12. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12Chander Kashyap2012-12-26-0/+276
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds clock structure for Exynos4x12. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addressesChander Kashyap2012-12-26-6/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch populates base addresses of Exynos4x12 registers. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | | m68k/lib: fix serial driver relocationangelo2013-01-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix coldfire serial driver bindings no more relocated to ram after last changes to drivers/serial/serial.c (regression). Serial initialization in ram has to be called after that gd->reloc_off is calculated. Signed-off-by: Angelo Dureghello <sysamfw@gmail.com> Cc: Jason Jin <jason.jin@freescale.com> Acked-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de> Tested-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-01-11-18/+89
|\ \ \ \
| * | | | arm: Tabify code for MMC initializationTaylor Hutt2013-01-10-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The two modified lines were indented with spaces. They are now indented with tabs. Signed-off-by: Taylor Hutt <thutt@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | arm: Move bootstage record for board_init_f() to after arch_cpu_init()Simon Glass2013-01-10-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timer may be inited in arch_cpu_init() so it is not safe to make a bootstage mark before this is called. Arrange the code to fix this. Note: The question was raised as to why we don't keep all archs in sync. PowerPC doesn't have specific bootstage markers at present (although it does use boot progress). I hope that the generic board series will solve this problem in general, but in the meantime this is a real problem, and only in ARM. We now get a correct time for board_init_f: Timer summary in microseconds: Mark Elapsed Stage 0 0 reset 100,000 100,000 spl_start 848,530 748,530 board_init_f 907,301 58,771 board_init_r 910,478 3,177 board_init Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | arm: Make interrupts.o and reset.o in libarm also appear in SPLTom Wai-Hong Tam2013-01-10-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPL u-boot may call do_reset() which depends on interrupts.o and reset.o. So make them also appear in SPL. Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | arm: Add CONFIG_DISPLAY_BOARDINFO_LATE to display board info on LCDSimon Glass2013-01-10-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This option displays board info after stdio is running, so that it will appear on the LCD. If it is displayed earlier, the board info will appear on the serial console but not on the LCD. Here follows a blow-by-blow description. 1a. Without CONFIG_DISPLAY_BOARDINFO_LATE, on serial: U-Boot 2011.12-02550-g037e1c5-dirty (Nov 15 2012 - 14:29:42) for SMDK5250 CPU: S5PC520 @ 1700MHz Board: Google Snow, rev 0 I2C: ready DRAM: 2 GiB Elpida DDR3 @ 800MHz MMC: S5P MSHC0: 0, S5P MSHC1: 1 SF: Detected W25Q32 with page size 4 KiB, total 4 MiB *** Warning - bad CRC, using default environment In: mkbp-keyb Out: lcd Err: lcd Net: No ethernet found. Hit any key to stop autoboot: 0 SMDK5250 # 1b. Without CONFIG_DISPLAY_BOARDINFO_LATE, on LCD (note machine info is missing): In: mkbp-keyb Out: lcd Err: lcd Net: No ethernet found. Hit any key to stop autoboot: 0 SMDK5250 # 2a. With CONFIG_DISPLAY_BOARDINFO_LATE, on serial: U-Boot 2011.12-02550-g037e1c5 (Nov 15 2012 - 14:27:40) for SMDK5250 CPU: S5PC520 @ 1700MHz I2C: ready DRAM: 2 GiB Elpida DDR3 @ 800MHz MMC: S5P MSHC0: 0, S5P MSHC1: 1 SF: Detected W25Q32 with page size 4 KiB, total 4 MiB *** Warning - bad CRC, using default environment Model: Google Snow In: mkbp-keyb Out: lcd Err: lcd Net: No ethernet found. Hit any key to stop autoboot: 0 SMDK5250 # 2b. With CONFIG_DISPLAY_BOARDINFO_LATE, on LCD (note machine info is present): Model: Google Snow In: mkbp-keyb Out: lcd Err: lcd Net: No ethernet found. Hit any key to stop autoboot: 0 SMDK5250 # Since the LCD is all that a typical user sees, it is useful to display the model there. We may be able to rearrange things some other way one day, but at present this seems like a convenient way of getting the required behaviour. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | arm: Add CONFIG_DELAY_ENVIRONMENT to delay environment loadingSimon Glass2013-01-10-2/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This option delays loading of the environment until later, so that only the default environment will be available to U-Boot. This can address the security risk of untrusted data being used during boot. Any time you load untrusted data you expose yourself to a bug in the code. The attacker gets to choose the data so can sometimes carefully craft it to exploit a bug. We try to avoid touching user-controlled data during a verified boot unless strictly necessary. Since the default environment is good enough in this case (or you would just change it), this gets around the problem by just not loading the environment. When CONFIG_DELAY_ENVIRONMENT is defined, it is convenient to have a run-time way of enabling loading of the environment. Add this to the fdt as /config/delay-environment. Note: This patch depends on http://patchwork.ozlabs.org/patch/194342/ Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org>
| * | | | arm: Move fdt check earlier so that board_early_init_f() can use itSimon Glass2013-01-10-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want to use the fdt inside board_early_init_f(), so check for its presence earlier in the pre-reloc init sequence. So far ARM and microblaze are the only only ones that use CONFIG_OF_CONTROL. Microblaze does not have the same init loop, and in particular does not have the board_early_init_f() call. So a patch for microblaze would have no meaning. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | arm: Keep track of the tlb size as well as its locationGabe Black2013-01-10-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It may be necessary to know where the TLB area ends as well as where it starts. This allows board code to complete a secure memory erase without destroying the page tables. Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | arm: move flush_dcache_all() to just before disable cacheArun Mankuzhi2013-01-10-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Cortex-A15 architecture, when we run cache invalidate the cache clean operation executes automatically. So if there are any dirty cache lines before disabling the L2 cache these will be synchronized with the main memory when invalidate_dcache_all() runs in the last part of U-boot The two functions after flush_dcache_all is using the stack. So this data will be on the cache. After disable when invalidate is called the data will be flushed from cache to memory. This corrupts the stack in invalida_dcache_all. So this change is required to avoid the u-boot hang. So flush has to be done just before clearing CR_C bit Signed-off-by: Arun Mankuzhi <arun.m@samsung.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | Merge 'u-boot-atmel/master' into 'u-boot-arm/master'Albert ARIBAUD2013-01-09-0/+15
| |\ \ \ \
| | * | | | at91sam9x5: enable USB support for 9x5ek board.Richard Genoud2012-12-09-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Richard Genoud <richard.genoud@gmail.com> Acked-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | | | Merge branch 'u-boot-marvell/master' into 'u-boot-arm/master'Albert ARIBAUD2013-01-09-3/+3
| |\ \ \ \ \
generated by cgit v1.1 at 2024-11-05 23:28:24 +0000