summaryrefslogtreecommitdiff
path: root/arch
Commit message (Collapse)AuthorAgeLines
* driver/ddr/fsl: Add workaround for erratum A-010165Shengzhou Liu2016-05-18-0/+1
| | | | | | | | | During DDR-2133 operation, the transmit data eye margins determined during the memory controller initialization may be sub-optimal, set DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* crypto/fsl: add support for multiple SEC engines initializationAlex Porosanu2016-05-18-0/+9
| | | | | | | | | For SoCs that contain multiple SEC engines, each of them needs to be initialized (by means of initializing among others the random number generator). Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arch/arm, arch/powerpc: add # of SEC engines on the SOCAlex Porosanu2016-05-18-0/+9
| | | | | | | | | | Some SOCs, specifically the ones in the C29x familiy can have multiple security engines. This patch adds a system configuration define which indicates the maximum number of SEC engines that can be found on a SoC. Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arch/arm: add SEC JR0 offsetAlex Porosanu2016-05-18-10/+28
| | | | | | | | | Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts) Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv7: ls102xa: spl: fix the macro name of MMC modeQianyu Gong2016-05-18-1/+1
| | | | | | | MMCSD_MODE_FAT has been renamed to MMCSD_MODE_FS by commit 205b4f33. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: spl: fix the macro name of MMC modeQianyu Gong2016-05-18-1/+1
| | | | | | | MMCSD_MODE_FAT has be renmaed to MMCSD_MODE_FS by commit 205b4f33. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: spl: remove duplicate init_early_memctl_regs()Qianyu Gong2016-05-18-3/+0
| | | | | | | | init_early_memctl_regs() is also be called in board_early_init_f(). So remove the duplicated call in spl code. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-layerscape: Remove unnecessary flushing dcacheAlison Wang2016-05-18-3/+0
| | | | | | | | | As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/ls1043a: update the node for QSPI supportYuan Yao2016-05-18-2/+3
| | | | | | | | The address value and size value set for QSPI dts node "reg" property have type of u64 on arm64. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/fdt: add fixup_crypto_nodeAlex Porosanu2016-05-17-0/+19
| | | | | | | | | For Qoriq PPC&ARM v7 platforms, the crypto node is being fixup'ed in order to update the SEC internal version (aka SEC ERA). This patch adds the same functionality to the ARMv8 SoCs. Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* driver/ddr/fsl: Add workaround for erratum A-009801Shengzhou Liu2016-05-17-0/+1
| | | | | | | | The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8/ls1043: Add workaround for DDR erratum A-008850Shengzhou Liu2016-05-17-0/+37
| | | | | | | | | Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm/arm64: Move barrier instructions into separate headerAndre Przywara2016-05-12-21/+46
| | | | | | | | | | | | | | | | Commit bfb33f0bc45b ("sunxi: mctl_mem_matches: Add missing memory barrier") broke compilation for the Pine64, as dram_helper.c now includes <asm/armv7.h>, which does not compile on arm64. Fix this by moving all barrier instructions into a separate header file, which can easily be shared between arm and arm64. Also extend the inline assembly to take the "sy" argument, which is optional for ARMv7, but mandatory for v8. This fixes compilation for 64-bit sunxi boards (Pine64). Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-05-06-1/+2
|\
| * socfpga: fix broken build if CONFIG_ETH_DESIGNWARE disabledAnatolij Gustschin2016-05-06-1/+1
| | | | | | | | | | | | | | Building without ethernet driver doesn't work. Fix it. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
| * ARM: socfpga: Disable USB OC protection on SoCratesMarek Vasut2016-05-06-0/+1
| | | | | | | | | | | | | | | | This is mandatory, otherwise the USB does not work. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@kernel.org>
* | imx6: cache: disable L2 before touching Auxiliary Control RegisterPeng Fan2016-05-06-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According PL310 TRM, Auxiliary Control Register " The register must be written to using a secure access, and it can be read using either a secure or a NS access. If you write to this register with a NS access, it results in a write response with a DECERR response, and the register is not updated. Writing to this register with the L2 cache enabled, that is, bit[0] of L2 Control Register set to 1, results in a SLVERR. " So If L2 cache is already enabled by ROM, chaning value of ACR will cause SLVERR and uboot hang. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
* | ARM: am33xx: Fix DDR initialization delaysRuss Dill2016-05-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current delays in the DDR initialization routines for am33xx architectures are sometimes not running long enough leading to DDR init errors. On am437x, this shows up as an L3 NOC error after the kernel boots. This is due to the timer not being initialized properly, but instead still containing the timer init values from the boot ROM which cause timers to expire in 1/4th the time required. timer_init is typically not called until board_init_r, however on am33xx/am43xx udelay is required in sdram_init which is called from board_init_f, so a call to timer_init is required earlier. Note that this issue introduced in v2015.01 by: b352dde "am33xx: Drop timer_init call from s_init". Although this could instead fixed by reverting said commit, it would cause timer_init to be called twice in both SPL and non-SPL cases. This gives a little more fine grained control and also matches what is being done on omap-command and fsl-layerscape. Signed-off-by: Russ Dill <russ.dill@ti.com>
* | ARM: fix ifdefs in ARMv8 lowlevel_init()Stephen Warren2016-05-06-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 724219a65f55 "ARM: always perform per-CPU GIC init" removed some ifdefs to unify the MULTIENTRY-vs-non-MULTIENTRY paths. However, the wrong endif was removed. This patch adds back that missing endif, and adds a new ifdef to match the endif the now-correctly-terminated block used to match against. Use "git show -U25 724219a65f55" to see enough context to make the original issue clear. In practical terms, this makes no difference to runtime behaviour. The code that was incorrectly compiled into the binary when ifndef MULTIENTRY is a no-op for other cases, since branch_if_master evaluates to a hard- coded jump. The only issues were: - A few extra instructions were added to the binary. - The comment on the endif at the very end of the function, indicating which ifdef it matched, were wrong. An alternative might be to simply fix the comment on that trailing ifdef, but that only addresses the second point above, not the first. Fixes: 724219a65f55 ("ARM: always perform per-CPU GIC init") Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Fix various typos, scattered over the code.Robert P. J. Day2016-05-05-4/+4
|/ | | | | | | | | | | | | Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller
* ARM: tegra: enable GPU node by compatible valueStephen Warren2016-05-04-15/+22
| | | | | | | | | | | | | | | | | | | In current Linux kernel Tegra DT files, 64-bit addresses are represented in unit addresses as a pair of comma-separated 32-bit values. Apparently this is no longer the correct representation for simple busses, and the unit address should be represented as a single 64-bit value. If this is changed in the DTs, arm/arm/mach-tegra/board2.c:ft_system_setup() will no longer be able to find and enable the GPU node, since it looks up the node by name. Fix that function to enable nodes based on their compatible value rather than their node name. This will work no matter what the node name is, i.e for DTs both before and after any rename operation. Cc: Thierry Reding <treding@nvidia.com> Cc: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Change my mailaddressAndreas Bießmann2016-05-02-7/+7
| | | | | | I'll switch my mails to my own server, so drop all gmail references. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arch/arm/imx-common/Makefile: Update u-boot.uim MKIMAGEFLAGSTom Rini2016-05-02-1/+1
| | | | | | We need to be passing -T firmware here and aren't. Signed-off-by: Tom Rini <trini@konsulko.com>
* Revert "rockchip: rk3288: correct sdram setting"Vagrant Cascadian2016-05-02-7/+7
| | | | | | | | | | This reverts commit b5788dc0dd9570e98552833767f4373db965985d. Ram size is incorrectly reported as 512MB on a firefly-rk3288 board with 2GB of ram. Reverting this patch displays the full amount of ram. Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-05-02-29/+47
|\
| * ARM: uniphier: move pin-mux code into pin_init functionMasahiro Yamada2016-05-01-27/+5
| | | | | | | | | | | | | | The code in uniphier_sld3_sbc_init() is pin-muxing, so it would be a better fit in uniphier_sld3_early_pin_init(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: allow to use System Bus for ROM boot mode of PH1-LD20Masahiro Yamada2016-05-01-1/+37
| | | | | | | | | | | | | | | | | | The System Bus is not available by default on the ROM boot mode of PH1-LD20. To use devices connected to the System Bus, such as the Micro Support Card, it is necessary to set up pin-muxing and some System Bus Controller register. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: enable Peripherl clock to use UART in SPLMasahiro Yamada2016-05-01-0/+4
| | | | | | | | | | | | This is needed to use UART on SPL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: fix boot mode table of PH1-LD20Masahiro Yamada2016-05-01-1/+1
| | | | | | | | | | | | | | PH1-LD20 does not have the dedicated boot swap select latch. Instead, it is controlled from the boot mode select. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Revert "omap3: Use raw SPL by default for mmc1"Tom Rini2016-05-02-0/+2
|/ | | | | | | | | | | | | Unfortunately with this change we now are unable to do FS mode boots from MMC1 as with the way the code works today we will always load and assume that the hard-coded raw location contains U-Boot. Further, we cannot fix this by just changing other logic to try FS-then-RAW as it would also make us have to ignore what order the ROM is telling us to try. This reverts commit 22d90d560a2b01c47f180e196e6c6485eb8e65db. Signed-off-by: Tom Rini <trini@konsulko.com>
* sunxi: mctl_mem_matches: Add missing memory barrierHans de Goede2016-04-27-0/+2
| | | | | | | | | | | | | | | | | | | | | | | We are running with the caches disabled when mctl_mem_matches gets called, but the cpu's write buffer is still there and can still get in the way, add a memory barrier to fix this. This avoids mctl_mem_matches always returning false in some cases, which was resulting in: U-Boot SPL 2015.07 (Apr 14 2016 - 18:47:26) DRAM: 1024 MiB U-Boot 2015.07 (Apr 14 2016 - 18:47:26 +0200) Allwinner Technology CPU: Allwinner A23 (SUN8I) DRAM: 512 MiB Where 512 MiB is the right amount, but the DRAM controller would be initialized for 1024 MiB. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: DRA7: Add ABB setup for all domainsNishanth Menon2016-04-25-0/+52
| | | | | | | | | | | | | ABB should be initialized for all required domains voltage domain for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If we do not do this, kernel configuring just the frequency using the default boot loader configured voltage can fail on many corner lot units and has been hard to debug. This specifically is a concern with DRA7 generation of SoCs since other than VDD_MPU, all other domains are only permitted to setup the voltages to required OPP only at boot. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: OMAP5: Enable ABB configuration for MM voltage domainNishanth Menon2016-04-25-0/+19
| | | | | | | | | | Since we setup the voltage and frequency for the MM domain, we *must* setup the ABB configuration needed for the domain as well. If we do not do this, kernel configuring just the frequency using the default boot loader configured voltage can fail on many corner lot units. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: OMAP5/DRA7: Move ABB TXDONE mask to voltage structureNishanth Menon2016-04-25-2/+7
| | | | | | | | | | | ABB TX_DONE mask will vary depending on ABB module. For example, 3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain, DRA7 has it on all domains with the exception of CORE, RTC. Hence, move the txdone mask definition over to structure describing voltage domain. Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: OMAP5/DRA7: Get rid of control_std_fuse_opp_vdd_mpu_2Nishanth Menon2016-04-25-5/+2
| | | | | | | | | | | | | This information is already available under vcores->volts.efuse.reg. There is no reason for duplicating the information since AVS Class 0 definitions are common for OMAP5 and DRA7 and defined with STD_FUSE_OPP_* macros. This allows a central location of defining the ABB and voltage definitions especially since they are reused. This also makes it simpler to prevent mistakes involved when changing the boot OPP for the device. Signed-off-by: Nishanth Menon <nm@ti.com>
* ARM: hisilicon: hikey: dts: Add pl011 additional clock binding.Peter Griffin2016-04-25-0/+5
| | | | | | | | This is a binding which only exists in U-Boot, but is required to get working serial in U-Boot. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: hisilicon: hikey: Enable OF_CONTROL for hikey board.Peter Griffin2016-04-25-0/+3
| | | | | | | | | | | Currently only the serial pl01x driver is using DT, and the other drivers still use platform data but as more DT lands in the upstream kernel the aim is to migrate the other drivers over to DT as well to have a fully DT configured hikey u-boot. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: hisilicon: hikey: Add hikey & hi6220 dts from v4.6-rc3.Peter Griffin2016-04-25-0/+254
| | | | | | | | | Import the upstream kernel dts into U-Boot. Currently only serial is supported, but a lot more DT changes are queued for v4.7. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* configs: Re-sync with cmd/KconfigTom Rini2016-04-25-6/+0
| | | | | | | Update the config.h and defconfig files for the commands that 8e3c036 converted over to Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
* configs: Re-sync almost all of cmd/KconfigTom Rini2016-04-25-4/+0
| | | | | | | | This syncs up the current cmd/Kconfig and include/configs/ files with the only exception being CMD_NAND. Due to how we have used this historically we need to take further care here when converting. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-uniphierTom Rini2016-04-25-60/+969
|\
| * ARM: dts: uniphier: add SD controller node for PH1-LD20Masahiro Yamada2016-04-24-0/+17
| | | | | | | | | | | | | | PH1-LD20 does not support 1.8V signaling for SD card; only Default Speed and High Speed (up to 50MHz) with 3.3V signaling is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: add PH1-LD20 SoC supportMasahiro Yamada2016-04-24-3/+888
| | | | | | | | | | | | This is the first ARMv8 SoC from Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: rework uniphier_set_fdt_file()Masahiro Yamada2016-04-24-31/+31
| | | | | | | | | | | | | | | | | | | | | | | | The current table look-up for the DTB file name turned out bothersome in terms of maintainability; I ended up adding a new entry every time a new board is supported. There is a common pattern between the DT compatible string and the corresponding file name; drop the vendor prefix "socionext," and prefix it with "uniphier-" and suffix it with ".dtb". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: carry on booting for Unknown boot modeMasahiro Yamada2016-04-24-2/+2
| | | | | | | | | | | | | | | | No need to stop booting U-Boot even if boot mode is unknown. Setting the "bootmode" environment is only useful for booting Linux Kernel. Anyway, U-Boot has already booted by this point. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: add sg_set_iectrl_range()Masahiro Yamada2016-04-24-0/+8
| | | | | | | | | | | | | | | | For PH1-LD20 or later, per-pin input-enable control is supported, that is, we need to set-up IECTRL registers for a group of pins. This helper function will be useful for a bunch of register settings. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: dts: uniphier: move aliases node up to satisfy fdtgrepMasahiro Yamada2016-04-24-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, fdtgrep would not accept uniphier-ph1-ld20-ref.dtb and uniphier-ph1-ld11-ref.dtb unless the aliases node comes the first in the root node. $ make -s uniphier_pxs2_ld6b_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-ld20-ref [snip] LDS spl/u-boot-spl.lds LD spl/u-boot-spl OBJCOPY spl/u-boot-spl-nodtb.bin FDTGREP spl/u-boot-spl.dtb Error at 'fdt_find_regions': FDT_ERR_BADLAYOUT /aliases node must come before all other nodes Error: FDT_ERR_BADMAGIC make[1]: *** [spl/u-boot-spl.dtb] Error 1 make: *** [spl/u-boot-spl] Error 2 This commit moves the aliases node as the error message from the fdtgrep tool suggests, although this requirement does not sound reasonable to me. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: dts: uniphier: use Ref Daughter board on PH1-LD20 Ref boardMasahiro Yamada2016-04-24-0/+1
| | | | | | | | | | | | | | This makes the EEPROM device on the Reference Daughter board available. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * ARM: uniphier: avoid unaligned access to DT on 64bit SoCMasahiro Yamada2016-04-24-6/+4
| | | | | | | | | | | | | | Because DT properties are 4-byte aligned, the pointer access *(fdt64_t *) in this code causes unaligned access. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-04-25-1/+167
|\ \ | |/ |/|