| Commit message (Collapse) | Author | Age | Lines |
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Move the header file and definitions of ftsmc020
static memory control unit from a320 SoC folder to
"drivers/mtd" folder.
This change will let other SoC which also use ftsmc020
could share the same header file.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
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Move the header file "ftsdmc020.h" (SDRAM Controller)
to "include/faraday" folder.
This change will let other SoC which also use ftsdmc020
could share the same header file.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
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Removed boot_flash_* extern variables.
boot_flash_type was totally unused. The other ones were actually constants, so
they have been replaced with #defines in the board config files.
Signed-off-by: Luca Ceresoli <luca.ceresoli@comelit.it>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.aribaud@free.fr>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Signed-off-by: Tom Warren <twarren@nvidia.com>
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Signed-off-by: Tom Warren <twarren@nvidia.com>
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Since addr_sp is a byte address, it should be adjusted by 12 here.
Signed-off-by: Eric Cooper <ecc@cmu.edu>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Wolfgang Denk <wd@denx.de>
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Signed-off-by: Tom Warren <twarren@nvidia.com>
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Signed-off-by: Luca Ceresoli <luca.ceresoli@comelit.it>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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CONFIG_OMAP34XX must be checked for existence, not value.
Signed-off-by: Luca Ceresoli <luca.ceresoli@comelit.it>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Albert Aribaud <albert.aribaud@free.fr>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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The reset sequence/configuration for ehci is highly board specific,
so this will be done in the source for the board, instead of
introducing several CONFIG_* which would be needed to make those
few lines in beagle.c usable across different OMAP boards.
Signed-off-by: Alexander Holler <holler@ahsoftware.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Signed-off-by: Alexander Holler <holler@ahsoftware.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
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Fix include path of timer fttmr010 in a320evb.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
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Move the header file and definitions of fttmr010
power control unit from a320 SoC folder to
"include/faraday" folder.
This change will let other SoC which also use fttmr010
could share the same header file.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
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Add i2c support to aspenite board with Armada100 soc.
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Lei Wen <leiwen@marvell.com>
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Add i2c support to dkb board with pantheon soc.
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Lei Wen <leiwen@marvell.com>
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Add i2c_clk_enable in the cpu specific code, since previous platform it,
while new platform don't need. In the pantheon and armada100 platform,
this function is defined as NULL one.
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Lei Wen <leiwen@marvell.com>
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For better sharing with other platform other than pxa's,
it is more convenient to put the driver to the common place.
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Lei Wen <leiwen@marvell.com>
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ftpmu010 related code has been moved to drivers/power/.
Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
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Using optimized versions of memset and memcpy from linux brings a quite
noticeable speed (x2 or better) improvement for these two functions.
Here are some numbers for test done with jadecpu
| HEAD(1)| HEAD(1)| HEAD(2)| HEAD(2)|
| | +patch | | +patch |
---------------------------+--------+--------+--------+--------+
Reset to prompt | 438ms | 330ms | 228ms | 120ms |
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TFTP a 3MB img | 4782ms | 3428ms | 3245ms | 2820ms |
| | | | |
FATLOAD USB a 3MB img* | 8515ms | 8510ms | ------ | ------ |
| | | | |
BOOTM LZO img in RAM | 3473ms | 3168ms | 592ms | 592ms |
where CRC is | 615ms | 615ms | 54ms | 54ms |
uncompress | 2460ms | 2462ms | 450ms | 451ms |
final boot_elf | 376ms | 68ms | 65ms | 65ms |
| | | | |
BOOTM LZO img in FLASH | 3207ms | 2902ms | 1050ms | 1050ms |
where CRC is | 600ms | 600ms | 135ms | 135ms |
uncompress | 2209ms | 2211ms | 828ms | 828ms |
| | | | |
Copy 1.4MB from NOR to RAM | 134ms | 72ms | 120ms | 70ms |
(1) No dcache
(2) dcache enabled in board_init
*Does not work when dcache is on
Size impact:
C version:
text data bss dec hex filename
202862 18912 266456 488230 77326 u-boot
ASM version:
text data bss dec hex filename
203798 18912 266288 488998 77626 u-boot
222712 u-boot.bin
Signed-off-by: Matthias Weisser <weisserm@arcor.de>
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This allows the reading of EEPROMS on the expansion bus without adding
external pull-ups.
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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Drop warnings due to recent commit
ARM: mx31: Print the silicon version
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
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factor out boot cause function to common code to avoid
the duplicate code in each board support package
Signed-off-by: Jason Liu <jason.hui@linaro.org>
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Commit 5d2c154 (IMX: MX31: Cleanup include files and drop nasty #ifdef in drivers)
renamed mx31-imx-regs.h to imx-regs.h.
Change the file label accordingly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Detlev Zundel <dzu@denx.de>
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Use the same method of the Linux kernel to print the MX31 silicon version on
boot.
Tested on a MX31PDK with a 2.0 silicon, where it shows:
CPU: Freescale i.MX31 rev 2.0 at 531 MHz
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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As exception among the i.MX processors, the i.MX31 has headers
without general names (mx31-regs.h, mx31.h instead of imx-regs.h and
clock.h). This requires several nasty #ifdef in the drivers to
include the correct header. The patch cleans up the driver and
renames the header files as for the other i.MX processors.
Signed-off-by: Stefano Babic <sbabic@denx.de>
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Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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The patch add CONFIG_HW_WATCHDOG to be used
with the internal watchdog timer of the MX31
processor. Two function are exported for the
board maintainers:
mxc_hw_watchdog_enable
mxc_hw_watchdog_reset
The board maintainer can decide to use mxc_hw_watchdog_reset as
hw_watchdog_reset, or to implement his own function to reset
the watchdog.
The watchdog timer can be configured with CONFIG_SYS_WD_TIMER_SECS
(value in seconds). The MX31 allows values between 0.5
(CONFIG_SYS_WD_TIMER_SECS = 0) and 128 seconds.
Signed-off-by: Stefano Babic <sbabic@denx.de>
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The fsl_phy_enet_if enum was, essentially, the phy_interface_t enum.
This meant that drivers which used fsl_phy_enet_if to deal with
PHY interfaces would have to convert between the two (or we would have
to have them mirror each other, and deal with the ensuing maintenance
headache). Instead, we switch all clients of fsl_phy_enet_if over to
phy_interface_t, which should become the standard, anyway.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Acked-by: Detlev Zundel <dzu@denx.de>
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This converts tsec to use the new PHY Lib. All of the old PHY support
is ripped out. The old MDIO driver is split off, and placed in
fsl_mdio.c. The initialization is modified to initialize the MDIO
driver as well. The powerpc config file is modified to configure PHYLIB
if TSEC_ENET is configured.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Detlev Zundel <dzu@denx.de>
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The Blackfin gpio command isn't terribly Blackfin-specific. So generalize
the few pieces into two new optional helpers:
name_to_gpio() - turn a string name into a GPIO #
gpio_status() - display current pin bindings (think /proc/gpio)
Once these pieces are pulled out, we can relocate the cmd_gpio.c into the
common directory.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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This reverts commit 39768f7715ed637ef02f49fc7de664cc1aaf14b3.
Reson: it breaks a number of boards with embedded environment as the
code size grows in some places.
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Partial linking allows weak functions to be overridden in files containing
only one function. Moving the sc520 override of reset_cpu gets rid of an
ugly #ifdef
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
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Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
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Make the copyright notices in the x86 files consistent and update them with
proper attributions for recent updates
Also fix a few comment style/accuracy and whitespace/blank line issues
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
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By including <config.h> in the ld script, CONFIG_SYS_MONITOR_LEN (defined
in the boards config file) can be used in lieu of FLASH_SIZE (defined in
the board specific config.mk)
As this is the last remaining entry in the board specific config.mk, this
file can now be removed
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
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Rename STANDALONE_LOAD_ADDR into CONFIG_STANDALONE_LOAD_ADDR
and allow that the architecture-specific default value gets
overwritten by defining the value in the board header file.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Cc: Daniel Hellstrom <daniel@gaisler.com>
Cc: Tsi Chung Liew <tsi-chung.liew@freescale.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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Signed-off-by: Loïc Minier <loic.minier@linaro.org>
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-msingle-pic-base is a new gcc option for ppc and
it reduces the size of my u-boot with 6-8 KB.
While at it, add -fno-jump-tables too to save a
few more bytes.
-msingle-pic-base will be in gcc 4.6, however
backported patches are available at
http://bugs.gentoo.org/show_bug.cgi?id=347281
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
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The -fPIC flag belongs with -mrelocatable, move it there.
Also change -fPIC to -fpic as this produces smaller
binaries.
However, currently -mrelocatable promotes -fpic to -fPIC, a
fix for this is in upcoming gcc 4.6 or you can apply this small
patch to gcc:
diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h
index 8da8410..e4b8280 100644
--- a/gcc/config/rs6000/sysv4.h
+++ b/gcc/config/rs6000/sysv4.h
@@ -227,7 +227,8 @@ do { \
} \
\
else if (TARGET_RELOCATABLE) \
- flag_pic = 2; \
+ if (!flag_pic) \
+ flag_pic = 2; \
} while (0)
#ifndef RS6000_BI_ARCH
--
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
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Removed clearing of L2 cache as SRAM as it is not necessary without ECC.
This also speeds up the booting process.
Signed-off-by: Fabian Cenedese <cenedese@indel.ch>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark
level register description has been changed:
9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00
25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and
PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as
1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from
CPC after PBL completes RCW and PBI phases.
Signed-off-by: Chunhe Lan <b25806@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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For soc which have pin multiplex relation, some of them can't enable
simultaneously. This patch add environment var 'hwconfig' content
defination for them. you can enable some one function by setting
environment var 'hwconfig' content and reset board. Detail setting
please refer doc/README.p1022ds
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Remove the SERDES8 erratum work-around code that only applied to P4080
rev1, which is not supported by this version of U-Boot.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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