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* powerpc: add support for the Freescale P1022DS reference boardTimur Tabi2010-07-16-0/+169
| | | | | | | | | | | | | Specifics: 1) 36-bit only 2) Booting from NOR flash only 3) Environment stored in NOR flash only 4) No SPI support 5) No DIU support Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl: add LAW target to fsl_pci_info structureTimur Tabi2010-07-16-8/+11
| | | | | | | | | | | | | Add the LAW target (enum law_trgt_if) to the fsl_pci_info structure, so that we can capture the LAW target for a given PCI or PCIE controller. Also update the SET_STD_PCI_INFO and SET_STD_PCIE_INFO macros to assign the LAW_TRGT_IF_PCI[E]_x macro to the LAW target field of the structure. This will allow future PCI[E] code to configure the LAW target automatically, rather than requiring each board to it for each PCI controller separately. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add support for link stack & STAC on e5500Kumar Gala2010-07-16-1/+3
| | | | | | | | The e5500 has a link register stack and segment target address cache. Its safe to enable these bits on older e500 cores as the bits are implemented in the register. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add recognition of e5500 coreKumar Gala2010-07-16-10/+18
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc 83xx/85xx: Merge lbc upmconfig codeBecky Bruce2010-07-16-127/+53
| | | | | | | | | | Each platform had its own version of the upmconfig, despite the init process being identical. Now that we have a spot for common lbc code, create a common upmconfig() there. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Add reginfo commandBecky Bruce2010-07-16-0/+13
| | | | | | | | The new command dumps the TLBCAM, the LAWs, and the BR/OR regs. Add CONFIG_CMD_REGINFO to the config for all MPC85xx parts. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* drivers/misc/fsl_law.c: Rearrange code to avoid duplicationBecky Bruce2010-07-16-0/+1
| | | | | | | | The current code redefines functions based on FSL_CORENET_ vs not - create macros/inlines instead that hide the differences. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Add print_tlbcam() functionBecky Bruce2010-07-16-0/+21
| | | | | | | This dumps out the contents of TLB1 on 85xx-based systems. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: tlb.c cleanupsBecky Bruce2010-07-16-26/+25
| | | | | | | | | | | Extract the operation to read a tlb into a function - we will need this later to print out the tlbs, and there's no point in duplicating the code. Create a TSIZE_TO_BYTES macro to deal with the conversion from the MAS field to an actual size instead of duplicating this in code. There are a few misc other minor cleanups. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 83xx/85xx/86xx: LBC register cleanupBecky Bruce2010-07-16-339/+196
| | | | | | | | | | | | | | | | | | | | | Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Add is_core_disabled to remove disabled cores from dtbKumar Gala2010-07-16-7/+50
| | | | | | | If we explicitly disabled a core remove it from the dtb we pass on to the kernel. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc8xxx: Remove cpu-handles for cpus we deleteKumar Gala2010-07-16-6/+30
| | | | | | | We may have cpu-handles pointing to the cpu nodes we delete. If so we should delete the handles as well. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Add base support for the SEC4Kim Phillips2010-07-16-1/+47
| | | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Distinguish between incompatible SEC h/w typesKim Phillips2010-07-16-3/+10
| | | | | | | | | CONFIG_SYS_FSL_SEC_COMPAT is set to 2 for the SEC 2.x and SEC 3.x. Parts with newer SEC h/w versions will increment the number to accomodate incompatible code changes. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fdt: move fsl specific code from common fdt area to mpc8xxx/fdt.cKim Phillips2010-07-16-3/+137
| | | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'next' of git://git.denx.de/u-boot-niosWolfgang Denk2010-07-14-0/+30
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| * nios2: add gpio_requestThomas Chou2010-07-12-0/+6
| | | | | | | | | | | | | | This will be used by nand_plat. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * nios2: add fdt supportThomas Chou2010-07-12-0/+21
| | | | | | | | | | | | | | | | This patch adds fdt support to boot linux, followed Michal's work on microblaze. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * nios2: use gc sections to reduce image sizeThomas Chou2010-07-12-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Follow the discussion of Charles Manning and Mike Frysinger. Using gc_sections helps reduce image size. Configuring for nios2-generic board... Before, text data bss dec hex filename 123979 3724 22892 150595 24c43 /tmp/u-boot/u-boot After, text data bss dec hex filename 115983 3800 22732 142515 22cb3 /tmp/u-boot/u-boot Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2010-07-14-13/+35
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| * | mpc8308: support for Freescale MPC8308 cpuIlya Yanok2010-07-09-13/+35
| |/ | | | | | | | | | | | | | | | | | | This patch adds basic support for Freescale MPC8308 CPU. Serial ports, NOR flash and integrated Ethernet controllers are supported. PCI Express is also supported. eSDHC, NAND and USB may work but aren't tested (using ULPI PHY requires additional patch). Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-netWolfgang Denk2010-07-14-2/+19
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| * | mvgbe: add support for orion5x GbE controllerAlbert Aribaud2010-07-12-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add definitions and initialization in orion5x for mvgbe. Add orion5x in mvgbe SoC includes. Signed-off-by: Albert Aribaud <albert.aribaud@free.fr> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | mvgbe: support SoCs other than kirkwoodAlbert Aribaud2010-07-12-2/+5
| |/ | | | | | | | | | | | | | | | | Rename all references to kirkwood in mvgbe symbols throughout the whole codebase. Signed-off-by: Albert Aribaud <albert.aribaud@free.fr> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | Blackfin: bf561: use DMA for Core B L1 regionsMike Frysinger2010-07-13-1/+9
| | | | | | | | | | | | | | The L1 regions of Core B are not directly accessible from Core A, so we need to use DMA to get at them. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: serial: convert to portmux frameworkMike Frysinger2010-07-13-0/+19
| | | | | | | | | | | | | | | | Use the new portmux framework to handle the details when possible. Unfortunately, we cannot yet use this in the standalone initialization logic, so we need to keep around the old portmux writes for now. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: unify custom gpio commandsMike Frysinger2010-07-05-0/+121
| | | | | | | | | | | | | | Now that we have a unified gpio layer, the misc partial gpio commands can be unified and made complete (support all possible gpios). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: import gpio/portmux layer from LinuxMike Frysinger2010-07-05-0/+3561
| | | | | | | | | | | | | | | | | | The current pinmux handling has spread throughout Blackfin drivers and board code and is getting hideous to maintain. So import the gpio and portmux layer from the Blackfin Linux code. This should spur a serious of cleanups across the Blackfin tree. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: set up simple NMI handlers for anomaly 05000219Mike Frysinger2010-07-05-1/+34
| | | | | | | | | | | | | | Older on-chip Blackfin bootroms do not create a dummy NMI handler, so set up one ourselves when anomaly 05000219 applies. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: update anomaly lists to latest sheetsMike Frysinger2010-07-05-183/+437
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: expand EVT1 usage documentation a bit moreMike Frysinger2010-07-05-1/+6
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: implement bootcount supportMike Frysinger2010-07-05-0/+35
| | | | | | | | | | | | | | | | The default storage location for bootcount is EVT0. This version uses one 32bit value and combines the magic/count value in the upper/lower 16bits. If there is demand for more, should be easy to do. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: clean up trace buffer handling when crashingMike Frysinger2010-07-05-28/+49
|/ | | | | | | | | | Avoid banging on the trace MMRs when debugging is disabled, avoid calling the funcs multiple times in a row, disable the trace buffer earlier in the exception handler to avoid eating more user entries, and dump the buffer before calling the kgdb hook. This way we maximize useful debugging info up front rather than needing external tools (like gdb/serial/etc...). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Make sure that argv[] argument pointers are not modified.Wolfgang Denk2010-07-04-97/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hush shell dynamically allocates (and re-allocates) memory for the argument strings in the "char *argv[]" argument vector passed to commands. Any code that modifies these pointers will cause serious corruption of the malloc data structures and crash U-Boot, so make sure the compiler can check that no such modifications are being done by changing the code into "char * const argv[]". This modification is the result of debugging a strange crash caused after adding a new command, which used the following argument processing code which has been working perfectly fine in all Unix systems since version 6 - but not so in U-Boot: int main (int argc, char **argv) { while (--argc > 0 && **++argv == '-') { /* ====> */ while (*++*argv) { switch (**argv) { case 'd': debug++; break; ... default: usage (); } } } ... } The line marked "====>" will corrupt the malloc data structures and usually cause U-Boot to crash when the next command gets executed by the shell. With the modification, the compiler will prevent this with an error: increment of read-only location '*argv' N.B.: The code above can be trivially rewritten like this: while (--argc > 0 && **++argv == '-') { char *arg = *argv; while (*++arg) { switch (*arg) { ... Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2010-07-04-53/+107
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| * ppc4xx: Cleanup Boot/FLASH TLB reassignment for PPC440/460Stefan Roese2010-07-01-15/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Background Info: Some PPC440/460 boards have caches enabled in the Boot/FLASH TLB (via init.S) to speed up the boot process. In relocate_code (start.S) the cache inhibit attribute for this TLB is set to disable cache. This is needed for the CFI FLASH driver. This patch now cleans this code up: - CONFIG_SYS_TLB_FOR_BOOT_FLASH is defined to 0 (default TLB) if not defined in the top of this file. This way, we can remove an ugly #ifdef in this code. - Replace complex "#if defined(CONFIG_440EP) || defined(CONFIG_GR)..." statement with "#if defined(CONFIG_440)". - Remove unnecessary cache invalidate calls resulting in faster bootup. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add DDR1/2 macros in ppc4xx-sdram.h for non-405EX as wellStefan Roese2010-07-01-1/+3
| | | | | | | | | | | | | | This patch adds some DDR(2) macros to all PPC4xx's equipped with this IBM DDR1/2 controller. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: DDR2: Complete RDSS configuration on non-SPD based boardsStefan Roese2010-07-01-14/+38
| | | | | | | | | | | | | | | | | | As described in item #10 of the SDRAM initialization (chapter 22.2.9 of the PPC460EX/EXr/GT users manual), RDSS may need to be adjusted. The code for this is now factored out and executed for non-SPD based boards as well. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Enable overwriting of default scan window for IBM DDR2 controllerStefan Roese2010-07-01-12/+10
| | | | | | | | | | | | | | | | | | | | | | This patch makes it possible to overwrite the default auto-calibration scan window (SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR] values) with board specific values. The parameters of the weak default function are corrected as well. This way we don't need the casts any more. This feature will be used by an upcoming PPC460GT board port. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Enable PCIe support without PCI support on PPC440/460Stefan Roese2010-07-01-1/+11
| | | | | | | | | | | | | | | | | | | | | | By not defining CONFIG_SYS_PCI_MASTER_INIT and CONFIG_SYS_PCI_TARGET_INIT, PCI support (host and adapter) will not be enabled. But it's still possible to use the U-Boot PCI infrastructure for the PCIe ports. This configuration option is needed for a new 460GT board, which uses PCIe but has PCI disabled. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Enable booting with Option E on 460EX/EXr/GTStefan Roese2010-07-01-10/+39
| | | | | | | | | | | | | | | | | | This patch enables booting with option E on the PPC460EX/EXr/GT. When booting with Option E, the PLL is in bypass, CPR0_PLLC[ENG]=0. The Software Boot Configuration Procedure is needed to engage the PLL and perform a chip reset. Signed-off-by: Stefan Roese <sr@denx.de>
* | USB OHCI support for at91sam9g45 SoCSergey Matyukevich2010-06-30-2/+12
|/ | | | | | | | | | Add USB OHCI support for at91sam9g45ekes/at91sam9m10g45ek boards. Note that according to errata from Atmel, OHCI is not operational on the first revision of at91sam9g45 chip. So this patch enables OHCI support for later revisions. Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
* Merge branch 'master' into nextWolfgang Denk2010-06-30-9/+12
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| * MPC512x: workaround data corruption for unaligned local bus accessesWolfgang Denk2010-06-29-9/+12
| | | | | | | | | | | | | | | | | | | | | | Commit 460c2ce3 "MPC5200: workaround data corruption for unaligned local bus accesses" fixed the problem for MPC5200 only, but MPC512x is affected as well, so apply the same fix here, too. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: Detlev Zundel <dzu@denx.de>
* | powerpc/bootcount: Add bootcount support for MPC512xMichael Weiss2010-06-29-0/+5
| | | | | | | | | | | | | | This also uses the breadcrumb register as on MPC5200. Signed-off-by: Michael Weiss <michael.weiss@ifm.com> Signed-off-by: Detlev Zundel <dzu@denx.de>
* | avr32: add unaligned.hAndreas Bießmann2010-06-29-0/+1
| | | | | | | | | | | | | | | | | | This patch fixes following error: zlib.c:31:27: error: asm/unaligned.h: No such file or directory Suggested-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
* | avr32: disable branch foldingAndreas Bießmann2010-06-29-3/+4
| | | | | | | | | | | | | | | | Due to a hardware bug mentioned in latest AP7000 datasheet errata (revision M from 09.09) branch folding is unreliable. This patch disables CPUCR.FE bitfield as stated in datasheet. Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
* | Fix (null) problem for AVR32 boardsReinhard Meyer (-VC)2010-06-29-2/+3
| | | | | | | | | | | | | | | | | | | | Currently the U-Boot address ranges for AVR32 boards are printed like this: "U-Boot code: (null) -> 0001183c data: 000188e8 -> 0004e9b0" This patch fixes this to print: "U-Boot code: 00000000 -> 0001183c data: 000188f8 -> 0004e9c0" Signed-off-by: Reinhard Meyer <info@emk-elektronik.de>
* | Merge branch 'next' of git://git.denx.de/u-boot-ti into nextWolfgang Denk2010-06-29-1/+1
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| * | DaVinci: EMAC: Get EMAC_MDIO_PHY_NUM from config filesPrakash PM2010-06-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently EMAC_MDIO_PHY_NUM is defined as 1 in emac_defs.h. Because of this, EMAC does not work on EVMs which do not have phy connected at 1. Moving the macro to board config file makes this configurable depending on where the phy is connected on the MDIO bus. This patch fixes the board reset issue observed during network access on DM365EVM. EMAC driver was assuming EMAC_MDIO_PHY_NUM as 1 but it is 0 on DM365EVM. This patch is verified on da830/omap-l137, dm365 and dm644x evms. Signed-off-by: Prakash PM <prakash.pm@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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