summaryrefslogtreecommitdiff
path: root/arch
Commit message (Collapse)AuthorAgeLines
* omap4: sdram init changes for omap4460Aneesh V2011-08-03-19/+30
| | | | | Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: add omap4460 revision detectionAneesh V2011-08-03-0/+5
| | | | | Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* mkimage: Add OMAP boot image supportJohn Rigby2011-08-03-0/+30
| | | | | | | | | | - Add mkimage support for OMAP boot image - Add support for OMAP boot image(MLO) generation in the new SPL framework Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap: add MMC and FAT support to SPLAneesh V2011-08-03-2/+277
| | | | | | | | | | | | | | - Add MMC raw and FAT mode boot support for OMAP - Provide a means by which parameters passed by ROM-code can be saved in u-boot. - Save boot mode related information passed by OMAP4 ROM-code and use it to determine where to load the u-boot from - Assumes that the image has a mkimage header. Gets the payload size and load address from this header. If the header is not detected assume u-boot.bin as payload Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap: add basic SPL supportAneesh V2011-08-03-2/+201
| | | | | | | | | | | | | - Provide alternate implementations of board_init_f() board_init_r() for OMAP spl. - Provide linker script - Initialize global data - Add serial console support - Update CONFIG_SYS_TEXT_BASE to allow for SPL's bss and move it to board config header from config.mk Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* armv7: start.S: fixes and enhancements for SPLAneesh V2011-08-03-12/+39
| | | | | | | | | | | - Allow SPL to have .bss disjoint from rest of the image - Allow for .bss setup in CONFIG_SPL_BUILD case too. - Take care of the special case where relocation offset = 0. - Compile out exception handling code and install a simpler vector Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: automatic sdram detectionAneesh V2011-08-03-0/+238
| | | | | | | | | | | | | | | | | | | | | | | | | Identify SDRAM devices connected to EMIF automatically: LPDDR2 devices have some Mode Registers that provide details about the device such as the type, density, bus width etc. EMIF has the capability to read these registers. If there are no devices connected to a given chip-select reading mode registers will return junk values. After reading as many such registers as possible and matching with expected ranges of values the driver can identify if there is a device connected to the respective CS. If we identify that a device is connected the values read give us complete details about the device. This along with the base AC timings specified by JESD209-2 allows us to do a complete automatic initialization of SDRAM that works on all boards. Please note that the default AC timings specified by JESD209-2 will be safe for all devices but not necessarily optimal. However, for the Elpida devices used on Panda and SDP the default timings are both safe and optimal. Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: calculate EMIF register valuesAneesh V2011-08-03-10/+967
| | | | | | | | | | | | | | Calculate EMIF register values based on AC timing parameters from the SDRAM datasheet and the DDR frequency rather than using the hard-coded values. For a new board the user doen't have to go through the tedious process of calculating the register values. Instead, just provide the AC timings from the device data sheet as input and the driver will automatically calculate the register values. Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: add sdram init supportAneesh V2011-08-03-7/+1500
| | | | | | | Add support for the SDRAM controller (EMIF). Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: add clock supportAneesh V2011-08-03-0/+1486
| | | | | | | | | | | | | | Add support for: 1. DPLL locking 2. Initialization of clock domains and clock modules 3. Setting up the right voltage on voltage rails This work draws upon previous work done for x-loader by: Santosh Shilimkar <santosh.shilimkar@ti.com> Rajendra Nayak <rnayak@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: add OMAP4430 revision checkAneesh V2011-08-03-8/+97
| | | | | Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: cleanup pin mux dataAneesh V2011-08-03-4/+129
| | | | | | | | | | | | | - separate mux settings into essential and non essential parts - essential part is board independent as of now(so move it to SoC directory). Will help in having single SPL for all boards. - Non-essential part(the pins not essential for u-boot to function) need to be phased out eventually. - Correct mux data by aligning to the latest settings in x-loader Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap4: utility function to identify the context of hw initAneesh V2011-08-03-1/+82
| | | | | | | | | | | | | | | | The basic hardware init of OMAP4(s_init()) can happen in 4 different contexts: 1. SPL running from SRAM 2. U-Boot running from FLASH 3. Non-XIP U-Boot loaded to SDRAM by SPL 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the Configuration Header feature What level of hw initialization gets done depends on this context. Add a utility function to find this context. Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* DA8xx: fix LPSC constantsLaurence Withers2011-08-03-12/+31
| | | | | | | | | | Some of the LPSC constants were incorrect, and some were missing. This commit fixes the incorrect constants (which were not used anywhere in the tree) and adds all constants for both DA830 and DA850, as per the TI datasheets. Signed-off-by: Laurence Withers <lwithers@guralp.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* DA8xx: switch an enum to defines for consistencyLaurence Withers2011-08-03-41/+40
| | | | | | | | | | There are two main sets of LPSC constants, depending on the processor family. The DA8xx constants were given in an enum whereas the non-DA8xx constants were preprocessor defines. This commit switches the DA8xx constants to defines for consistency. Signed-off-by: Laurence Withers <lwithers@guralp.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* DA8xx: add MMC/SD controller addressesLaurence Withers2011-08-03-0/+2
| | | | | Signed-off-by: Laurence Withers <lwithers@guralp.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* DaVinci EMAC: declare function for all DA8xx CPUsLaurence Withers2011-08-03-1/+1
| | | | | | | | | | | | The function davinci_emac_mii_mode_sel() is defined in board/davinci/common/misc.c for any DA8xx CPU which has CONFIG_DRIVER_TI_EMAC enabled. However, the prototype was only being declared in <include/asm/arch/davinci_misc.h> for the DA850 EVM board. This patch declares it for all DA8xx CPUs where CONFIG_DRIVER_TI_EMAC is enabled. Signed-off-by: Laurence Withers <lwithers@guralp.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* DA8xx: add generic GPIO driverLaurence Withers2011-08-03-0/+8
| | | | | | | | | | | Add a generic GPIO driver for the DaVinci DA8xx processors. It is turned on by defining CONFIG_DA8XX_GPIO and fulfills the generic GPIO interface specified in <asm/gpio.h> . The driver has support for both manipulating GPIO pins as well as automatically configuring the pin multiplexor registers to set the pin function to GPIO. Signed-off-by: Laurence Withers <lwithers@guralp.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* DaVinci: rename gpio_defs.h to gpio.hLaurence Withers2011-08-03-0/+0
| | | | | | | | | In preparation for a generic GPIO driver for the DA8xx processors, rename <asm/arch/gpio_defs.h> to <asm/arch/gpio.h> and fix up all files which include it. Signed-off-by: Laurence Withers <lwithers@guralp.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* omap3: Include array definition only when it is usedSanjeev Premi2011-08-03-0/+3
| | | | | | | | | | | | The array of strings corresponding to cpu revision is used only when CONFIG_DISPLAY_CPUINFO is selected - in the function print_cpuinfo(). Enclose definition of this array in #ifdef...#endif for the same. Signed-off-by: Sanjeev Premi <premi@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2011-08-02-409/+758
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-blackfin: Blackfin: jtag-console: fix timer usage Blackfin: switch to common display_options() Blackfin: serial: move early debug strings into .rodata section Blackfin: adi boards: also set stderr to nc with helper Blackfin: update anomaly lists to latest public info Blackfin: serial: convert to bfin_{read,write} helpers Blackfin: split out async setup Blackfin: adi boards: enable pretty flash progress output Blackfin: drop unused dma.h header from start code Blackfin: portmux: allow header to be included in assembly files Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: enable mmc_spi support Blackfin: cm-bf537e/cm-bf537u/tcm-bf537: update network settings Blackfin: sync MMR read/write helpers with Linux Blackfin: gpio: optimize free path a little Blackfin: post: setup default CONFIG_SYS_POST_WORD_ADDR Blackfin: uart: fix printf warning Blackfin: add init.elf helper code Blackfin: dont reset SWRST on newer bf526 parts Blackfin: adi boards: enable multi serial support by default Blackfin: uart: add multiple serial support Blackfin: uart: move debug buffers into local bss
| * Blackfin: jtag-console: fix timer usageMike Frysinger2011-07-12-2/+2
| | | | | | | | | | Reported-by: Graeme Russ <graeme.russ@gmail.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: switch to common display_options()Mike Frysinger2011-07-12-1/+1
| | | | | | | | | | | | | | Use common code to output the version string rather than doing it ourselves. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: serial: move early debug strings into .rodata sectionMike Frysinger2011-07-12-5/+5
| | | | | | | | | | | | | | | | | | | | Rewrite the assembly serial_early_puts() helper to place the strings in the .rodata section rather than embedding them directly in the .text section. Using .text is a little simpler, but it doesn't let people execute out of internal L1 sram (since core reads don't work on those regions). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: update anomaly lists to latest public infoMike Frysinger2011-07-12-221/+335
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: serial: convert to bfin_{read,write} helpersMike Frysinger2011-07-12-17/+19
| | | | | | | | | | | | | | | | Since the serial struct declares the sizes for us, no need to hardcode them in the accessor functions. Let the bfin_{read,write} helpers do it for us. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: split out async setupMike Frysinger2011-07-12-50/+84
| | | | | | | | | | | | | | | | | | | | | | We really only need to tweak the async banks in the initcode if the processor is booting out of it, otherwise we can wait until later on in the CPU booting setup. This also makes testing in the sim and early bring up over JTAG work much smoother when the initcode gets bypassed. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: drop unused dma.h header from start codeMike Frysinger2011-07-12-1/+0
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: portmux: allow header to be included in assembly filesMike Frysinger2011-07-12-0/+4
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: sync MMR read/write helpers with LinuxMike Frysinger2011-07-12-46/+42
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: gpio: optimize free path a littleMike Frysinger2011-07-12-1/+4
| | | | | | | | | | | | | | | | | | When we aren't doing resource tracking, the gpio_free() function is a stub that simply returns, so pull this logic up a level and make it an inline stub in the header. Now we don't have to waste time at any of the call sites. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: post: setup default CONFIG_SYS_POST_WORD_ADDRMike Frysinger2011-07-12-0/+3
| | | | | | | | | | | | | | Set the default post word location to an L1 data location for all Blackfin parts so things "just work" for most people. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: uart: fix printf warningMike Frysinger2011-07-12-1/+1
| | | | | | | | | | | | | | The code uses %i to printf a size_t when it should use %zu, otherwise we get a warning from gcc about it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: add init.elf helper codeMike Frysinger2011-07-12-1/+43
| | | | | | | | | | | | | | | | | | This creates a standalone ELF that executes just the Blackfin initcode. This is useful for people who want to program the low level aspects of the CPU (memory/clocks/etc...) and can easily be used with JTAG for quick booting while developing. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: dont reset SWRST on newer bf526 partsMike Frysinger2011-07-12-1/+3
| | | | | | | | | | | | | | The bug in the BF526 rom when doing a software reset exists only in older silicon versions, so don't clear SWRST on newer parts. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: uart: add multiple serial supportMike Frysinger2011-07-12-55/+210
| | | | | | | | | | | | | | This brings CONFIG_SERIAL_MULTI support to the Blackfin on-chip UARTs. Ends up adding only ~512bytes per additional UART. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: uart: move debug buffers into local bssMike Frysinger2011-07-12-8/+3
| | | | | | | | | | | | | | There's no need for these saved buffers to be global symbols, or in the data section. So mark them static to move them into the bss. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-mipsWolfgang Denk2011-08-02-4/+15
|\ \ | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mips: README: update MIPS related informations MIPS: make cache operation mode configurable MIPS: rename INFINEON_EBU_BOOTCFG to CONFIG_SYS_XWAY_EBU_BOOTFG MIPS: INCA-IP: rename inca-swap-bytes host tool
| * | MIPS: make cache operation mode configurableDaniel Schwierzeck2011-07-31-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the cache operation mode is hard-coded to CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs which operate at a different mode. This patch makes the cache operation mode configurable via board config. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Acked-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
| * | MIPS: rename INFINEON_EBU_BOOTCFG to CONFIG_SYS_XWAY_EBU_BOOTFGDaniel Schwierzeck2011-07-31-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | This define is a board-specific config option and should be renamed to follow the U-Boot naming convention. Additionally, add an explaining comment for this option. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Acked-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
* | | Unify timer_init() and cpu_init() prototypesWolfgang Denk2011-08-01-35/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up some duplicated prototype declarations. Get rid of now useless AVR32 initcalls.h file. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.aribaud@free.fr> Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Cc: Graeme Russ <graeme.russ@gmail.com>
* | | ARM: fix error: conflicting types for 'setenv'seedshope2011-08-01-8/+0
|/ / | | | | | | | | | | | | | | | | Also remove bogus comment. Signed-off-by: Zhong hongbo <bocui107@gmail.com> Changed commit message Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.aribaud@free.fr>
* | powerpc/8xxx: Remove dependency on <usb.h>Kumar Gala2011-07-29-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We used <usb.h> for USB_MAX_DEVICE. However this requires we actual build in support for USB into u-boot (which should not be required for device tree fixup). At this time no FSL SoC that utilizies this code (83xx/85xx) has more than 2 USB controllers. So we replace USB_MAX_DEVICE with a local define FSL_MAX_NUM_USB_CTRLS. If/when a device shows up with more than 2 controllers we can easily bump this value or refactor into a proper define per SoC. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: enable USB2 gadget mode for corenet ds boardShaohui Xie2011-07-29-2/+0
| | | | | | | | | | | | | | | | | | | | to make USB2 worked in gadget mode, we need to set it's 'dr_mode' to 'peripheral' in hwconfig, but driver starts scan from 'usb1', it'll break out if it cannot find 'usb1', so drop the 'else' clause to make driver scan all the 'usbx'. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: verify the device tree before booting LinuxTimur Tabi2011-07-29-0/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce ft_verify_fdt(), a function that is called after the device tree has been fixed up, that displays warning messages if there is a mismatch between the physical addresses of some devices that U-Boot has configured with what the device tree says the addresses are. This is a particular problem when booting a 36-bit device tree from a 32-bit U-Boot (or vice versa), because the physical address of CCSR is wrong in the device tree. When the operating system boots, no messages are displayed, so the user generally has no idea what's wrong. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | MPC8xxx: drop redundant boot messagesWolfgang Denk2011-07-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current code would print RAM size information like this: DRAM: DDR: 256 MiB (DDR1, 64-bit, CL=2, ECC off) Turn a number of printf()s into debug() to get rid of the redundant "DDR: " string like this: DRAM: 256 MiB (DDR1, 64-bit, CL=2, ECC off) Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Cleanup handling of PVR detection for e500/e500mc/e5500Kumar Gala2011-07-29-19/+17
| | | | | | | | | | | | | | | | At some point we broke the detection of e500v1 class cores. Fix that and simply the code to just utilize PVR_VER() to have a single case statement. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: Fix up clock_freq property in CAN node of dtsBhaskar Upadhaya2011-07-29-0/+3
| | | | | | | | | | | | | | | | | | Fix up the device tree property associated with the Flexcan clock frequency. This property is used to calculate the bit timing parameters for Flexcan. Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | powerpc/85xx: provide 85xx flush_icache for cmd_cacheMatthew McClintock2011-07-29-0/+2
| | | | | | | | | | | | | | | | This provides a function that will override the weak function flush_icache to let 85xx boards to flush the icache cc: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Matthew McClintock <msm@freescale.com>
* | powerpc/85xx: Handle the lack of L2 cache on P2040/P2040EKumar Gala2011-07-29-9/+37
| | | | | | | | | | | | | | | | | | | | The P2040/P2040E have no L2 cache. So we utilize the SVR to determine if we are one of these devices and skip the L2 init code in cpu_init.c and release. For the device tree we skip the updating of the L2 cache properties but we still update the chain of caches so the CPC/L3 node can be properly updated. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-12-06 22:21:56 +0000